linux-kernel - Re: [PATCH v2 07/20] clk: npcm8xx: add clock controller

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Message-ID: <CAP6Zq1j2+NciZqgYoDZ5DXNs_2NvfErQkKhW5CoePbrC7CQQkQ@mail.gmail.com>
Date:   Fri, 10 Jun 2022 01:42:42 +0300
From:   Tomer Maimon <tmaimon77@...il.com>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Arnd Bergmann <arnd@...db.de>,
        Avi Fishman <avifishman70@...il.com>,
        Benjamin Fair <benjaminfair@...gle.com>,
        Biju Das <biju.das.jz@...renesas.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Greg KH <gregkh@...uxfoundation.org>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        Jiri Slaby <jirislaby@...nel.org>,
        Joel Stanley <joel@....id.au>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Lubomir Rintel <lkundrak@...sk>,
        Marcel Ziswiler <marcel.ziswiler@...adex.com>,
        Michael Turquette <mturquette@...libre.com>,
        Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>,
        Olof Johansson <olof@...om.net>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Robert Hancock <robert.hancock@...ian.com>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Tali Perry <tali.perry1@...il.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Patrick Venture <venture@...gle.com>,
        Vinod Koul <vkoul@...nel.org>, Will Deacon <will@...nel.org>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        Nancy Yuen <yuenn@...gle.com>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        LINUXWATCHDOG <linux-watchdog@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 07/20] clk: npcm8xx: add clock controller

Hi Stephen,

Thanks for your comment, it will be addressed next patch set

On Fri, 10 Jun 2022 at 01:14, Stephen Boyd <sboyd@...nel.org> wrote:
>
> Quoting Tomer Maimon (2022-06-08 02:56:10)
> > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > new file mode 100644
> > index 000000000000..40340c3611b5
> > --- /dev/null
> > +++ b/drivers/clk/clk-npcm8xx.c
> > @@ -0,0 +1,756 @@
> [...]
> > +
> > +#define PLLCON_LOKI    BIT(31)
> > +#define PLLCON_LOKS    BIT(30)
> > +#define PLLCON_FBDV    GENMASK(27, 16)
> > +#define PLLCON_OTDV2   GENMASK(15, 13)
> > +#define PLLCON_PWDEN   BIT(12)
> > +#define PLLCON_OTDV1   GENMASK(10, 8)
> > +#define PLLCON_INDV    GENMASK(5, 0)
> > +
> > +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> > +                                                unsigned long parent_rate)
> > +{
> > +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> > +       unsigned long fbdv, indv, otdv1, otdv2;
> > +       unsigned int val;
> > +       u64 ret;
> > +
> > +       if (parent_rate == 0) {
> > +               pr_debug("%s: parent rate is zero", __func__);
>
> Missing newline.
>
> > +               return 0;
> > +       }
> > +
> > +       val = readl_relaxed(pll->pllcon);
> > +
> > +       indv = FIELD_GET(PLLCON_INDV, val);

Best regards,

Tomer