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Message-Id: <20220609024148.26527-1-gengcixi@gmail.com>
Date: Thu, 9 Jun 2022 10:41:48 +0800
From: Cixi Geng <gengcixi@...il.com>
To: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
orsonzhai@...il.com, baolin.wang7@...il.com, zhang.lyra@...il.com
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: [PATCH] include: dt-bindings: soc: Add global register header for UMS512
From: Cixi Geng <cixi.geng1@...soc.com>
Add global register header for UMS512.
Signed-off-by: Cixi Geng <cixi.geng1@...soc.com>
---
include/dt-bindings/soc/sprd,ums512-mask.h | 9525 ++++++++++++++++++++
include/dt-bindings/soc/sprd,ums512-regs.h | 2134 +++++
2 files changed, 11659 insertions(+)
create mode 100644 include/dt-bindings/soc/sprd,ums512-mask.h
create mode 100644 include/dt-bindings/soc/sprd,ums512-regs.h
diff --git a/include/dt-bindings/soc/sprd,ums512-mask.h b/include/dt-bindings/soc/sprd,ums512-mask.h
new file mode 100644
index 000000000000..84d509570c97
--- /dev/null
+++ b/include/dt-bindings/soc/sprd,ums512-mask.h
@@ -0,0 +1,9525 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Spreadtrum UMS512 SOC system global register file
+ *
+ * Copyright C 2022, Spreadtrum Communications Inc.
+ */
+
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_RSTN 0x8000000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_RUN 0x4000000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_PD 0x2000000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_VALID 0x1000000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_BG_RBIAS_MODE 0x800000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_TEST_SEL 0x600000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_BP_MODE 0x100000
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_DATA 0xffc00
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_BP_DATA 0x3ff
+#define MASK_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM_RESERVED 0xffff
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_THM1_1_THM_RSTN 0x8
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_THM1_1_THM_RUN 0x4
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_THM1_1_THM_PD 0x2
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_THM1_1_THM_RESERVED 0x1
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFS_ENK1 0x10
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFS_ENK2 0x8
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFS_TRCS 0x4
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFS_AT1 0x2
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFS_AT0 0x1
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_EFUSE4K_EFS_ENK1 0x2
+#define MASK_ANLG_PHY_G4_RF_DBG_SEL_ANALOG_EFUSE4K_EFS_ENK2 0x1
+#define MASK_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_CSI_PHY_POWER_CONTROL 0xffffffff
+#define MASK_AP_CLK_CORE_CGM_AP_APB_CFG_CGM_AP_APB_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_IPI_CFG_CGM_IPI_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_UART0_CFG_CGM_UART0_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_UART0_CFG_CGM_UART0_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_UART1_CFG_CGM_UART1_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_UART1_CFG_CGM_UART1_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_UART2_CFG_CGM_UART2_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_UART2_CFG_CGM_UART2_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_I2C0_CFG_CGM_I2C0_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_I2C0_CFG_CGM_I2C0_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_I2C1_CFG_CGM_I2C1_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_I2C1_CFG_CGM_I2C1_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_I2C2_CFG_CGM_I2C2_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_I2C2_CFG_CGM_I2C2_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_I2C3_CFG_CGM_I2C3_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_I2C3_CFG_CGM_I2C3_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_I2C4_CFG_CGM_I2C4_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_I2C4_CFG_CGM_I2C4_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_SPI0_CFG_CGM_SPI0_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_SPI0_CFG_CGM_SPI0_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_SPI0_CFG_CGM_SPI0_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_SPI1_CFG_CGM_SPI1_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_SPI1_CFG_CGM_SPI1_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_SPI1_CFG_CGM_SPI1_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_SPI2_CFG_CGM_SPI2_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_SPI2_CFG_CGM_SPI2_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_SPI2_CFG_CGM_SPI2_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_SPI3_CFG_CGM_SPI3_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_SPI3_CFG_CGM_SPI3_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_SPI3_CFG_CGM_SPI3_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_IIS0_CFG_CGM_IIS0_DIV 0x3f00
+#define MASK_AP_CLK_CORE_CGM_IIS0_CFG_CGM_IIS0_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_IIS1_CFG_CGM_IIS1_DIV 0x3f00
+#define MASK_AP_CLK_CORE_CGM_IIS1_CFG_CGM_IIS1_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_IIS2_CFG_CGM_IIS2_DIV 0x3f00
+#define MASK_AP_CLK_CORE_CGM_IIS2_CFG_CGM_IIS2_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_SIM_CFG_CGM_SIM_DIV 0x700
+#define MASK_AP_CLK_CORE_CGM_SIM_CFG_CGM_SIM_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_CE_CFG_CGM_CE_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_AP_EMMC_32K_CFG_CGM_AP_EMMC_32K_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_AP_SDIO0_32K_CFG_CGM_AP_SDIO0_32K_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_AP_SDIO1_32K_CFG_CGM_AP_SDIO1_32K_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_AP_SDIO2_32K_CFG_CGM_AP_SDIO2_32K_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_AP_SIM_32K_CFG_CGM_AP_SIM_32K_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_SDIO0_2X_CFG_CGM_SDIO0_2X_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_SDIO1_2X_CFG_CGM_SDIO1_2X_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_EMMC_2X_CFG_CGM_EMMC_2X_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_VSP_CFG_CGM_VSP_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_DISPC0_CFG_CGM_DISPC0_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_DISPC0_DPI_CFG_CGM_DISPC0_DPI_DIV 0xf00
+#define MASK_AP_CLK_CORE_CGM_DISPC0_DPI_CFG_CGM_DISPC0_DPI_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_DSI_APB_CFG_CGM_DSI_APB_SEL 0x3
+#define MASK_AP_CLK_CORE_CGM_DSI_RXESC_CFG_CGM_DSI_RXESC_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_DSI_LANEBYTE_CFG_CGM_DSI_LANEBYTE_PAD_SEL 0x10000
+#define MASK_AP_CLK_CORE_CGM_VDSP_CFG_CGM_VDSP_SEL 0x7
+#define MASK_AP_CLK_CORE_CGM_VDSP_M_CFG_CGM_VDSP_M_DIV 0x300
+#define MASK_AP_CLK_CORE_CGM_DPHY_REF_CFG_CGM_DPHY_REF_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_DPHY_CFG_CFG_CGM_DPHY_CFG_SEL 0x1
+#define MASK_AP_CLK_CORE_CGM_DSI_PHY_SCAN_ONLY_CFG_CGM_DSI_PHY_SCAN_ONLY_SEL 0x1
+#define MASK_AP_AHB_RF_BUSMON_CLOCK_EB 0x100
+#define MASK_AP_AHB_RF_CKG_EB 0x80
+#define MASK_AP_AHB_RF_IPI_EB 0x40
+#define MASK_AP_AHB_RF_DMA_EB 0x20
+#define MASK_AP_AHB_RF_DMA_ENABLE 0x10
+#define MASK_AP_AHB_RF_VDMA_EB 0x8
+#define MASK_AP_AHB_RF_VSP_EB 0x4
+#define MASK_AP_AHB_RF_DISPC_EB 0x2
+#define MASK_AP_AHB_RF_DSI_EB 0x1
+#define MASK_AP_AHB_RF_DISPC_VAU_SOFT_RST 0x4000
+#define MASK_AP_AHB_RF_VSP_SOFT_RST 0x2000
+#define MASK_AP_AHB_RF_VPP_SOFT_RST 0x1000
+#define MASK_AP_AHB_RF_VSP_GLOBAL_SOFT_RST 0x800
+#define MASK_AP_AHB_RF_VDSP_DEBUG_SOFT_RST 0x400
+#define MASK_AP_AHB_RF_VDSP_SOFT_RST 0x200
+#define MASK_AP_AHB_RF_DMA_SOFT_RST 0x100
+#define MASK_AP_AHB_RF_VDMA_SOFT_RST 0x80
+#define MASK_AP_AHB_RF_IPI_SOFT_RST 0x40
+#define MASK_AP_AHB_RF_VDMA_VAU_SOFT_RST 0x20
+#define MASK_AP_AHB_RF_VDSP_MSTI_VAU_SOFT_RST 0x10
+#define MASK_AP_AHB_RF_VDSP_MSTD_VAU_SOFT_RST 0x8
+#define MASK_AP_AHB_RF_VDSP_IDMA_VAU_SOFT_RST 0x4
+#define MASK_AP_AHB_RF_DISPC_SOFT_RST 0x2
+#define MASK_AP_AHB_RF_DSI_SOFT_RST 0x1
+#define MASK_AP_AHB_RF_AXI_LP_CTRL_DISABLE 0x8
+#define MASK_AP_AHB_RF_PERI_FORCE_ON 0x4
+#define MASK_AP_AHB_RF_PERI_FORCE_OFF 0x2
+#define MASK_AP_AHB_RF_CGM_CLK_AP_AXI_AUTO_GATE_EN 0x1
+#define MASK_AP_AHB_RF_AP_MAINMTX_LP_DISABLE 0x40
+#define MASK_AP_AHB_RF_AP_AHB_AUTO_GATE_EN 0x20
+#define MASK_AP_AHB_RF_AP_EMC_AUTO_GATE_EN 0x10
+#define MASK_AP_AHB_RF_HOLDING_PEN 0xffffffff
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_SDIO2 0x200
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_SDIO1 0x100
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_SDIO0 0x80
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_EMMC 0x40
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_APCPU 0x20
+#define MASK_AP_AHB_RF_AP_AXI_BUS_IDLE_BYPASS_DMA 0x10
+#define MASK_AP_AHB_RF_AP_APB_AUTO_CONTROL_SEL 0x8
+#define MASK_AP_AHB_RF_AP_APB_AUTO_MUX_SEL 0x6
+#define MASK_AP_AHB_RF_AP_APB_AUTO_MUX_EN 0x1
+#define MASK_AP_AHB_RF_VDSP_M_FRC_OFF 0x40000000
+#define MASK_AP_AHB_RF_VDSP_FRC_OFF 0x20000000
+#define MASK_AP_AHB_RF_VSP_FRC_OFF 0x10000000
+#define MASK_AP_AHB_RF_SIM0_32K_FRC_OFF 0x8000000
+#define MASK_AP_AHB_RF_SDIO2_32K_FRC_OFF 0x4000000
+#define MASK_AP_AHB_RF_SDIO1_32K_FRC_OFF 0x2000000
+#define MASK_AP_AHB_RF_SDIO0_32K_FRC_OFF 0x1000000
+#define MASK_AP_AHB_RF_EMMC_32K_FRC_OFF 0x800000
+#define MASK_AP_AHB_RF_CE_FRC_OFF 0x400000
+#define MASK_AP_AHB_RF_IIS2_FRC_OFF 0x200000
+#define MASK_AP_AHB_RF_IIS1_FRC_OFF 0x100000
+#define MASK_AP_AHB_RF_IIS0_FRC_OFF 0x80000
+#define MASK_AP_AHB_RF_SPI3_FRC_OFF 0x40000
+#define MASK_AP_AHB_RF_SPI2_FRC_OFF 0x20000
+#define MASK_AP_AHB_RF_SPI1_FRC_OFF 0x10000
+#define MASK_AP_AHB_RF_SPI0_FRC_OFF 0x8000
+#define MASK_AP_AHB_RF_I2C4_FRC_OFF 0x4000
+#define MASK_AP_AHB_RF_I2C3_FRC_OFF 0x2000
+#define MASK_AP_AHB_RF_I2C2_FRC_OFF 0x1000
+#define MASK_AP_AHB_RF_I2C1_FRC_OFF 0x800
+#define MASK_AP_AHB_RF_I2C0_FRC_OFF 0x400
+#define MASK_AP_AHB_RF_UART2_FRC_OFF 0x200
+#define MASK_AP_AHB_RF_UART1_FRC_OFF 0x100
+#define MASK_AP_AHB_RF_UART0_FRC_OFF 0x80
+#define MASK_AP_AHB_RF_AP_APB_FRC_OFF 0x40
+#define MASK_AP_AHB_RF_EMMC_1X_FRC_OFF 0x20
+#define MASK_AP_AHB_RF_EMMC_2X_FRC_OFF 0x10
+#define MASK_AP_AHB_RF_SDIO1_1X_FRC_OFF 0x8
+#define MASK_AP_AHB_RF_SDIO1_2X_FRC_OFF 0x4
+#define MASK_AP_AHB_RF_SDIO0_1X_FRC_OFF 0x2
+#define MASK_AP_AHB_RF_SDIO0_2X_FRC_OFF 0x1
+#define MASK_AP_AHB_RF_IPI_FRC_OFF 0x40
+#define MASK_AP_AHB_RF_SIM_FRC_OFF 0x20
+#define MASK_AP_AHB_RF_DSI_APB_FRC_OFF 0x10
+#define MASK_AP_AHB_RF_DPHY_CFG_FRC_OFF 0x8
+#define MASK_AP_AHB_RF_DPHY_REF_FRC_OFF 0x4
+#define MASK_AP_AHB_RF_DISP_DPI_FRC_OFF 0x2
+#define MASK_AP_AHB_RF_DISP_FRC_OFF 0x1
+#define MASK_AP_AHB_RF_VDSP_M_FRC_ON 0x40000000
+#define MASK_AP_AHB_RF_VDSP_FRC_ON 0x20000000
+#define MASK_AP_AHB_RF_VSP_FRC_ON 0x10000000
+#define MASK_AP_AHB_RF_SIM0_32K_FRC_ON 0x8000000
+#define MASK_AP_AHB_RF_SDIO2_32K_FRC_ON 0x4000000
+#define MASK_AP_AHB_RF_SDIO1_32K_FRC_ON 0x2000000
+#define MASK_AP_AHB_RF_SDIO0_32K_FRC_ON 0x1000000
+#define MASK_AP_AHB_RF_EMMC_32K_FRC_ON 0x800000
+#define MASK_AP_AHB_RF_CE_FRC_ON 0x400000
+#define MASK_AP_AHB_RF_IIS2_FRC_ON 0x200000
+#define MASK_AP_AHB_RF_IIS1_FRC_ON 0x100000
+#define MASK_AP_AHB_RF_IIS0_FRC_ON 0x80000
+#define MASK_AP_AHB_RF_SPI3_FRC_ON 0x40000
+#define MASK_AP_AHB_RF_SPI2_FRC_ON 0x20000
+#define MASK_AP_AHB_RF_SPI1_FRC_ON 0x10000
+#define MASK_AP_AHB_RF_SPI0_FRC_ON 0x8000
+#define MASK_AP_AHB_RF_I2C4_FRC_ON 0x4000
+#define MASK_AP_AHB_RF_I2C3_FRC_ON 0x2000
+#define MASK_AP_AHB_RF_I2C2_FRC_ON 0x1000
+#define MASK_AP_AHB_RF_I2C1_FRC_ON 0x800
+#define MASK_AP_AHB_RF_I2C0_FRC_ON 0x400
+#define MASK_AP_AHB_RF_UART2_FRC_ON 0x200
+#define MASK_AP_AHB_RF_UART1_FRC_ON 0x100
+#define MASK_AP_AHB_RF_UART0_FRC_ON 0x80
+#define MASK_AP_AHB_RF_AP_APB_FRC_ON 0x40
+#define MASK_AP_AHB_RF_EMMC_1X_FRC_ON 0x20
+#define MASK_AP_AHB_RF_EMMC_2X_FRC_ON 0x10
+#define MASK_AP_AHB_RF_SDIO1_1X_FRC_ON 0x8
+#define MASK_AP_AHB_RF_SDIO1_2X_FRC_ON 0x4
+#define MASK_AP_AHB_RF_SDIO0_1X_FRC_ON 0x2
+#define MASK_AP_AHB_RF_SDIO0_2X_FRC_ON 0x1
+#define MASK_AP_AHB_RF_IPI_FRC_ON 0x40
+#define MASK_AP_AHB_RF_SIM_FRC_ON 0x20
+#define MASK_AP_AHB_RF_DSI_APB_FRC_ON 0x10
+#define MASK_AP_AHB_RF_DPHY_CFG_FRC_ON 0x8
+#define MASK_AP_AHB_RF_DPHY_REF_FRC_ON 0x4
+#define MASK_AP_AHB_RF_DISP_DPI_FRC_ON 0x2
+#define MASK_AP_AHB_RF_DISP_FRC_ON 0x1
+#define MASK_AP_AHB_RF_DPHY_REF_CKG_EN 0x2
+#define MASK_AP_AHB_RF_DPHY_CFG_CKG_EN 0x1
+#define MASK_AP_AHB_RF_VDSP_ASYNC_BRG_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_VDSP_ASYNC_BRG_LP_NUM 0x1fffe
+#define MASK_AP_AHB_RF_VDSP_ASYNC_BRG_LP_EB 0x1
+#define MASK_AP_AHB_RF_DISP_ASYNC_BRG_PU_NUM 0x7f80000
+#define MASK_AP_AHB_RF_DISP_CSYSACK_SYNC_SEL 0x40000
+#define MASK_AP_AHB_RF_DISP_CACTIVE_SYNC_SEL 0x20000
+#define MASK_AP_AHB_RF_DISP_ASYNC_BRG_LP_NUM 0x1fffe
+#define MASK_AP_AHB_RF_DISP_ASYNC_BRG_LP_EB 0x1
+#define MASK_AP_AHB_RF_MAIN_S6_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S6_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S6_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S6_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S5_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S5_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S5_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S5_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_AP_ASYNC_BRG_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_AP_ASYNC_BRG_LP_NUM 0x1fffe
+#define MASK_AP_AHB_RF_AP_ASYNC_BRG_LP_EB 0x1
+#define MASK_AP_AHB_RF_MAIN_M0_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M1_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M2_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M2_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M2_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M3_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M3_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M3_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M4_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M4_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M4_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M5_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M5_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M5_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M6_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M6_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M6_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_M7_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MAIN_M7_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_M7_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MATRIX_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S0_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S0_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S1_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S1_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S2_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S2_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S2_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S2_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S3_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S3_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S3_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S3_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S4_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S4_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S4_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S4_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_M0_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_M0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_M0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_M1_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_M1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_M1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MAIN_S7_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MTX_S7_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MAIN_S7_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MAIN_S7_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_S0_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MERGE_S0_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MERGE_S0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_S0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_ARQOS_CE 0xf00000
+#define MASK_AP_AHB_RF_AWQOS_CE 0xf0000
+#define MASK_AP_AHB_RF_ARQOS_DMA 0xf000
+#define MASK_AP_AHB_RF_AWQOS_DMA 0xf00
+#define MASK_AP_AHB_RF_ARQOS_SDIO0 0xf0000000
+#define MASK_AP_AHB_RF_AWQOS_SDIO0 0xf000000
+#define MASK_AP_AHB_RF_ARQOS_SDIO1 0xf00000
+#define MASK_AP_AHB_RF_AWQOS_SDIO1 0xf0000
+#define MASK_AP_AHB_RF_ARQOS_SDIO2 0xf000
+#define MASK_AP_AHB_RF_AWQOS_SDIO2 0xf00
+#define MASK_AP_AHB_RF_ARQOS_EMMC 0xf0
+#define MASK_AP_AHB_RF_AWQOS_EMMC 0xf
+#define MASK_AP_AHB_RF_ARQOS_THRESHHOLD_VDSP 0xf0000000
+#define MASK_AP_AHB_RF_AWQOS_THRESHHOLD_VDSP 0xf000000
+#define MASK_AP_AHB_RF_ARQOS_THRESHHOLD_MAIN 0xf00000
+#define MASK_AP_AHB_RF_AWQOS_THRESHHOLD_MAIN 0xf0000
+#define MASK_AP_AHB_RF_ARQOS_THRESHHOLD_MERGE 0xf000
+#define MASK_AP_AHB_RF_AWQOS_THRESHHOLD_MERGE 0xf00
+#define MASK_AP_AHB_RF_ARQOS_THRESHHOLD_DISP 0xf0
+#define MASK_AP_AHB_RF_AWQOS_THRESHHOLD_DISP 0xf
+#define MASK_AP_AHB_RF_AXI_DETECTOR_OVERFLOW_AP 0x20
+#define MASK_AP_AHB_RF_AXI_DETECTOR_OVERFLOW_DISP 0x10
+#define MASK_AP_AHB_RF_AXI_DETECTOR_OVERFLOW_VDSP 0x8
+#define MASK_AP_AHB_RF_BRIDGE_TRANS_IDLE_AP 0x4
+#define MASK_AP_AHB_RF_BRIDGE_TRANS_IDLE_DISP 0x2
+#define MASK_AP_AHB_RF_BRIDGE_TRANS_IDLE_VDSP 0x1
+#define MASK_AP_AHB_RF_DISP_BRIDGE_DEBUG_SIGNAL_W 0xffffffff
+#define MASK_AP_AHB_RF_AP_BRIDGE_DEBUG_SIGNAL_W 0xffffffff
+#define MASK_AP_AHB_RF_VDSP_BRIDGE_DEBUG_SIGNAL_W 0xffffffff
+#define MASK_AP_AHB_RF_ARQOS_VDSP_MSTI 0xf0000000
+#define MASK_AP_AHB_RF_ARQOS_VDSP_MSTD 0xf00000
+#define MASK_AP_AHB_RF_AWQOS_VDSP_MSTD 0xf0000
+#define MASK_AP_AHB_RF_ARQOS_VDSP_IDMA 0xf000
+#define MASK_AP_AHB_RF_AWQOS_VDSP_IDMA 0xf00
+#define MASK_AP_AHB_RF_ARQOS_VDMA 0xf0
+#define MASK_AP_AHB_RF_AWQOS_VDMA 0xf
+#define MASK_AP_AHB_RF_ARQOS_VDSP_MSTI_SEL 0x40
+#define MASK_AP_AHB_RF_ARQOS_VDSP_MSTD_SEL 0x20
+#define MASK_AP_AHB_RF_AWQOS_VDSP_MSTD_SEL 0x10
+#define MASK_AP_AHB_RF_ARQOS_VDSP_IDMA_SEL 0x8
+#define MASK_AP_AHB_RF_AWQOS_VDSP_IDMA_SEL 0x4
+#define MASK_AP_AHB_RF_ARQOS_VDMA_SEL 0x2
+#define MASK_AP_AHB_RF_AWQOS_VDMA_SEL 0x1
+#define MASK_AP_AHB_RF_MERGE_VDSP_M0_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_M1_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_M2_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M2_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M2_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_M3_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M3_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_M3_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_MAIN_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MERGE_VDSP_MATRIX_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MERGE_VDSP_MAIN_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_MAIN_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_S0_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MERGE_VDSP_S0_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MERGE_VDSP_S0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_S0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDSP_S1_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MERGE_VDSP_S1_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MERGE_VDSP_S1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDSP_S1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDMA_M0_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDMA_M0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDMA_M0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDMA_M1_PU_NUM 0x1fe0000
+#define MASK_AP_AHB_RF_MERGE_VDMA_M1_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDMA_M1_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_MERGE_VDMA_S0_PU_NUM 0x3fc0000
+#define MASK_AP_AHB_RF_CGM_MERGE_VDMA_S0_AUTO_GATE_EN 0x20000
+#define MASK_AP_AHB_RF_MERGE_VDMA_S0_LP_EB 0x10000
+#define MASK_AP_AHB_RF_MERGE_VDMA_S0_LP_NUM 0xffff
+#define MASK_AP_AHB_RF_SYS_SOFT_RST_REQ_VDMA 0x8
+#define MASK_AP_AHB_RF_SYS_SOFT_RST_REQ_GSP 0x4
+#define MASK_AP_AHB_RF_SYS_SOFT_RST_REQ_DISP 0x2
+#define MASK_AP_AHB_RF_SYS_SOFT_RST_REQ_VSP 0x1
+#define MASK_AP_AHB_RF_ARCACHE_SDIO2 0xf0000000
+#define MASK_AP_AHB_RF_AWCACHE_SDIO2 0xf000000
+#define MASK_AP_AHB_RF_ARCACHE_SDIO1 0xf00000
+#define MASK_AP_AHB_RF_AWCACHE_SDIO1 0xf0000
+#define MASK_AP_AHB_RF_ARCACHE_SDIO0 0xf000
+#define MASK_AP_AHB_RF_AWCACHE_SDIO0 0xf00
+#define MASK_AP_AHB_RF_ARCACHE_EMMC 0xf0
+#define MASK_AP_AHB_RF_AWCACHE_EMMC 0xf
+#define MASK_AP_AHB_RF_DISP_FRAME_LINE_SEL_FOR_DDR_DFS 0x200
+#define MASK_AP_AHB_RF_DISP_FRAME_LINE_SEL_FOR_DVFS 0x100
+#define MASK_AP_AHB_RF_MIPI_DSI_RESERVED 0x1fffe00
+#define MASK_AP_AHB_RF_MIPI_DSI_TX_RCTL 0x1e0
+#define MASK_AP_AHB_RF_MIPI_DSI_TRIMBG 0x1e
+#define MASK_AP_AHB_RF_MIPI_DSI_IF_SEL 0x1
+#define MASK_AP_AHB_RF_PRID 0xffff0000
+#define MASK_AP_AHB_RF_DBGEN 0x800
+#define MASK_AP_AHB_RF_NIDEN 0x400
+#define MASK_AP_AHB_RF_SPIDEN 0x200
+#define MASK_AP_AHB_RF_SPNIDEN 0x100
+#define MASK_AP_AHB_RF_VDSP_TRIGOUT_IDMA 0xc0
+#define MASK_AP_AHB_RF_VDSP_TRIGIN_IDMA 0x30
+#define MASK_AP_AHB_RF_STAT_VECTOR_SEL 0x8
+#define MASK_AP_AHB_RF_RUN_STALL_ON_RESET 0x4
+#define MASK_AP_AHB_RF_DCACHE_DRAM_FLUSH 0x3
+#define MASK_AP_AHB_RF_VDSP_PFAULTINFO_LOW 0xffffffff
+#define MASK_AP_AHB_RF_VDSP_PFAULTINFO_HIGH 0xffffffff
+#define MASK_AP_AHB_RF_VDSP_PWAITMODE 0x20
+#define MASK_AP_AHB_RF_VDSP_M_AUTO_GATE_EN 0x10
+#define MASK_AP_AHB_RF_VDSP_CLK_FRC_ON 0x8
+#define MASK_AP_AHB_RF_VDSP_STOP_EN 0x4
+#define MASK_AP_AHB_RF_VDSP_FRC_SLEEP 0x2
+#define MASK_AP_AHB_RF_VDSP_AUTO_GATE_EN 0x1
+#define MASK_AP_AHB_RF_INT_REQ_VDMA_MASK 0x10000
+#define MASK_AP_AHB_RF_INT_REQ_VDMA_VAU_MASK 0x8000
+#define MASK_AP_AHB_RF_INT_REQ_VDSP_VAU_MASK 0x4000
+#define MASK_AP_AHB_RF_VDSP_ALL_INT_MASK 0x2000
+#define MASK_AP_AHB_RF_INT_REQ_DCAM2_MASK 0x1000
+#define MASK_AP_AHB_RF_INT_REQ_DCAM1_MASK 0x800
+#define MASK_AP_AHB_RF_INT_TO_VDSP_BYIPI_MASK_3 0x400
+#define MASK_AP_AHB_RF_INT_TO_VDSP_BYIPI_MASK_2 0x200
+#define MASK_AP_AHB_RF_INT_TO_VDSP_BYIPI_MASK_1 0x100
+#define MASK_AP_AHB_RF_INT_REQ_GPIO_MASK 0x80
+#define MASK_AP_AHB_RF_INT_REQ_DCAM0_MASK 0x40
+#define MASK_AP_AHB_RF_INT_TO_VDSP_BYIPI_MASK_0 0x20
+#define MASK_AP_AHB_RF_INT_REQ_I2C4_MASK 0x10
+#define MASK_AP_AHB_RF_INT_REQ_I2C3_MASK 0x8
+#define MASK_AP_AHB_RF_INT_REQ_I2C2_MASK 0x4
+#define MASK_AP_AHB_RF_INT_REQ_I2C1_MASK 0x2
+#define MASK_AP_AHB_RF_INT_REQ_I2C0_MASK 0x1
+#define MASK_AP_AHB_RF_CHIP_ID 0xffffffff
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_HOLD 0x1
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_UP_WINDOW 0xffff0000
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_DOWN_WINDOW 0xffff
+#define MASK_AP_DVFS_APB_RF_VDSP_DFS_EN 0x4
+#define MASK_AP_DVFS_APB_RF_VSP_DFS_EN 0x2
+#define MASK_AP_DVFS_APB_RF_DISPC_DFS_EN 0x1
+#define MASK_AP_DVFS_APB_RF_VDSP_DFS_SW_TRIG 0x4
+#define MASK_AP_DVFS_APB_RF_VSP_DFS_SW_TRIG 0x2
+#define MASK_AP_DVFS_APB_RF_DISPC_DFS_SW_TRIG 0x1
+#define MASK_AP_DVFS_APB_RF_AP_SYS_MIN_VOLTAGE 0x7
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_ACK 0x100
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_VOLTAGE_SW 0x70
+#define MASK_AP_DVFS_APB_RF_AP_CURRENT_VOLTAGE_SW 0xe
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_REQ_SW 0x1
+#define MASK_AP_DVFS_APB_RF_REG_VDSP_FREQ_UPD_EN_BYP 0x4
+#define MASK_AP_DVFS_APB_RF_REG_VSP_FREQ_UPD_EN_BYP 0x2
+#define MASK_AP_DVFS_APB_RF_REG_DISPC_FREQ_UPD_EN_BYP 0x1
+#define MASK_AP_DVFS_APB_RF_CGM_AP_DVFS_FORCE_EN 0x2
+#define MASK_AP_DVFS_APB_RF_CGM_AP_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_AP_DVFS_APB_RF_AP_CURRENT_VOLTAGE 0x7000
+#define MASK_AP_DVFS_APB_RF_VDSP_VOLTAGE 0xe00
+#define MASK_AP_DVFS_APB_RF_VSP_VOLTAGE 0x1c0
+#define MASK_AP_DVFS_APB_RF_DISPC_VOLTAGE 0x38
+#define MASK_AP_DVFS_APB_RF_AP_INTERNAL_VOTE_VOLTAGE 0x7
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_DVFS 0x300
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_DVFS 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_DVFS 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_DVFS 0x7
+#define MASK_AP_DVFS_APB_RF_AP_SYS_DVFS_BUSY 0x80000
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_WINDOW_CNT 0x7fff8
+#define MASK_AP_DVFS_APB_RF_AP_DVFS_STATE 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX0 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX0 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX0 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX1 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX1 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX1 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX2 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX2 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX2 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX3 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX3 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX3 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX4 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX4 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX4 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX5 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX5 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX5 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX6 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX6 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX6 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_VOL_INDEX7 0xe0
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_M_DIV_INDEX7 0x18
+#define MASK_AP_DVFS_APB_RF_CGM_VDSP_SEL_INDEX7 0x7
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX0 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX0 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX1 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX1 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX2 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX2 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX3 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX3 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX4 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX4 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX5 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX5 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX6 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX6 0x3
+#define MASK_AP_DVFS_APB_RF_VSP_VOL_INDEX7 0x1c
+#define MASK_AP_DVFS_APB_RF_CGM_VSP_SEL_INDEX7 0x3
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX0 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX0 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX1 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX1 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX2 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX2 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX3 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX3 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX4 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX4 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX5 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX5 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX6 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX6 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_VOL_INDEX7 0x38
+#define MASK_AP_DVFS_APB_RF_CGM_DISPC_SEL_INDEX7 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_DVFS_INDEX 0x7
+#define MASK_AP_DVFS_APB_RF_VDSP_DVFS_INDEX_IDLE 0x7
+#define MASK_AP_DVFS_APB_RF_VSP_DVFS_INDEX 0x7
+#define MASK_AP_DVFS_APB_RF_VSP_DVFS_INDEX_IDLE 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_DVFS_INDEX 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_DVFS_INDEX_IDLE 0x7
+#define MASK_AP_DVFS_APB_RF_DISPC_DVFS_FREQ_UPD_STATE 0xf00
+#define MASK_AP_DVFS_APB_RF_VSP_DVFS_FREQ_UPD_STATE 0xf0
+#define MASK_AP_DVFS_APB_RF_VDSP_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_AP_DVFS_APB_RF_VDSP_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_AP_DVFS_APB_RF_DISPC_GFREE_WAIT_DELAY 0xffc00
+#define MASK_AP_DVFS_APB_RF_VSP_GFREE_WAIT_DELAY 0x3ff
+#define MASK_AP_DVFS_APB_RF_DISPC_FREQ_UPD_DELAY_EN 0x20
+#define MASK_AP_DVFS_APB_RF_DISPC_FREQ_UPD_HDSK_EN 0x10
+#define MASK_AP_DVFS_APB_RF_VSP_FREQ_UPD_DELAY_EN 0x8
+#define MASK_AP_DVFS_APB_RF_VSP_FREQ_UPD_HDSK_EN 0x4
+#define MASK_AP_DVFS_APB_RF_VDSP_FREQ_UPD_DELAY_EN 0x2
+#define MASK_AP_DVFS_APB_RF_VDSP_FREQ_UPD_HDSK_EN 0x1
+#define MASK_AP_DVFS_APB_RF_AP_DISPC_DFS_IDLE_DISABLE 0x4
+#define MASK_AP_DVFS_APB_RF_AP_VSP_DFS_IDLE_DISABLE 0x2
+#define MASK_AP_DVFS_APB_RF_AP_VDSP_DFS_IDLE_DISABLE 0x1
+#define MASK_AP_DVFS_APB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_AP_DVFS_APB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_AP_DVFS_APB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_AP_DVFS_APB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_HOLD 0x4
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_HOLD 0x2
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_UP_WINDOW 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_DOWN_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_UP_WINDOW 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_DOWN_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_MIN_VOLTAGE 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_MIN_VOLTAGE 0x7
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_AUTO_TUNE_EN 0x4
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_AUTO_TUNE_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_AUTO_TUNE_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_DFS_IDLE_DISABLE 0x800
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_DFS_IDLE_DISABLE 0x400
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_DFS_IDLE_DISABLE 0x200
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_DFS_IDLE_DISABLE 0x100
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_DFS_IDLE_DISABLE 0x80
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_DFS_IDLE_DISABLE 0x40
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_GRP_DFS_IDLE_DISABLE 0x20
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_GRP_DFS_IDLE_DISABLE 0x10
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_DFS_IDLE_DISABLE 0x8
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_DFS_IDLE_DISABLE 0x4
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_DFS_IDLE_DISABLE 0x2
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_DFS_IDLE_DISABLE 0x1
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_ACK 0x100
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_VOLTAGE_SW 0x70
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_CURRENT_VOLTAGE_SW 0xe
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_REQ_SW 0x1
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_ACK 0x100
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_VOLTAGE_SW 0x70
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_CURRENT_VOLTAGE_SW 0xe
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_REQ_SW 0x1
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_GIC_FREQ_UPD_EN_BYP 0x800
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_PERIPH_FREQ_UPD_EN_BYP 0x400
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_ATB_FREQ_UPD_EN_BYP 0x200
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_SCU_FREQ_UPD_EN_BYP 0x100
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE7_FREQ_UPD_EN_BYP 0x80
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE6_FREQ_UPD_EN_BYP 0x40
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE5_FREQ_UPD_EN_BYP 0x20
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE4_FREQ_UPD_EN_BYP 0x10
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE3_FREQ_UPD_EN_BYP 0x8
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE2_FREQ_UPD_EN_BYP 0x4
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE1_FREQ_UPD_EN_BYP 0x2
+#define MASK_APCPU_DVFS_APB_RF_REG_APCPU_CORE0_FREQ_UPD_EN_BYP 0x1
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DVFS_FORCE_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOLTAGE 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOLTAGE 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOLTAGE 0x38000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOLTAGE 0x7000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_VOLTAGE 0xe00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_VOLTAGE 0x1c0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_VOLTAGE 0x38
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_VOLTAGE 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_VOLTAGE 0xe00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_VOLTAGE 0x1c0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_VOLTAGE 0x38
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_VOLTAGE 0x7
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_DVFS 0xe000000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_DVFS 0x1c00000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_DVFS 0x300000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE3_DIV_DVFS 0xe0000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE3_SEL_DVFS 0x18000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE2_DIV_DVFS 0x7000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE2_SEL_DVFS 0xc00
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE1_DIV_DVFS 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE1_SEL_DVFS 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE0_DIV_DVFS 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE0_SEL_DVFS 0x3
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_DVFS 0x1c000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_DVFS 0x3000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_DVFS 0xc00
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_DVFS 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_DVFS 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_DVFS 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_DVFS 0x3
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE7_DIV_DVFS 0xe0000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE7_SEL_DVFS 0x18000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE6_DIV_DVFS 0x7000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE6_SEL_DVFS 0xc00
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE5_DIV_DVFS 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE5_SEL_DVFS 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE4_DIV_DVFS 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE4_SEL_DVFS 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_WINDOW_CNT 0x1fffe00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_CURRENT_VOLTAGE 0x1c0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_VOTE_VOL 0x38
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_DVFS_STATE 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_WINDOW_CNT 0x1fffe00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_CURRENT_VOLTAGE 0x1c0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_VOTE_VOL 0x38
+#define MASK_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_DVFS_STATE 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_VOTE_DCDC_CPU0_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_VOTE_DCDC_CPU0_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX0 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX0 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX0 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX0 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX0 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX1 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX1 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX1 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX1 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX1 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX2 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX2 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX2 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX2 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX2 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX3 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX3 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX3 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX3 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX3 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX4 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX4 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX4 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX4 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX4 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX5 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX5 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX5 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX5 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX5 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX6 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX6 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX6 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX6 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX6 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX7 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX7 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX7 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX7 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX7 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX8 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX8 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX8 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX8 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX8 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX8 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX8 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX9 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX9 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX9 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX9 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX9 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX9 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX9 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX10 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX10 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX10 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX10 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX10 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX10 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX10 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX11 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX11 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX11 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX11 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX11 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX11 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX11 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX12 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX12 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX12 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX12 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX12 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX12 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX12 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX13 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX13 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX13 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX13 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX13 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX13 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX13 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX14 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX14 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX14 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX14 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX14 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX14 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX14 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_GIC_INDEX15 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOL_INDEX15 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_INDEX15 0x7000
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_PERIPH_INDEX15 0xe00
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_VOTE_SCU_INDEX15 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_DIV_INDEX15 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_ANANKE_SEL_INDEX15 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX0 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX0 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX0 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX0 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX0 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX0 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX1 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX1 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX1 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX1 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX1 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX1 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX2 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX2 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX2 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX2 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX2 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX2 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX3 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX3 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX3 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX3 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX3 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX3 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX4 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX4 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX4 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX4 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX4 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX4 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX5 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX5 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX5 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX5 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX5 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX5 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX6 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX6 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX6 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX6 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX6 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX6 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX7 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX7 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX7 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX7 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX7 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX7 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX8 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX8 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX8 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX8 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX8 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX8 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX8 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX8 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX9 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX9 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX9 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX9 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX9 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX9 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX9 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX9 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX10 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX10 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX10 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX10 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX10 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX10 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX10 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX10 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX11 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX11 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX11 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX11 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX11 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX11 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX11 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX11 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX12 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX12 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX12 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX12 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX12 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX12 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX12 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX12 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX13 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX13 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX13 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX13 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX13 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX13 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX13 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX13 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX14 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX14 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX14 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX14 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX14 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX14 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX14 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX14 0x3
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_GIC_INDEX15 0xe00000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DCDC_CPU0_VOL_INDEX15 0x1c0000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOL_INDEX15 0x38000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_INDEX15 0x7000
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_PERIPH_INDEX15 0xe00
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_VOTE_SCU_INDEX15 0x1e0
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_DIV_INDEX15 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_PROMETHEUS_SEL_INDEX15 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX0 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX0 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX0 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX1 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX1 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX1 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX2 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX2 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX2 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX3 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX3 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX3 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX4 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX4 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX4 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX5 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX5 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX5 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX6 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX6 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX6 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX7 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX7 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX7 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX8 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX8 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX8 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX8 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX8 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX9 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX9 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX9 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX9 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX9 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX10 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX10 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX10 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX10 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX10 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX11 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX11 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX11 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX11 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX11 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX12 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX12 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX12 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX12 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX12 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX13 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX13 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX13 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX13 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX13 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX14 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX14 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX14 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX14 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX14 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_VOL_INDEX15 0x3800
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_INDEX15 0x700
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_INDEX15 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_INDEX15 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_INDEX15 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX0 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX0 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX1 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX1 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX2 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX2 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX3 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX3 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX4 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX4 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX5 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX5 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX6 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX6 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_VOL_INDEX7 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_DEBUG_APB_DIV_INDEX7 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ATB_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX0 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX1 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX2 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX3 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX4 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX5 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX6 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_VOL_INDEX7 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_PERIPH_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX 0xf
+#define MASK_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX_IDLE 0xf
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX 0xf
+#define MASK_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX_IDLE 0xf
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX 0xf
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX_IDLE 0xf
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX_IDLE 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX_IDLE 0x7
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_POWER_OFF_CNT_EN 0x4
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_AUTO_RELOCK_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_AUTO_PD_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_RELOCK_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_POWER_ON_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_UNGATE_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_GATE_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_POWER_OFF_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_POWER_OFF_WAIT_WINDOW 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_RELOCK_UPD_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_POWER_OFF_CNT_EN 0x4
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_AUTO_RELOCK_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_AUTO_PD_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_RELOCK_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_POWER_ON_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_UNGATE_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_GATE_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_POWER_OFF_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_POWER_OFF_WAIT_WINDOW 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_RELOCK_UPD_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_POWER_OFF_CNT_EN 0x4
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_AUTO_RELOCK_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_AUTO_PD_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_RELOCK_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_POWER_ON_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_UNGATE_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_GATE_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_POWER_OFF_DELAY 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_POWER_OFF_WAIT_WINDOW 0xffff0000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_RELOCK_UPD_DELAY 0xffff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX0 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX0 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX0 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX1 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX1 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX1 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX2 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX2 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX2 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX3 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX3 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX3 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX4 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX4 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX4 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX5 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX5 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX5 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX6 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX6 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX6 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_VOL_INDEX7 0xe0
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_DIV_INDEX7 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_GIC_SEL_INDEX7 0x3
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_CTRL_STATE 0xf00
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_CTRL_STATE 0xf0
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_CTRL_STATE 0xf
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_FREQ_UPD_STATE 0xf0000000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_FREQ_UPD_STATE 0xf000000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_FREQ_UPD_STATE 0xf00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_FREQ_UPD_STATE 0xf0000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_DVFS_FREQ_UPD_STATE 0xf000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_DVFS_FREQ_UPD_STATE 0xf00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_DVFS_FREQ_UPD_STATE 0xf0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_ACE_DIV_RELOCK_BYP 0xe000000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_DIV_RELOCK_BYP 0x1c00000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_SCU_SEL_RELOCK_BYP 0x300000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE3_DIV_RELOCK_BYP 0xe0000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE3_SEL_RELOCK_BYP 0x18000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE2_DIV_RELOCK_BYP 0x7000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE2_SEL_RELOCK_BYP 0xc00
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE1_DIV_RELOCK_BYP 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE1_SEL_RELOCK_BYP 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE0_DIV_RELOCK_BYP 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE0_SEL_RELOCK_BYP 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_GFREE_WAIT_DELAY 0xffc00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_GFREE_WAIT_DELAY 0x3ff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_GFREE_WAIT_DELAY 0xffc00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_GFREE_WAIT_DELAY 0x3ff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_GFREE_WAIT_DELAY 0xffc00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_GFREE_WAIT_DELAY 0x3ff
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_GFREE_WAIT_DELAY 0xffc00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_GFREE_WAIT_DELAY 0x3ff
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_POWER_OFF_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_POWER_OFF_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_POWER_OFF_RELOCK_WINDOW 0xffff
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE7_DIV_RELOCK_BYP 0xe0000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE7_SEL_RELOCK_BYP 0x18000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE6_DIV_RELOCK_BYP 0x7000
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE6_SEL_RELOCK_BYP 0xc00
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE5_DIV_RELOCK_BYP 0x380
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE5_SEL_RELOCK_BYP 0x60
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE4_DIV_RELOCK_BYP 0x1c
+#define MASK_APCPU_DVFS_APB_RF_CGM_APCPU_CORE4_SEL_RELOCK_BYP 0x3
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_FREQ_UPD_DELAY_EN 0x800000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_FREQ_UPD_HDSK_EN 0x400000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_FREQ_UPD_DELAY_EN 0x200000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_PERIPH_FREQ_UPD_HDSK_EN 0x100000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_FREQ_UPD_DELAY_EN 0x80000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_ATB_FREQ_UPD_HDSK_EN 0x40000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_FREQ_UPD_DELAY_EN 0x20000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_SCU_FREQ_UPD_HDSK_EN 0x10000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_FREQ_UPD_DELAY_EN 0x8000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_FREQ_UPD_HDSK_EN 0x4000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_FREQ_UPD_DELAY_EN 0x2000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_FREQ_UPD_HDSK_EN 0x1000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_FREQ_UPD_DELAY_EN 0x800
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_FREQ_UPD_HDSK_EN 0x400
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_FREQ_UPD_DELAY_EN 0x200
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_FREQ_UPD_HDSK_EN 0x100
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_FREQ_UPD_DELAY_EN 0x80
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE3_FREQ_UPD_HDSK_EN 0x40
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_FREQ_UPD_DELAY_EN 0x20
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE2_FREQ_UPD_HDSK_EN 0x10
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_FREQ_UPD_DELAY_EN 0x8
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE1_FREQ_UPD_HDSK_EN 0x4
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_FREQ_UPD_DELAY_EN 0x2
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE0_FREQ_UPD_HDSK_EN 0x1
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_CNT_DONE 0x20000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_CLKOUT_EN 0x10000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_DVFS_PD 0x8000
+#define MASK_APCPU_DVFS_APB_RF_MPLL2_INDEX 0x7000
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_CNT_DONE 0x800
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_CLKOUT_EN 0x400
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_DVFS_PD 0x200
+#define MASK_APCPU_DVFS_APB_RF_MPLL1_INDEX 0x1c0
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_CNT_DONE 0x20
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_CLKOUT_EN 0x10
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_DVFS_PD 0x8
+#define MASK_APCPU_DVFS_APB_RF_MPLL0_INDEX 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE7_DVFS_FREQ_UPD_STATE 0xf000
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE6_DVFS_FREQ_UPD_STATE 0xf00
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE5_DVFS_FREQ_UPD_STATE 0xf0
+#define MASK_APCPU_DVFS_APB_RF_APCPU_CORE4_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX 0x7
+#define MASK_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX_IDLE 0x7
+#define MASK_APCPU_DVFS_APB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_APCPU_DVFS_APB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_APCPU_DVFS_APB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_APCPU_DVFS_APB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_REG_FW0_AP_APB_MISC_CTRL_RD_SEC 0x4
+#define MASK_REG_FW0_AP_APB_RST_RD_SEC 0x2
+#define MASK_REG_FW0_AP_APB_EB_RD_SEC 0x1
+#define MASK_REG_FW0_AP_APB_MISC_CTRL_WR_SEC 0x4
+#define MASK_REG_FW0_AP_APB_RST_WR_SEC 0x2
+#define MASK_REG_FW0_AP_APB_EB_WR_SEC 0x1
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY0 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY1 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY2 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY3 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY4 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY5 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY6 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY7 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY8 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY9 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY10 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY11 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY12 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY13 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY14 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY15 0xffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY0 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY1 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY2 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY3 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY4 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY5 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY6 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY7 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY8 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY9 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY10 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY11 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY12 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY13 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY14 0xffffffff
+#define MASK_REG_FW0_AP_BIT_CTRL_ARRAY15 0xffffffff
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_HOLD 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_UP_WINDOW 0xffff0000
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_DOWN_WINDOW 0xffff
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_ACK 0x100
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_VOLTAGE_SW 0x70
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_CURRENT_VOLTAGE_SW 0xe
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_REQ_SW 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_REG_DSP_FREQ_UPD_EN_BYP 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_AUDCP_DVFS_FORCE_EN 0x2
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_AUDCP_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_CURRENT_VOLTAGE 0x38000
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_INTERNAL_VOTE_VOLTAGE 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_DVFS 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_DVFS 0x300
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_DVFS 0xc0
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_DVFS 0x38
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_DVFS 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_SYS_DVFS_BUSY 0x80000
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_WINDOW_CNT 0x7fff8
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_STATE 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX0 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX0 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX0 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX0 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX0 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX0 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX1 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX1 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX1 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX1 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX1 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX1 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX2 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX2 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX2 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX2 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX2 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX2 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX3 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX3 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX3 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX3 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX3 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX3 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX4 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX4 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX4 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX4 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX4 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX4 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX5 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX5 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX5 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX5 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX5 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX5 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX6 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX6 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX6 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX6 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX6 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX6 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_VOL_INDEX7 0xe000
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_APB_DIV_INDEX7 0x1c00
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AHB_DIV_INDEX7 0x380
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_AXI_DIV_INDEX7 0x60
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_DIV_INDEX7 0x18
+#define MASK_AUDCP_DVFS_AHB_RF_CGM_DSP_CORE_SEL_INDEX7 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_DVFS_INDEX 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_DVFS_INDEX_IDLE 0x7
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_GFREE_WAIT_DELAY 0x3ff
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_FREQ_UPD_DELAY_EN 0x2
+#define MASK_AUDCP_DVFS_AHB_RF_DSP_FREQ_UPD_HDSK_EN 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_AUDCP_DSP_CORE_GRP_DFS_IDLE_DISABLE 0x1
+#define MASK_AUDCP_DVFS_AHB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_AUDCP_DVFS_AHB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_AUDCP_DVFS_AHB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_AUDCP_DVFS_AHB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_AUD_CP_CLK_CORE_CGM_DSP_CORE_CFG_CGM_DSP_CORE_DIV 0x300
+#define MASK_AUD_CP_CLK_CORE_CGM_DSP_CORE_CFG_CGM_DSP_CORE_SEL 0x7
+#define MASK_AUD_CP_CLK_CORE_CGM_DSP_AXI_CFG_CGM_DSP_AXI_DIV 0x300
+#define MASK_AUD_CP_CLK_CORE_CGM_DSP_AHB_CFG_CGM_DSP_AHB_DIV 0x700
+#define MASK_AUD_CP_CLK_CORE_CGM_DSP_APB_CFG_CGM_DSP_APB_DIV 0x700
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS0_CFG_CGM_IIS0_DIV 0x3f00
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS0_CFG_CGM_IIS0_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS1_CFG_CGM_IIS1_DIV 0x3f00
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS1_CFG_CGM_IIS1_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS2_CFG_CGM_IIS2_DIV 0x3f00
+#define MASK_AUD_CP_CLK_CORE_CGM_IIS2_CFG_CGM_IIS2_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_UART_CFG_CGM_UART_DIV 0x700
+#define MASK_AUD_CP_CLK_CORE_CGM_UART_CFG_CGM_UART_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_TMR_26M_CFG_CGM_TMR_26M_SEL 0x1
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_CFG_CGM_VBC_SEL 0x1
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_24M_CFG_CGM_VBC_24M_SEL 0x1
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_IFD_CFG_CGM_VBC_IFD_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_IIS0_CFG_CGM_VBC_IIS0_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_IIS1_CFG_CGM_VBC_IIS1_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_IIS2_CFG_CGM_VBC_IIS2_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_VBC_IIS3_CFG_CGM_VBC_IIS3_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_TDM_SLV_CFG_CGM_TDM_SLV_PAD_SEL 0x10000
+#define MASK_AUD_CP_CLK_CORE_CGM_SRC48K_CFG_CGM_SRC48K_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_AUD_CFG_CGM_AUD_SEL 0x1
+#define MASK_AUD_CP_CLK_CORE_CGM_AUDIF_CFG_CGM_AUDIF_SEL 0x3
+#define MASK_AUD_CP_CLK_CORE_CGM_AUDCP_DVFS_CFG_CGM_AUDCP_DVFS_SEL 0x3
+#define MASK_PUB_APB_RF_SOFT_CMD_NUM 0x700
+#define MASK_PUB_APB_RF_SOFT_CMD_FC_SEL 0x30
+#define MASK_PUB_APB_RF_SOFT_CMD_RESP 0x8
+#define MASK_PUB_APB_RF_SOFT_CMD_DONE 0x4
+#define MASK_PUB_APB_RF_SOFT_CMD_START 0x1
+#define MASK_PUB_APB_RF_SOFT_CMD_SEQL 0xffffffff
+#define MASK_PUB_APB_RF_SOFT_CMD_SEQH 0xffffffff
+#define MASK_PUB_APB_RF_SOFT_CMD_STEP 0xffffffff
+#define MASK_PUB_APB_RF_DPLL_PRE_DIV_MONITOR_GATE_AUTO_EN_STATUS 0xc
+#define MASK_PUB_APB_RF_DPLL_PRE_DIV_MONITOR_WAIT_EN_STATUS 0x3
+#define MASK_PUB_APB_RF_DFI_MON_IDLE_CNT 0xff00
+#define MASK_PUB_APB_RF_DFI_MON_TIMER_DELAY 0xff
+#define MASK_PUB_APB_RF_URGENT_CHN_SEL 0x2
+#define MASK_PUB_APB_RF_QOS_URGENT_SEL 0x1
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_AGCP 0x20000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_PUBCP 0x10000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_WTLCP 0x8000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_AON 0x4000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_AP 0x2000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_VDSP 0x1000000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_ISP 0x800000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_ISP_RAW 0x400000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_DPU 0x200000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_GPU 0x100000
+#define MASK_PUB_APB_RF_HANDSHK_FORCE_OPEN_CLOCK_EN_APCPU 0x80000
+#define MASK_PUB_APB_RF_CH6_DMC_STOP_CG_EN 0x40000
+#define MASK_PUB_APB_RF_CH5_DMC_STOP_CG_EN 0x20000
+#define MASK_PUB_APB_RF_CH4_DMC_STOP_CG_EN 0x10000
+#define MASK_PUB_APB_RF_CH3_DMC_STOP_CG_EN 0x8000
+#define MASK_PUB_APB_RF_CH2_DMC_STOP_CG_EN 0x4000
+#define MASK_PUB_APB_RF_CH1_DMC_STOP_CG_EN 0x2000
+#define MASK_PUB_APB_RF_CH0_DMC_STOP_CG_EN 0x1000
+#define MASK_PUB_APB_RF_LP_STAT_MTX_CG_EN 0x800
+#define MASK_PUB_APB_RF_PUB_PTM_26M_EN 0x400
+#define MASK_PUB_APB_RF_OT_DETECT_CLK_EB 0x200
+#define MASK_PUB_APB_RF_PUB_CLK_CSSYS_PTM_EB 0x100
+#define MASK_PUB_APB_RF_PUB_APB_PTM_REG_EB 0x80
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_PTM_EB 0x40
+#define MASK_PUB_APB_RF_PUB_APB_INT_EB 0x20
+#define MASK_PUB_APB_RF_PUB_APB_BIST_REG_EB 0x10
+#define MASK_PUB_APB_RF_PUB_AHB_QOSC_REG_EB 0x8
+#define MASK_PUB_APB_RF_PUB_AHB_REG_EB 0x4
+#define MASK_PUB_APB_RF_PUB_AHB_BUS_EB 0x2
+#define MASK_PUB_APB_RF_PUB_PHY_REG_EB 0x1
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_AP_AON_S0 0x8000000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_AP_AON_S0 0x4000000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_AP_AON_M1 0x2000000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_AP_AON_M1 0x1000000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_AP_AON_M0 0x800000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_AP_AON_M0 0x400000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_ISP_VDSP_S0 0x200000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_ISP_VDSP_S0 0x100000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_ISP_VDSP_M1 0x80000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_ISP_VDSP_M1 0x40000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_ISP_VDSP_M0 0x20000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_ISP_VDSP_M0 0x10000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_DPU_ISP_S0 0x8000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_DPU_ISP_S0 0x4000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_DPU_ISP_M1 0x2000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_DPU_ISP_M1 0x1000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_DPU_ISP_M0 0x800
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_DPU_ISP_M0 0x400
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUB_CFG_S3 0x200
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUB_CFG_S3 0x100
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUB_CFG_S2 0x80
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUB_CFG_S2 0x40
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUB_CFG_S1 0x20
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUB_CFG_S1 0x10
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUB_CFG_S0 0x8
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUB_CFG_S0 0x4
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUB_CFG_M0 0x2
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUB_CFG_M0 0x1
+#define MASK_PUB_APB_RF_INT_DFS_VOTE_DONE_CG_EN 0x400
+#define MASK_PUB_APB_RF_MEM_FW_PUB_CACTIVE_CG_EN 0x200
+#define MASK_PUB_APB_RF_INT_DMC_MPU_VIO_CG_EN 0x100
+#define MASK_PUB_APB_RF_INT_MEM_FW_CG_EN 0x80
+#define MASK_PUB_APB_RF_INT_DFS_GIVEUP_CG_EN 0x40
+#define MASK_PUB_APB_RF_INT_DFS_DENY_CG_EN 0x20
+#define MASK_PUB_APB_RF_INT_DFS_ERROR_CG_EN 0x10
+#define MASK_PUB_APB_RF_INT_HARDWARE_DFS_EXIT_CG_EN 0x8
+#define MASK_PUB_APB_RF_INT_DFS_COMPLETE_CG_EN 0x4
+#define MASK_PUB_APB_RF_INT_DFI_BUS_MONITOR_CG_EN 0x2
+#define MASK_PUB_APB_RF_INT_REQ_PUB_PTM_CG_EN 0x1
+#define MASK_PUB_APB_RF_PTM_TIMER_EN 0x8
+#define MASK_PUB_APB_RF_LATMON_TIMER_EN 0x4
+#define MASK_PUB_APB_RF_BWMON_TIMER_EN 0x2
+#define MASK_PUB_APB_RF_DBM_TIMER_EN 0x1
+#define MASK_PUB_APB_RF_BV_FV_EQUAL_INC_EN 0x20000000
+#define MASK_PUB_APB_RF_DBM_PERCENT_SEL 0x1c000000
+#define MASK_PUB_APB_RF_DFS_VOTE_DMC_REF_AG_EN 0x2000000
+#define MASK_PUB_APB_RF_DFS_APB_ACCESS_CLK_AUTO_EN 0x1000000
+#define MASK_PUB_APB_RF_RF_VOTE_CK_OPEN_CNT 0x1fe000
+#define MASK_PUB_APB_RF_TIMING_WINDOW_SEL 0x1c00
+#define MASK_PUB_APB_RF_VOTE_UNIT_TRANS_EN 0x200
+#define MASK_PUB_APB_RF_SW_FORCE_VOTE_MASK_EN 0x100
+#define MASK_PUB_APB_RF_SW_FORCE_VOTE_MASK 0xff
+#define MASK_PUB_APB_RF_VOTE_TAR_FRQ 0xe00
+#define MASK_PUB_APB_RF_VOTE_NEXT_STATE 0x1e0
+#define MASK_PUB_APB_RF_VOTE_CUR_STATE 0x1e
+#define MASK_PUB_APB_RF_VOTE_BW_OVERFLOW 0x1
+#define MASK_PUB_APB_RF_DFS_LOCK_DELAY_EN 0x80000000
+#define MASK_PUB_APB_RF_REG_DFS_LOCK_DELAY_CNT 0x78000000
+#define MASK_PUB_APB_RF_DFI_MASK_WAIT_LSLP_EN 0x1000000
+#define MASK_PUB_APB_RF_DFI_MASK_WAIT_TIME_LSLP 0xff0000
+#define MASK_PUB_APB_RF_DFI_MASK_WAIT_EN 0x100
+#define MASK_PUB_APB_RF_DFI_MASK_WAIT_TIME 0xff
+#define MASK_PUB_APB_RF_DMC_FIXED_QOS_EN 0x7f
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH3 0xf0000000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH3 0xf000000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH2 0xf00000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH2 0xf0000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH1 0xf000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH1 0xf00
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH0 0xf0
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH0 0xf
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH6 0xf00000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH6 0xf0000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH5 0xf000
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH5 0xf00
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_ARQOS_CH4 0xf0
+#define MASK_PUB_APB_RF_RF_DMC_FIXED_AWQOS_CH4 0xf
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH3 0xf0000000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH3 0xf000000
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH2 0xf00000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH2 0xf0000
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH1 0xf000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH1 0xf00
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH0 0xf0
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH0 0xf
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH7 0xf0000000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH7 0xf000000
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH6 0xf00000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH6 0xf0000
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH5 0xf000
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH5 0xf00
+#define MASK_PUB_APB_RF_RF_ARQOS_URGENT_CH4 0xf0
+#define MASK_PUB_APB_RF_RF_AWQOS_URGENT_CH4 0xf
+#define MASK_PUB_APB_RF_DFS_VOTE_DONE_INT_BYPASS 0x800000
+#define MASK_PUB_APB_RF_DFS_GIVEUP_INT_BYPASS 0x400000
+#define MASK_PUB_APB_RF_DFS_DENY_INT_BYPASS 0x200000
+#define MASK_PUB_APB_RF_DMC_MPU_VIO_INT_BYPASS 0x100000
+#define MASK_PUB_APB_RF_MEM_FW_INT_BYPASS 0x80000
+#define MASK_PUB_APB_RF_DFS_ERROR_INT_BYPASS 0x40000
+#define MASK_PUB_APB_RF_DFS_COMPLETE_INT_BYPASS 0x20000
+#define MASK_PUB_APB_RF_HW_DFS_EXIT_INT_BYPASS 0x10000
+#define MASK_PUB_APB_RF_DFS_VOTE_DONE_INT_CLR 0x8000
+#define MASK_PUB_APB_RF_DFS_VOTE_DONE_INT_EN 0x4000
+#define MASK_PUB_APB_RF_DFS_GIVEUP_INT_CLR 0x2000
+#define MASK_PUB_APB_RF_DFS_GIVEUP_INT_EN 0x1000
+#define MASK_PUB_APB_RF_DFS_DENY_INT_CLR 0x800
+#define MASK_PUB_APB_RF_DFS_DENY_INT_EN 0x400
+#define MASK_PUB_APB_RF_DMC_MPU_VIO_INT_CLR 0x200
+#define MASK_PUB_APB_RF_DMC_MPU_VIO_INT_EN 0x100
+#define MASK_PUB_APB_RF_MEM_FW_INT_CLR 0x80
+#define MASK_PUB_APB_RF_MEM_FW_INT_EN 0x40
+#define MASK_PUB_APB_RF_DFS_ERROR_INT_CLR 0x20
+#define MASK_PUB_APB_RF_DFS_ERROR_INT_EN 0x10
+#define MASK_PUB_APB_RF_DFS_COMPLETE_INT_CLR 0x8
+#define MASK_PUB_APB_RF_DFS_COMPLETE_INT_EN 0x4
+#define MASK_PUB_APB_RF_HW_DFS_EXIT_INT_CLR 0x2
+#define MASK_PUB_APB_RF_HW_DFS_EXIT_INT_EN 0x1
+#define MASK_PUB_APB_RF_DFS_HW_MIN_FREQ_UP_FORCE_TRIG_ACK 0x40000000
+#define MASK_PUB_APB_RF_DFS_USED_PLL 0x38000000
+#define MASK_PUB_APB_RF_DFS_FC_SEL 0x7000000
+#define MASK_PUB_APB_RF_SRC_AVAIL_PLL 0xe00000
+#define MASK_PUB_APB_RF_DFS_URGENT_WAIT_TIMEOUT_FLAG 0x100000
+#define MASK_PUB_APB_RF_RF_DFS_GIVEUP_INT_RAW 0x80000
+#define MASK_PUB_APB_RF_RF_INT_DFS_GIVEUP 0x40000
+#define MASK_PUB_APB_RF_RF_DFS_DENY_INT_RAW 0x20000
+#define MASK_PUB_APB_RF_RF_INT_DFS_DENY 0x10000
+#define MASK_PUB_APB_RF_HW_DFS_FSM_STATE 0xf800
+#define MASK_PUB_APB_RF_HW_DFS_FSM_IDLE 0x400
+#define MASK_PUB_APB_RF_RF_INT_DMC_MPU_VIO_RAW 0x200
+#define MASK_PUB_APB_RF_RF_INT_DMC_MPU_VIO 0x100
+#define MASK_PUB_APB_RF_RF_INT_MEM_FW_RAW 0x80
+#define MASK_PUB_APB_RF_RF_INT_MEM_FW 0x40
+#define MASK_PUB_APB_RF_RF_DFS_ERROR_INT_RAW 0x20
+#define MASK_PUB_APB_RF_RF_INT_DFS_ERROR 0x10
+#define MASK_PUB_APB_RF_RF_DFS_COMPLETE_INT_RAW 0x8
+#define MASK_PUB_APB_RF_RF_INT_DFS_COMPLETE 0x4
+#define MASK_PUB_APB_RF_RF_HW_DFS_EXIT_INT_RAW 0x2
+#define MASK_PUB_APB_RF_RF_INT_HW_DFS_EXIT 0x1
+#define MASK_PUB_APB_RF_DFS_SW_FSM_STATE 0x70
+#define MASK_PUB_APB_RF_RF_DFS_VOTE_DONE_INT_RAW 0x2
+#define MASK_PUB_APB_RF_RF_INT_DFS_VOTE_DONE 0x1
+#define MASK_PUB_APB_RF_DFS_FC_REQ_DELAY 0x7
+#define MASK_PUB_APB_RF_DFS_SW_MODE 0x40
+#define MASK_PUB_APB_RF_HW_DFS_STOP_ENABLE 0x20
+#define MASK_PUB_APB_RF_HW_DFS_RESTART_ENABLE 0x10
+#define MASK_PUB_APB_RF_AUTO_STOP_NOC_ENABLE 0x8
+#define MASK_PUB_APB_RF_AUTO_STOP_DFS_ENABLE 0x4
+#define MASK_PUB_APB_RF_PUB_DFS_EN 0x2
+#define MASK_PUB_APB_RF_PUB_LP_EN 0x1
+#define MASK_PUB_APB_RF_PU_NUM 0xff000000
+#define MASK_PUB_APB_RF_PU_NUM_PUB_CFG 0xff0000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUBCP_AG_S0 0x8000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUBCP_AG_S0 0x4000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUBCP_AG_M1 0x2000
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUBCP_AG_M1 0x1000
+#define MASK_PUB_APB_RF_CSYSACK_SYNC_SEL_PUBCP_AG_M0 0x800
+#define MASK_PUB_APB_RF_CACTIVE_SYNC_SEL_PUBCP_AG_M0 0x400
+#define MASK_PUB_APB_RF_LP_FORCE_ISP_VDSP_S0 0x20
+#define MASK_PUB_APB_RF_LP_EB_ISP_VDSP_S0 0x10
+#define MASK_PUB_APB_RF_LP_FORCE_ISP_VDSP_M1 0x8
+#define MASK_PUB_APB_RF_LP_EB_ISP_VDSP_M1 0x4
+#define MASK_PUB_APB_RF_LP_FORCE_ISP_VDSP_M0 0x2
+#define MASK_PUB_APB_RF_LP_EB_ISP_VDSP_M0 0x1
+#define MASK_PUB_APB_RF_LP_FORCE_PUB_CFG_S3 0x8000000
+#define MASK_PUB_APB_RF_LP_EB_PUB_CFG_S3 0x4000000
+#define MASK_PUB_APB_RF_LP_FORCE_PUB_CFG_S2 0x2000000
+#define MASK_PUB_APB_RF_LP_EB_PUB_CFG_S2 0x1000000
+#define MASK_PUB_APB_RF_LP_FORCE_PUB_CFG_S1 0x800000
+#define MASK_PUB_APB_RF_LP_EB_PUB_CFG_S1 0x400000
+#define MASK_PUB_APB_RF_LP_FORCE_PUB_CFG_S0 0x200000
+#define MASK_PUB_APB_RF_LP_EB_PUB_CFG_S0 0x100000
+#define MASK_PUB_APB_RF_LP_FORCE_PUB_CFG_M0 0x80000
+#define MASK_PUB_APB_RF_LP_EB_PUB_CFG_M0 0x40000
+#define MASK_PUB_APB_RF_LP_FORCE_PUBCP_AG_S0 0x20000
+#define MASK_PUB_APB_RF_LP_EB_PUBCP_AG_S0 0x10000
+#define MASK_PUB_APB_RF_LP_FORCE_PUBCP_AG_M1 0x8000
+#define MASK_PUB_APB_RF_LP_EB_PUBCP_AG_M1 0x4000
+#define MASK_PUB_APB_RF_LP_FORCE_PUBCP_AG_M0 0x2000
+#define MASK_PUB_APB_RF_LP_EB_PUBCP_AG_M0 0x1000
+#define MASK_PUB_APB_RF_LP_FORCE_AP_AON_S0 0x800
+#define MASK_PUB_APB_RF_LP_EB_AP_AON_S0 0x400
+#define MASK_PUB_APB_RF_LP_FORCE_AP_AON_M1 0x200
+#define MASK_PUB_APB_RF_LP_EB_AP_AON_M1 0x100
+#define MASK_PUB_APB_RF_LP_FORCE_AP_AON_M0 0x80
+#define MASK_PUB_APB_RF_LP_EB_AP_AON_M0 0x40
+#define MASK_PUB_APB_RF_LP_FORCE_DPU_ISP_S0 0x20
+#define MASK_PUB_APB_RF_LP_EB_DPU_ISP_S0 0x10
+#define MASK_PUB_APB_RF_LP_FORCE_DPU_ISP_M1 0x8
+#define MASK_PUB_APB_RF_LP_EB_DPU_ISP_M1 0x4
+#define MASK_PUB_APB_RF_LP_FORCE_DPU_ISP_M0 0x2
+#define MASK_PUB_APB_RF_LP_EB_DPU_ISP_M0 0x1
+#define MASK_PUB_APB_RF_LP_NUM_PUB_CFG 0xffff0000
+#define MASK_PUB_APB_RF_LP_NUM 0xffff
+#define MASK_PUB_APB_RF_PUB_CLK_DDR_EN_BY_FENCING_RELEASE 0x80000000
+#define MASK_PUB_APB_RF_RF_DDR_FENCING_EN 0x40000000
+#define MASK_PUB_APB_RF_RF_FENCING_CHNL_IDLE_CNT 0x3fffffff
+#define MASK_PUB_APB_RF_RF_AON_BASE_ADDR 0xf8000
+#define MASK_PUB_APB_RF_RF_AG_CP_BASE_ADDR 0x1fff
+#define MASK_PUB_APB_RF_RF_PUB_CP_BASE_ADDR 0x1fff0000
+#define MASK_PUB_APB_RF_RF_WTL_CP_BASE_ADDR 0xfff8
+#define MASK_PUB_APB_RF_LP_WAIT_CGM_BUSY_SEL 0x4
+#define MASK_PUB_APB_RF_CGM_PUB_DFS_SEL 0x2
+#define MASK_PUB_APB_RF_CGM_PUB_DFS_EN 0x1
+#define MASK_PUB_APB_RF_BIST_FAIL_FLAG_CH2 0x400
+#define MASK_PUB_APB_RF_BIST_FAIL_FLAG_CH1 0x200
+#define MASK_PUB_APB_RF_BIST_FAIL_FLAG_CH0 0x100
+#define MASK_PUB_APB_RF_BIST_PORT6_EN 0x40
+#define MASK_PUB_APB_RF_BIST_PORT5_EN 0x20
+#define MASK_PUB_APB_RF_BIST_PORT4_EN 0x10
+#define MASK_PUB_APB_RF_BIST_PORT3_EN 0x8
+#define MASK_PUB_APB_RF_BIST_PORT2_EN 0x4
+#define MASK_PUB_APB_RF_BIST_PORT1_EN 0x2
+#define MASK_PUB_APB_RF_BIST_PORT0_EN 0x1
+#define MASK_PUB_APB_RF_DMC_SOFT_RST 0x4
+#define MASK_PUB_APB_RF_DCC_SOFT_RST 0x2
+#define MASK_PUB_APB_RF_DDRPHY_SOFT_RST 0x1
+#define MASK_PUB_APB_RF_MC_IDLE_WAIT_CTRL 0xffffffff
+#define MASK_PUB_APB_RF_AWQOS_THRESHOLD_PUBCP_AG 0xf0000000
+#define MASK_PUB_APB_RF_ARQOS_THRESHOLD_PUBCP_AG 0xf000000
+#define MASK_PUB_APB_RF_AWQOS_THRESHOLD_DPU_ISP 0xf00000
+#define MASK_PUB_APB_RF_ARQOS_THRESHOLD_DPU_ISP 0xf0000
+#define MASK_PUB_APB_RF_AWQOS_THRESHOLD_AP_AON 0xf000
+#define MASK_PUB_APB_RF_ARQOS_THRESHOLD_AP_AON 0xf00
+#define MASK_PUB_APB_RF_AON_AWQOS 0xf0
+#define MASK_PUB_APB_RF_AON_ARQOS 0xf
+#define MASK_PUB_APB_RF_AWQOS_THRESHOLD_ISP_VDSP 0xf0
+#define MASK_PUB_APB_RF_ARQOS_THRESHOLD_ISP_VDSP 0xf
+#define MASK_PUB_APB_RF_PUB_CLK_DFS_SLEEP_AUTO_GATE_EN 0x80000000
+#define MASK_PUB_APB_RF_CLK_AON_APB_AUTO_GATE_EN 0x40000000
+#define MASK_PUB_APB_RF_CLK_DMC_REF_AUTO_GATE_EN 0x20000000
+#define MASK_PUB_APB_RF_PUB_CLK_DFS_AUTO_GATE_EN 0x10000000
+#define MASK_PUB_APB_RF_DMC_DFI_MON_AUTO_GATE_EN 0x8000000
+#define MASK_PUB_APB_RF_DMC_SREF_AUTO_GATE_EN 0x4000000
+#define MASK_PUB_APB_RF_DDR_PHY_AUTO_GATE_EN 0x2000000
+#define MASK_PUB_APB_RF_DDR_UMCTL_AUTO_GATE_EN 0x1000000
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_BIST_EB 0x800000
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_REF_EB 0x400000
+#define MASK_PUB_APB_RF_PUB_CLK_CSSYS_EB 0x200000
+#define MASK_PUB_APB_RF_PUB_CLK_AON_APB_EB 0x100000
+#define MASK_PUB_APB_RF_PUB_CLK_PHY_X2_FORCE_PHASE 0xc0000
+#define MASK_PUB_APB_RF_PUB_CLK_PHY_X2_FORCE_PHASE_SEL 0x20000
+#define MASK_PUB_APB_RF_PUB_CLK_PHY_X2_FORCE_BYP 0x10000
+#define MASK_PUB_APB_RF_PUB_CLK_DFS_EB 0x8000
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_X1_PTM_EB 0x4000
+#define MASK_PUB_APB_RF_PUB_CLK_MLB_D2_EB 0x2000
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_D2_EB 0x1000
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_X1_EB 0x800
+#define MASK_PUB_APB_RF_PUB_CLK_PHY_X2_EB 0x400
+#define MASK_PUB_APB_RF_PUB_CLK_DCC_EB 0x200
+#define MASK_PUB_APB_RF_PUB_DDR_CLK_EB 0x100
+#define MASK_PUB_APB_RF_TIMER_CLK_AON_APB_OPEN_EN 0x80
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_X1_PTM_AUTO_GATE_EN 0x40
+#define MASK_PUB_APB_RF_PUB_CLK_MLB_D2_CGM_SEL 0x20
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_D2_CGM_SEL 0x10
+#define MASK_PUB_APB_RF_PUB_CLK_DMC_X1_CGM_SEL 0x8
+#define MASK_PUB_APB_RF_PUB_CLK_PHY_X2_CGM_SEL 0x4
+#define MASK_PUB_APB_RF_PUB_CLK_DCC_CGM_SEL 0x2
+#define MASK_PUB_APB_RF_PUB_DDR_CLK_CGM_SEL 0x1
+#define MASK_PUB_APB_RF_DMC_CLK_INIT_SW_START 0x1
+#define MASK_PUB_APB_RF_DFS_LP_CTRL_CUR_STATE 0x7000
+#define MASK_PUB_APB_RF_DMC_CLK_HW_CUR_STATE 0xf0
+#define MASK_PUB_APB_RF_DMC_CUR_CLK_MODE 0xc
+#define MASK_PUB_APB_RF_DMC_CLK_INIT_SW_DONE 0x1
+#define MASK_PUB_APB_RF_DMC_STOP_WAIT_CNT 0xff0000
+#define MASK_PUB_APB_RF_DMC_SLEEP_FORCE_FINISH_MODE 0x100
+#define MASK_PUB_APB_RF_DESKEW_PLL_PD_DEFAULT_SW 0x20
+#define MASK_PUB_APB_RF_DESKEW_PLL_PD_DEFAULT_SEL 0x10
+#define MASK_PUB_APB_RF_DMC_SLEEP_CLK_AUTO_MODE 0x2
+#define MASK_PUB_APB_RF_DFS_CLK_AUTO_MODE 0x1
+#define MASK_PUB_APB_RF_DSKDLL_DCC_FINE_WAIT_SRC_SW 0x400
+#define MASK_PUB_APB_RF_DSKDLL_DCC_COARSE_WAIT_SRC_SW 0x200
+#define MASK_PUB_APB_RF_DSKPLL_LOCK_WAIT_SRC_SW 0x100
+#define MASK_PUB_APB_RF_DDL_ADJS_V_WAIT_EN 0x8
+#define MASK_PUB_APB_RF_DSKDLL_DCC_FINE_WAIT_EN 0x4
+#define MASK_PUB_APB_RF_DSKDLL_DCC_COARSE_WAIT_EN 0x2
+#define MASK_PUB_APB_RF_DSKPLL_LOCK_WAIT_EN 0x1
+#define MASK_PUB_APB_RF_WAIT_CNT_DSKPLL_PWRON_TIME 0xffff0000
+#define MASK_PUB_APB_RF_WAIT_CNT_DSKPLL_LOCK_TIME 0xffff
+#define MASK_PUB_APB_RF_WAIT_CNT_DSKDLL_DCC_FINE_TIME 0xffff0000
+#define MASK_PUB_APB_RF_WAIT_CNT_DSKDLL_DCC_COARSE_TIME 0xffff
+#define MASK_PUB_APB_RF_WAIT_CNT_DFS_RESET_OFF_TIME 0xff000000
+#define MASK_PUB_APB_RF_WAIT_CNT_DFS_RESET_ON_TIME 0xff0000
+#define MASK_PUB_APB_RF_WAIT_CNT_DFS_CLK_OFF_TIME 0xff
+#define MASK_PUB_APB_RF_WAIT_CNT_DDL_ADJS_V_HIGH_TIME 0xff0000
+#define MASK_PUB_APB_RF_WAIT_CNT_DDL_ADJS_V_LOW_TIME 0xff
+#define MASK_PUB_APB_RF_PTEST_DDL_SCOUT 0x4000000
+#define MASK_PUB_APB_RF_PTEST_DDL_SCIN 0x2000000
+#define MASK_PUB_APB_RF_PTEST_DDL_SE 0x1000000
+#define MASK_PUB_APB_RF_DMC_DDL_SW_ADJS 0x1ff00
+#define MASK_PUB_APB_RF_DMC_DDL_SW_UPDATE 0x80
+#define MASK_PUB_APB_RF_DMC_DDL_SW_BYPASS 0x40
+#define MASK_PUB_APB_RF_DMC_DDL_SW_RESET 0x20
+#define MASK_PUB_APB_RF_DMC_DDL_SW_ADJS_VALID 0x10
+#define MASK_PUB_APB_RF_DMC_DDL_CFG_SRC_PURE_SW 0x2
+#define MASK_PUB_APB_RF_DMC_DDL_CFG_SRC_SW 0x1
+#define MASK_PUB_APB_RF_PUB_DFS_SW_LOCK_REQ 0x8000000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_LOCK_MODE 0x4000000
+#define MASK_PUB_APB_RF_EMC_CKG_MODE_PURE_SW 0x3000000
+#define MASK_PUB_APB_RF_EMC_CKG_D2_SEL_PURE_SW 0xf00000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_CLK_MODE 0xc0000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_DENY 0x10000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_ACK 0x8000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_RESP 0x4000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_FC_REQ 0x2000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_REQ 0x1000
+#define MASK_PUB_APB_RF_PURE_SW_DFS_FC_ACK 0x800
+#define MASK_PUB_APB_RF_PURE_SW_DFS_FRQ_SEL 0x700
+#define MASK_PUB_APB_RF_EMC_CKG_SEL_PURE_SW 0xfe
+#define MASK_PUB_APB_RF_DFS_SW_DFS_MODE 0x1
+#define MASK_PUB_APB_RF_PUB_DFS_SWITCH_TYPE 0x80000000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_SWITCH_PERIOD 0x3fc00000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_RATIO_DEFAULT 0x3f8000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_RATIO 0x7f00
+#define MASK_PUB_APB_RF_PUB_DFS_SW_DENY 0x80
+#define MASK_PUB_APB_RF_PUB_DFS_SW_FRQ_SEL 0x70
+#define MASK_PUB_APB_RF_PUB_DFS_SW_RESP 0x8
+#define MASK_PUB_APB_RF_PUB_DFS_SW_ACK 0x4
+#define MASK_PUB_APB_RF_PUB_DFS_SW_REQ 0x2
+#define MASK_PUB_APB_RF_PUB_DFS_SW_ENABLE 0x1
+#define MASK_PUB_APB_RF_PUB_DFS_SW_UG_DENY_EN 0x400000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_LP_DENY_EN 0x200000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_UG_CHK_EN 0x100000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_CLK_MODE_DEFAULT 0xc0000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_CLK_MODE 0x30000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_RATIO_D2_DEFAULT 0xf00
+#define MASK_PUB_APB_RF_PUB_DFS_SW_RATIO_D2 0xf
+#define MASK_PUB_APB_RF_PUB_DFS_SW_DDL_ADJS_DEFAULT 0x1ff0000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_DDL_ADJS 0x1ff
+#define MASK_PUB_APB_RF_PUB_DFS_URGENT_WAIT_TIMEOUT_PERIOD 0xffc0000
+#define MASK_PUB_APB_RF_PUB_DFS_URGENT_WAIT_TIMEOUT_EN 0x20000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_URGENT_WAIT_EN 0x10000
+#define MASK_PUB_APB_RF_PUB_DFS_SW_URGENT_DENY_EN 0xffff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_DDL_ADJS_DEFAULT 0x7fc00000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_CLK_MODE_DEFAULT 0x300000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_RATIO_D2_DEFAULT 0xf0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_RATIO_DEFAULT 0x7f00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_INITIAL_FREQ 0x70
+#define MASK_PUB_APB_RF_PUB_DFS_HW_STOP 0x4
+#define MASK_PUB_APB_RF_PUB_DFS_HW_START 0x2
+#define MASK_PUB_APB_RF_PUB_DFS_HW_ENABLE 0x1
+#define MASK_PUB_APB_RF_SW_FORCE_EXIT_SW_LP_WAIT_ACK 0x80000000
+#define MASK_PUB_APB_RF_SW_FORCE_EXIT_HW_LP_WAIT_ACK 0x40000000
+#define MASK_PUB_APB_RF_SW_FORCE_EXIT_LP_WAIT_REQ 0x20000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_FREQ_UP_FORCE_TRIG 0x10000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_BWMON_MAX_EN 0x8000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_BWMON_MAX_FREQ 0x7000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_AVAIL_FREQ_EN 0xff0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_CHECK_PLL_EN 0x1000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_FREQ_UP 0x700
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_FREQ_DN 0x70
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_EN_UP 0x8
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_EN_DN 0x4
+#define MASK_PUB_APB_RF_PUB_DFS_HW_MIN_LOAD 0x2
+#define MASK_PUB_APB_RF_PUB_DFS_LP_PROT_EN 0x1
+#define MASK_PUB_APB_RF_DFS_INC_REQ_HOLD_EN 0x80000000
+#define MASK_PUB_APB_RF_DFS_DEC_TO_INC_EN 0x40000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_DEC_UG_DENY_EN 0x20000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_INC_UG_DENY_EN 0x10000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_DEC_LP_DENY_EN 0x8000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_INC_LP_DENY_EN 0x4000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_DEC_UG_CHK_EN 0x2000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_INC_UG_CHK_EN 0x1000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_URGENT_WAIT_EN 0x10000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_URGENT_DENY_EN 0xffff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F3_RATIO 0x7f000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F2_RATIO 0x7f0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F1_RATIO 0x7f00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F0_RATIO 0x7f
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F7_RATIO 0x7f000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F6_RATIO 0x7f0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F5_RATIO 0x7f00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F4_RATIO 0x7f
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F7_RATIO_D2 0xf0000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F6_RATIO_D2 0xf000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F5_RATIO_D2 0xf00000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F4_RATIO_D2 0xf0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F3_RATIO_D2 0xf000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F2_RATIO_D2 0xf00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F1_RATIO_D2 0xf0
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F0_RATIO_D2 0xf
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F7_CLK_MODE 0xc000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F6_CLK_MODE 0x3000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F5_CLK_MODE 0xc00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F4_CLK_MODE 0x300
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F3_CLK_MODE 0xc0
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F2_CLK_MODE 0x30
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F1_CLK_MODE 0xc
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F0_CLK_MODE 0x3
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F1_DDL_ADJS 0x1ff0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F0_DDL_ADJS 0x1ff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F3_DDL_ADJS 0x1ff0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F2_DDL_ADJS 0x1ff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F5_DDL_ADJS 0x1ff0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F4_DDL_ADJS 0x1ff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F7_DDL_ADJS 0x1ff0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F6_DDL_ADJS 0x1ff
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F7_REQ_DURATION 0xf0000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F6_REQ_DURATION 0xf000000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F5_REQ_DURATION 0xf00000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F4_REQ_DURATION 0xf0000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F3_REQ_DURATION 0xf000
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F2_REQ_DURATION 0xf00
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F1_REQ_DURATION 0xf0
+#define MASK_PUB_APB_RF_PUB_DFS_HW_F0_REQ_DURATION 0xf
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PD_DEEP_SLEEP_MODE 0xff000000
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PD_AUTO_LIGHT_SLEEP_MODE 0xff0000
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PD_SMART_LIGHT_SLEEP_MODE 0xff00
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PD_DEFAULT_BYP_MODE 0xff
+#define MASK_PUB_APB_RF_DFS_FC_ACK_ASSERT_WAIT_CNT 0xff00
+#define MASK_PUB_APB_RF_DFS_HW_FRQ_SEL_SW 0x70
+#define MASK_PUB_APB_RF_DFS_HW_FRQ_SEL_SET 0x8
+#define MASK_PUB_APB_RF_DFS_CUR_CLK_MODE_TOGGLE 0x4
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PD_DEFAULT_HIGH 0x2
+#define MASK_PUB_APB_RF_HW_DESKEW_PLL_PO_AHEAD_EN 0x1
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F7 0x70000000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F6 0x7000000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F5 0x700000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F4 0x70000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F3 0x7000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F2 0x700
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F1 0x70
+#define MASK_PUB_APB_RF_VDDCORE_VOL_F0 0x7
+#define MASK_PUB_APB_RF_VDDCORE_VOL_CUR 0x1c000000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_DFLT 0x3800000
+#define MASK_PUB_APB_RF_VDDCORE_VOL_SET 0x400000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_ACK 0x200000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_REQ_SW 0x100000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_VOL_SW 0xe0000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_DEC_EN 0xff00
+#define MASK_PUB_APB_RF_VDDCORE_DVS_INC_EN 0xff
+#define MASK_PUB_APB_RF_VDDCORE_DVS_VOL 0xe00000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_REQ 0x100000
+#define MASK_PUB_APB_RF_HW_DFS_AUTO_DIS 0x80000
+#define MASK_PUB_APB_RF_HW_DFS_TARGET_FSP 0x70000
+#define MASK_PUB_APB_RF_VDDCORE_DVS_DN_SW_EN 0xff00
+#define MASK_PUB_APB_RF_VDDCORE_DVS_UP_SW_EN 0xff
+#define MASK_PUB_APB_RF_DVS_DEC_BLOCK_TIME 0xffffffff
+#define MASK_PUB_APB_RF_DFS_VOTE_DEC_EN 0x80000000
+#define MASK_PUB_APB_RF_VOTE_HW_DFS_DEC_MASK_EN 0x40000000
+#define MASK_PUB_APB_RF_VOTE_HW_DFS_INC_MASK_EN 0x20000000
+#define MASK_PUB_APB_RF_RF_DFS_INTERVAL_CNT 0x3fff8000
+#define MASK_PUB_APB_RF_RF_VOTE_INTERVAL_CNT 0x7fff
+#define MASK_PUB_APB_RF_RF_THRD_INC_F1 0x3fff0000
+#define MASK_PUB_APB_RF_RF_THRD_INC_F0 0x3fff
+#define MASK_PUB_APB_RF_RF_THRD_INC_F3 0x3fff0000
+#define MASK_PUB_APB_RF_RF_THRD_INC_F2 0x3fff
+#define MASK_PUB_APB_RF_RF_THRD_INC_F5 0x3fff0000
+#define MASK_PUB_APB_RF_RF_THRD_INC_F4 0x3fff
+#define MASK_PUB_APB_RF_RF_THRD_INC_F7 0x3fff0000
+#define MASK_PUB_APB_RF_RF_THRD_INC_F6 0x3fff
+#define MASK_PUB_APB_RF_TEST_DSKPLL_BIST_CNT 0xffff
+#define MASK_PUB_APB_RF_DFS_COUNT_EN 0x200
+#define MASK_PUB_APB_RF_PUB_DFS_STA_EN 0x100
+#define MASK_PUB_APB_RF_DMC_ST_MON_SEL 0x6
+#define MASK_PUB_APB_RF_PUB_TOP_MON_EN 0x1
+#define MASK_PUB_APB_RF_DMC_ST_IDLE_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DMC_ST_WRITE_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DMC_ST_READ_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DMC_ST_SREF_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DMC_ST_LIGHT_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DMC_ST_SREF_CNT 0xffff0000
+#define MASK_PUB_APB_RF_DMC_ST_LIGHT_CNT 0xffff
+#define MASK_PUB_APB_RF_DFS_F0_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F1_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F2_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F3_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F4_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F5_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F6_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_DFS_F7_CYCLE_CNT 0xffffffff
+#define MASK_PUB_APB_RF_PUB_DFS_DBM_BW_VALID_BYPASS_PERIOD 0x3fc00
+#define MASK_PUB_APB_RF_DFS_COUNT 0x3ff
+#define MASK_PUB_APB_RF_RF_DPU_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_DPU_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_RF_HW_VOTE_DPU_FLAG_EN 0x20000000
+#define MASK_PUB_APB_RF_BFV_VOTE_DPU_SW 0x2000000
+#define MASK_PUB_APB_RF_VOTE_DPU_ACK 0x800000
+#define MASK_PUB_APB_RF_VOTE_DPU_HW_ACK 0x400000
+#define MASK_PUB_APB_RF_FREQ_VOTE_DPU 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_DPU 0x3fff
+#define MASK_PUB_APB_RF_RF_DCAM_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_DCAM_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_RF_HW_VOTE_DCAM_FLAG_EN 0x20000000
+#define MASK_PUB_APB_RF_BFV_VOTE_DCAM_SW 0x2000000
+#define MASK_PUB_APB_RF_VOTE_DCAM_ACK 0x800000
+#define MASK_PUB_APB_RF_VOTE_DCAM_HW_ACK 0x400000
+#define MASK_PUB_APB_RF_FREQ_VOTE_DCAM 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_DCAM 0x3fff
+#define MASK_PUB_APB_RF_RF_PUBCP_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_PUBCP_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_BW_VOTE_PUBCP_FLAG 0x2000000
+#define MASK_PUB_APB_RF_FREQ_VOTE_PUBCP_FLAG 0x1000000
+#define MASK_PUB_APB_RF_VOTE_PUBCP_ACK 0x800000
+#define MASK_PUB_APB_RF_FREQ_VOTE_PUBCP 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_PUBCP 0x3fff
+#define MASK_PUB_APB_RF_RF_WTLCP_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_WTLCP_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_BW_VOTE_WTLCP_FLAG 0x2000000
+#define MASK_PUB_APB_RF_FREQ_VOTE_WTLCP_FLAG 0x1000000
+#define MASK_PUB_APB_RF_VOTE_WTLCP_ACK 0x800000
+#define MASK_PUB_APB_RF_FREQ_VOTE_WTLCP 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_WTLCP 0x3fff
+#define MASK_PUB_APB_RF_RF_WTLCP1_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_WTLCP1_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_BW_VOTE_WTLCP1_FLAG 0x2000000
+#define MASK_PUB_APB_RF_FREQ_VOTE_WTLCP1_FLAG 0x1000000
+#define MASK_PUB_APB_RF_VOTE_WTLCP1_ACK 0x800000
+#define MASK_PUB_APB_RF_FREQ_VOTE_WTLCP1 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_WTLCP1 0x3fff
+#define MASK_PUB_APB_RF_RF_AGCP_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_AGCP_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_BW_VOTE_AGCP_FLAG 0x2000000
+#define MASK_PUB_APB_RF_FREQ_VOTE_AGCP_FLAG 0x1000000
+#define MASK_PUB_APB_RF_VOTE_AGCP_ACK 0x800000
+#define MASK_PUB_APB_RF_FREQ_VOTE_AGCP 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_AGCP 0x3fff
+#define MASK_PUB_APB_RF_RF_SW_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_SW_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_BW_VOTE_SW_FLAG 0x2000000
+#define MASK_PUB_APB_RF_FREQ_VOTE_SW_FLAG 0x1000000
+#define MASK_PUB_APB_RF_VOTE_SW_ACK 0x800000
+#define MASK_PUB_APB_RF_FREQ_VOTE_SW 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_SW 0x3fff
+#define MASK_PUB_APB_RF_RF_VDSP_BV_EN 0x80000000
+#define MASK_PUB_APB_RF_RF_VDSP_FV_EN 0x40000000
+#define MASK_PUB_APB_RF_RF_HW_VOTE_VDSP_FLAG_EN 0x20000000
+#define MASK_PUB_APB_RF_BFV_VOTE_VDSP_SW 0x2000000
+#define MASK_PUB_APB_RF_VOTE_VDSP_ACK 0x800000
+#define MASK_PUB_APB_RF_VOTE_VDSP_HW_ACK 0x400000
+#define MASK_PUB_APB_RF_FREQ_VOTE_VDSP 0x70000
+#define MASK_PUB_APB_RF_BW_VOTE_VDSP 0x3fff
+#define MASK_PUB_APB_RF_DFS_GFREE_HW_BYPASS_EN 0x1000000
+#define MASK_PUB_APB_RF_DFS_GFREE_SW_OPEN_DELAY 0x7fc00
+#define MASK_PUB_APB_RF_DFS_GFREE_SW_CLOSE_DELAY 0x3fe
+#define MASK_PUB_APB_RF_DFS_GFREE_SW_BYPASS 0x1
+#define MASK_PUB_APB_RF_PUB_DFS_SW_SWITCH_PERIOD_APPEND 0xf
+#define MASK_PUB_APB_RF_AWURGENT_DBG_AGCP 0x300000
+#define MASK_PUB_APB_RF_AWURGENT_DBG_WTLCP 0xc0000
+#define MASK_PUB_APB_RF_AWURGENT_DBG_PUBCP 0x30000
+#define MASK_PUB_APB_RF_AWURGENT_DBG_AON 0xc000
+#define MASK_PUB_APB_RF_AWURGENT_DBG_AP 0x3000
+#define MASK_PUB_APB_RF_AWURGENT_DBG_VDSP 0xc00
+#define MASK_PUB_APB_RF_AWURGENT_DBG_MM_ISP 0x300
+#define MASK_PUB_APB_RF_AWURGENT_DBG_ISP_RAW 0xc0
+#define MASK_PUB_APB_RF_AWURGENT_DBG_DPU 0x30
+#define MASK_PUB_APB_RF_AWURGENT_DBG_GPU 0xc
+#define MASK_PUB_APB_RF_AWURGENT_DBG_CPU 0x3
+#define MASK_PUB_APB_RF_ARURGENT_DBG_AGCP 0x300000
+#define MASK_PUB_APB_RF_ARURGENT_DBG_WTLCP 0xc0000
+#define MASK_PUB_APB_RF_ARURGENT_DBG_PUBCP 0x30000
+#define MASK_PUB_APB_RF_ARURGENT_DBG_AON 0xc000
+#define MASK_PUB_APB_RF_ARURGENT_DBG_AP 0x3000
+#define MASK_PUB_APB_RF_ARURGENT_DBG_VDSP 0xc00
+#define MASK_PUB_APB_RF_ARURGENT_DBG_MM_ISP 0x300
+#define MASK_PUB_APB_RF_ARURGENT_DBG_ISP_RAW 0xc0
+#define MASK_PUB_APB_RF_ARURGENT_DBG_DPU 0x30
+#define MASK_PUB_APB_RF_ARURGENT_DBG_GPU 0xc
+#define MASK_PUB_APB_RF_ARURGENT_DBG_CPU 0x3
+#define MASK_PUB_APB_RF_SRE_FLAG_DBG 0x2
+#define MASK_PUB_APB_RF_SRE_REQ_DBG 0x1
+#define MASK_PUB_APB_RF_PUB0_DUMMY_REG0 0xfffffffe
+#define MASK_PUB_APB_RF_DPLL0_CLKOUT_DIV32_EN 0x1
+#define MASK_PUB_APB_RF_PUB0_DUMMY_REG1 0xffffffff
+#define MASK_REG_FW1_AP_MERGE_M1_LPC_RD_SEC 0x80000000
+#define MASK_REG_FW1_AP_MERGE_M0_LPC_RD_SEC 0x40000000
+#define MASK_REG_FW1_AP_S4_LPC_RD_SEC 0x20000000
+#define MASK_REG_FW1_AP_S3_LPC_RD_SEC 0x10000000
+#define MASK_REG_FW1_AP_S2_LPC_RD_SEC 0x8000000
+#define MASK_REG_FW1_AP_S1_LPC_RD_SEC 0x4000000
+#define MASK_REG_FW1_AP_S0_LPC_RD_SEC 0x2000000
+#define MASK_REG_FW1_AP_MAIN_LPC_RD_SEC 0x1000000
+#define MASK_REG_FW1_AP_M7_LPC_RD_SEC 0x800000
+#define MASK_REG_FW1_AP_M6_LPC_RD_SEC 0x400000
+#define MASK_REG_FW1_AP_M5_LPC_RD_SEC 0x200000
+#define MASK_REG_FW1_AP_M4_LPC_RD_SEC 0x100000
+#define MASK_REG_FW1_AP_M3_LPC_RD_SEC 0x80000
+#define MASK_REG_FW1_AP_M2_LPC_RD_SEC 0x40000
+#define MASK_REG_FW1_AP_M1_LPC_RD_SEC 0x20000
+#define MASK_REG_FW1_AP_M0_LPC_RD_SEC 0x10000
+#define MASK_REG_FW1_AP_AP_ASYNC_BRG_RD_SEC 0x8000
+#define MASK_REG_FW1_AP_S5_LPC_RD_SEC 0x4000
+#define MASK_REG_FW1_AP_S6_LPC_RD_SEC 0x2000
+#define MASK_REG_FW1_AP_DISP_ASYNC_BRG_RD_SEC 0x1000
+#define MASK_REG_FW1_AP_VDSP_ASYNC_BRG_RD_SEC 0x800
+#define MASK_REG_FW1_AP_MISC_CKG_EN_RD_SEC 0x400
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_ON_1_RD_SEC 0x200
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_ON_0_RD_SEC 0x100
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_OFF_1_RD_SEC 0x80
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_OFF_0_RD_SEC 0x40
+#define MASK_REG_FW1_AP_CLOCK_FREQUENCY_DOWN_RD_SEC 0x20
+#define MASK_REG_FW1_AP_HOLDING_PEN_RD_SEC 0x10
+#define MASK_REG_FW1_AP_AP_SYS_AUTO_SLEEP_CFG_RD_SEC 0x8
+#define MASK_REG_FW1_AP_AP_SYS_FORCE_SLEEP_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AP_AHB_RST_RD_SEC 0x2
+#define MASK_REG_FW1_AP_AHB_EB_RD_SEC 0x1
+#define MASK_REG_FW1_AP_CHIP_ID_RD_SEC 0x40000000
+#define MASK_REG_FW1_AP_VDSP_INT_CTRL_RD_SEC 0x20000000
+#define MASK_REG_FW1_AP_VDSP_LP_CTRL_RD_SEC 0x10000000
+#define MASK_REG_FW1_AP_VDSP_FATAL_INFO_HIGH_RD_SEC 0x8000000
+#define MASK_REG_FW1_AP_VDSP_FATAL_INFO_LOW_RD_SEC 0x4000000
+#define MASK_REG_FW1_AP_VDSP_FUNC_CTRL_RD_SEC 0x2000000
+#define MASK_REG_FW1_AP_DSI_PHY_RD_SEC 0x1000000
+#define MASK_REG_FW1_AP_AP_QOS_CFG_RD_SEC 0x800000
+#define MASK_REG_FW1_AP_CACHE_EMMC_SDIO_RD_SEC 0x400000
+#define MASK_REG_FW1_AP_SYS_RST_RD_SEC 0x200000
+#define MASK_REG_FW1_AP_MERGE_VDMA_S0_LPC_RD_SEC 0x100000
+#define MASK_REG_FW1_AP_MERGE_VDMA_M1_LPC_RD_SEC 0x80000
+#define MASK_REG_FW1_AP_MERGE_VDMA_M0_LPC_RD_SEC 0x40000
+#define MASK_REG_FW1_AP_MERGE_VDSP_S1_LPC_RD_SEC 0x20000
+#define MASK_REG_FW1_AP_MERGE_VDSP_S0_LPC_RD_SEC 0x10000
+#define MASK_REG_FW1_AP_MERGE_VDSP_MAIN_LPC_RD_SEC 0x8000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M3_LPC_RD_SEC 0x4000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M2_LPC_RD_SEC 0x2000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M1_LPC_RD_SEC 0x1000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M0_LPC_RD_SEC 0x800
+#define MASK_REG_FW1_AP_AP_QOS3_SEL_RD_SEC 0x400
+#define MASK_REG_FW1_AP_AP_QOS3_RD_SEC 0x200
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_VDSP_RD_SEC 0x100
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_AP_RD_SEC 0x80
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_DISP_RD_SEC 0x40
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_IDLE_OVERFLOW_RD_SEC 0x20
+#define MASK_REG_FW1_AP_AP_QOS2_RD_SEC 0x10
+#define MASK_REG_FW1_AP_AP_QOS1_RD_SEC 0x8
+#define MASK_REG_FW1_AP_AP_QOS0_RD_SEC 0x4
+#define MASK_REG_FW1_AP_MERGE_S0_LPC_RD_SEC 0x2
+#define MASK_REG_FW1_AP_S7_LPC_RD_SEC 0x1
+#define MASK_REG_FW1_AP_MERGE_M1_LPC_WR_SEC 0x80000000
+#define MASK_REG_FW1_AP_MERGE_M0_LPC_WR_SEC 0x40000000
+#define MASK_REG_FW1_AP_S4_LPC_WR_SEC 0x20000000
+#define MASK_REG_FW1_AP_S3_LPC_WR_SEC 0x10000000
+#define MASK_REG_FW1_AP_S2_LPC_WR_SEC 0x8000000
+#define MASK_REG_FW1_AP_S1_LPC_WR_SEC 0x4000000
+#define MASK_REG_FW1_AP_S0_LPC_WR_SEC 0x2000000
+#define MASK_REG_FW1_AP_MAIN_LPC_WR_SEC 0x1000000
+#define MASK_REG_FW1_AP_M7_LPC_WR_SEC 0x800000
+#define MASK_REG_FW1_AP_M6_LPC_WR_SEC 0x400000
+#define MASK_REG_FW1_AP_M5_LPC_WR_SEC 0x200000
+#define MASK_REG_FW1_AP_M4_LPC_WR_SEC 0x100000
+#define MASK_REG_FW1_AP_M3_LPC_WR_SEC 0x80000
+#define MASK_REG_FW1_AP_M2_LPC_WR_SEC 0x40000
+#define MASK_REG_FW1_AP_M1_LPC_WR_SEC 0x20000
+#define MASK_REG_FW1_AP_M0_LPC_WR_SEC 0x10000
+#define MASK_REG_FW1_AP_AP_ASYNC_BRG_WR_SEC 0x8000
+#define MASK_REG_FW1_AP_S5_LPC_WR_SEC 0x4000
+#define MASK_REG_FW1_AP_S6_LPC_WR_SEC 0x2000
+#define MASK_REG_FW1_AP_DISP_ASYNC_BRG_WR_SEC 0x1000
+#define MASK_REG_FW1_AP_VDSP_ASYNC_BRG_WR_SEC 0x800
+#define MASK_REG_FW1_AP_MISC_CKG_EN_WR_SEC 0x400
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_ON_1_WR_SEC 0x200
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_ON_0_WR_SEC 0x100
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_OFF_1_WR_SEC 0x80
+#define MASK_REG_FW1_AP_AP_SYS_CLK_EN_FRC_OFF_0_WR_SEC 0x40
+#define MASK_REG_FW1_AP_CLOCK_FREQUENCY_DOWN_WR_SEC 0x20
+#define MASK_REG_FW1_AP_HOLDING_PEN_WR_SEC 0x10
+#define MASK_REG_FW1_AP_AP_SYS_AUTO_SLEEP_CFG_WR_SEC 0x8
+#define MASK_REG_FW1_AP_AP_SYS_FORCE_SLEEP_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AP_AHB_RST_WR_SEC 0x2
+#define MASK_REG_FW1_AP_AHB_EB_WR_SEC 0x1
+#define MASK_REG_FW1_AP_CHIP_ID_WR_SEC 0x40000000
+#define MASK_REG_FW1_AP_VDSP_INT_CTRL_WR_SEC 0x20000000
+#define MASK_REG_FW1_AP_VDSP_LP_CTRL_WR_SEC 0x10000000
+#define MASK_REG_FW1_AP_VDSP_FATAL_INFO_HIGH_WR_SEC 0x8000000
+#define MASK_REG_FW1_AP_VDSP_FATAL_INFO_LOW_WR_SEC 0x4000000
+#define MASK_REG_FW1_AP_VDSP_FUNC_CTRL_WR_SEC 0x2000000
+#define MASK_REG_FW1_AP_DSI_PHY_WR_SEC 0x1000000
+#define MASK_REG_FW1_AP_AP_QOS_CFG_WR_SEC 0x800000
+#define MASK_REG_FW1_AP_CACHE_EMMC_SDIO_WR_SEC 0x400000
+#define MASK_REG_FW1_AP_SYS_RST_WR_SEC 0x200000
+#define MASK_REG_FW1_AP_MERGE_VDMA_S0_LPC_WR_SEC 0x100000
+#define MASK_REG_FW1_AP_MERGE_VDMA_M1_LPC_WR_SEC 0x80000
+#define MASK_REG_FW1_AP_MERGE_VDMA_M0_LPC_WR_SEC 0x40000
+#define MASK_REG_FW1_AP_MERGE_VDSP_S1_LPC_WR_SEC 0x20000
+#define MASK_REG_FW1_AP_MERGE_VDSP_S0_LPC_WR_SEC 0x10000
+#define MASK_REG_FW1_AP_MERGE_VDSP_MAIN_LPC_WR_SEC 0x8000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M3_LPC_WR_SEC 0x4000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M2_LPC_WR_SEC 0x2000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M1_LPC_WR_SEC 0x1000
+#define MASK_REG_FW1_AP_MERGE_VDSP_M0_LPC_WR_SEC 0x800
+#define MASK_REG_FW1_AP_AP_QOS3_SEL_WR_SEC 0x400
+#define MASK_REG_FW1_AP_AP_QOS3_WR_SEC 0x200
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_VDSP_WR_SEC 0x100
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_AP_WR_SEC 0x80
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_DEBUG_SIGNAL_W_DISP_WR_SEC 0x40
+#define MASK_REG_FW1_AP_ASYNC_BRIDGE_IDLE_OVERFLOW_WR_SEC 0x20
+#define MASK_REG_FW1_AP_AP_QOS2_WR_SEC 0x10
+#define MASK_REG_FW1_AP_AP_QOS1_WR_SEC 0x8
+#define MASK_REG_FW1_AP_AP_QOS0_WR_SEC 0x4
+#define MASK_REG_FW1_AP_MERGE_S0_LPC_WR_SEC 0x2
+#define MASK_REG_FW1_AP_S7_LPC_WR_SEC 0x1
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY0 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY1 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY2 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY3 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY4 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY5 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY6 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY7 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY8 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY9 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY10 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY11 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY12 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY13 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY14 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY15 0xffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY0 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY1 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY2 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY3 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY4 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY5 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY6 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY7 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY8 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY9 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY10 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY11 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY12 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY13 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY14 0xffffffff
+#define MASK_REG_FW1_AP_BIT_CTRL_ARRAY15 0xffffffff
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTHSCLK 0x10
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSCLK 0x8
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXITCLK 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATECLK 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ULPSACTIVENOTCLK 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_0 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_0 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_0 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_0 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_0 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_0 0x3c
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_0 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_0 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_1 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_1 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_1 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_1 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_1 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_1 0x3c
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_1 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_1 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_2 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_2 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_2 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_2 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_2 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_2 0x3c
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_2 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_2 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_3 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_3 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_3 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_3 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_3 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_3 0x3c
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_3 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXREADYESC_3 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_0 0xff000000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_1 0xff0000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_2 0xff00
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_3 0xff
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_0 0x800000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_0 0x780000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_0 0x40000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_1 0x20000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_1 0x1e000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_1 0x1000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_2 0x800
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_2 0x780
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_2 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXLPDTESC_3 0x20
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXTRIGGERESC_3 0x1e
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RXVALIDESC_3 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_0 0x80000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_0 0x40000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_0 0x20000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_0 0x10000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_0 0x8000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_1 0x4000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_1 0x2000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_1 0x1000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_1 0x800
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_1 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_2 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_2 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_2 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_2 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_2 0x20
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRESC_3 0x10
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRSYNCESC_3 0x8
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTROL_3 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP0_3 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ERRCONTENTIONLP1_3 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S 0x200000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L 0x100000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_SHUTDOWNZ 0x80000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RSTZ 0x40000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_0 0x20000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_1 0x10000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_2 0x8000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_3 0x4000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ENABLECLK 0x2000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCEPLL 0x1000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_PLLLOCK 0x800
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_BISTON 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_BISTDONE 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_IF_SEL 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TRIMBG 0xf0
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TX_RCTL 0xf
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RESERVED 0xff00
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_RESERVEDO 0xff
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TESTDIN 0x7f800
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TESTDOUT 0x7f8
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TESTEN 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLK 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLR 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_0 0x400000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_0 0x200000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_0 0x100000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_0 0x80000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_0 0x40000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_0 0x20000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_1 0x10000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_1 0x8000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_1 0x4000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_1 0x2000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_1 0x1000
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_2 0x800
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_2 0x400
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_2 0x200
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_2 0x100
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_2 0x80
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_2 0x40
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_3 0x20
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_DIRECTION_3 0x10
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TURNDISABLE_3 0x8
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCERXMODE_3 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_FORCETXSTOPMODE_3 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_STOPSTATEDATA_3 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_0 0x8
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_1 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_2 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_3 0x1
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_DIV6CLK_GATEEN 0x4
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_PHY_MODE 0x2
+#define MASK_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTHSCLK 0x80000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSCLK 0x40000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXITCLK 0x20000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_0 0x10000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_0 0x8000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXLPDTESC_0 0x4000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_0 0x2000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_0 0x1000000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXTRIGGERESC_0 0x800000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXVALIDESC_0 0x400000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_1 0x200000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_1 0x100000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_1 0x80000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_1 0x40000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_2 0x20000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_2 0x10000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_2 0x8000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_2 0x4000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTDATAHS_3 0x2000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXREQUESTESC_3 0x1000
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSESC_3 0x800
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXULPSEXIT_3 0x400
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXDATAESC_0 0x200
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S 0x100
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L 0x80
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_SHUTDOWNZ 0x40
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_RSTZ 0x20
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_0 0x10
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_1 0x8
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_2 0x4
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLE_3 0x2
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ENABLECLK 0x1
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PHY_MODE 0x800
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_FORCEPLL 0x400
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTDIN 0x200
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTEN 0x100
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLK 0x80
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TESTCLR 0x40
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TURNREQUEST_0 0x20
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_0 0x10
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_1 0x8
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_2 0x4
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_TXSKEWCALHS_3 0x2
+#define MASK_ANLG_PHY_G1_RF_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_ISO_SW_EN 0x1
+#define MASK_AON_SEC_APB_RF_KPRTL_0 0xffffffff
+#define MASK_AON_SEC_APB_RF_KPRTL_1 0xffffffff
+#define MASK_AON_SEC_APB_RF_KPRTL_2 0xffffffff
+#define MASK_AON_SEC_APB_RF_KPRTL_3 0xffffffff
+#define MASK_AON_SEC_APB_RF_SEC_32K_DET_EB 0x800
+#define MASK_AON_SEC_APB_RF_SEC_EIC_RTCDV5_EB 0x400
+#define MASK_AON_SEC_APB_RF_SEC_EIC_RTC_EB 0x200
+#define MASK_AON_SEC_APB_RF_SEC_EIC_EB 0x100
+#define MASK_AON_SEC_APB_RF_SEC_RTC_CLK_GATE_EB 0x80
+#define MASK_AON_SEC_APB_RF_SEC_GPIO_EB 0x40
+#define MASK_AON_SEC_APB_RF_SEC_WDG_EB 0x20
+#define MASK_AON_SEC_APB_RF_SEC_WDG_RTC_EB 0x10
+#define MASK_AON_SEC_APB_RF_SEC_RTC_EB 0x8
+#define MASK_AON_SEC_APB_RF_SEC_TMR0_EB 0x4
+#define MASK_AON_SEC_APB_RF_SEC_TMR0_RTC_EB 0x2
+#define MASK_AON_SEC_APB_RF_SEC_TZPC_EB 0x1
+#define MASK_AON_SEC_APB_RF_SEC_32K_DET_SOFT_RST 0x40
+#define MASK_AON_SEC_APB_RF_SEC_EIC_SOFT_RST 0x20
+#define MASK_AON_SEC_APB_RF_SEC_GPIO_SOFT_RST 0x10
+#define MASK_AON_SEC_APB_RF_SEC_WDG_SOFT_RST 0x8
+#define MASK_AON_SEC_APB_RF_SEC_RTC_SOFT_RST 0x4
+#define MASK_AON_SEC_APB_RF_SEC_TMR0_SOFT_RST 0x2
+#define MASK_AON_SEC_APB_RF_SEC_TZPC_SOFT_RST 0x1
+#define MASK_AON_SEC_APB_RF_FUNC_DMA_EN 0x1
+#define MASK_AON_SEC_APB_RF_ETC_SEC_EB 0x4
+#define MASK_AON_SEC_APB_RF_I2C_SEC_EB 0x2
+#define MASK_AON_SEC_APB_RF_EFUSE_SEC_EB 0x1
+#define MASK_AON_SEC_APB_RF_SEC_EFUSE_BOUNDRY 0xff
+#define MASK_AON_SEC_APB_RF_APCPU_CSSYS_EB 0x1
+#define MASK_AON_SEC_APB_RF_APCPU_CSSYS_APB_SOFT_RST 0x4000
+#define MASK_AON_SEC_APB_RF_APCPU_CSSYS_SOFT_RST 0x2000
+#define MASK_AON_SEC_APB_RF_APCPU_SCU_SOFT_RST 0x1000
+#define MASK_AON_SEC_APB_RF_APCPU_DEBUG_APB_SOFT_RST 0x800
+#define MASK_AON_SEC_APB_RF_APCPU_PERIPH_SOFT_RST 0x400
+#define MASK_AON_SEC_APB_RF_APCPU_GIC_SOFT_RST 0x200
+#define MASK_AON_SEC_APB_RF_APCPU_ATB_SOFT_RST 0x100
+#define MASK_AON_SEC_APB_RF_APCPU_CORE_SOFT_RST 0xff
+#define MASK_AON_SEC_APB_RF_CGM_CORE3_DIV 0x70000000
+#define MASK_AON_SEC_APB_RF_CGM_CORE3_SEL 0x7000000
+#define MASK_AON_SEC_APB_RF_CGM_CORE2_DIV 0x700000
+#define MASK_AON_SEC_APB_RF_CGM_CORE2_SEL 0x70000
+#define MASK_AON_SEC_APB_RF_CGM_CORE1_DIV 0x7000
+#define MASK_AON_SEC_APB_RF_CGM_CORE1_SEL 0x700
+#define MASK_AON_SEC_APB_RF_CGM_CORE0_DIV 0x70
+#define MASK_AON_SEC_APB_RF_CGM_CORE0_SEL 0x7
+#define MASK_AON_SEC_APB_RF_CGM_CORE7_DIV 0x70000000
+#define MASK_AON_SEC_APB_RF_CGM_CORE7_SEL 0x7000000
+#define MASK_AON_SEC_APB_RF_CGM_CORE6_DIV 0x700000
+#define MASK_AON_SEC_APB_RF_CGM_CORE6_SEL 0x70000
+#define MASK_AON_SEC_APB_RF_CGM_CORE5_DIV 0x7000
+#define MASK_AON_SEC_APB_RF_CGM_CORE5_SEL 0x700
+#define MASK_AON_SEC_APB_RF_CGM_CORE4_DIV 0x70
+#define MASK_AON_SEC_APB_RF_CGM_CORE4_SEL 0x7
+#define MASK_AON_SEC_APB_RF_CGM_AXI_ACP_DIV 0x70000000
+#define MASK_AON_SEC_APB_RF_CGM_AXI_PERIPH_DIV 0x700000
+#define MASK_AON_SEC_APB_RF_CGM_ACE_DIV 0x7000
+#define MASK_AON_SEC_APB_RF_CGM_SCU_DIV 0x70
+#define MASK_AON_SEC_APB_RF_CGM_SCU_SEL 0x7
+#define MASK_AON_SEC_APB_RF_CGM_PERIPH_DIV 0x70000000
+#define MASK_AON_SEC_APB_RF_CGM_PERIPH_SEL 0x3000000
+#define MASK_AON_SEC_APB_RF_CGM_GIC_DIV 0x700000
+#define MASK_AON_SEC_APB_RF_CGM_GIC_SEL 0x30000
+#define MASK_AON_SEC_APB_RF_CGM_DEBUG_APB_DIV 0x3000
+#define MASK_AON_SEC_APB_RF_CGM_ATB_DIV 0x70
+#define MASK_AON_SEC_APB_RF_CGM_ATB_SEL 0x3
+#define MASK_AON_SEC_APB_RF_RVBARADDR0 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR1 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR2 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR3 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR4 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR5 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR6 0xffffffff
+#define MASK_AON_SEC_APB_RF_RVBARADDR7 0xffffffff
+#define MASK_AON_SEC_APB_RF_APCPU_PWAKEUPDBG_FORCE_ON 0x10
+#define MASK_AON_SEC_APB_RF_APCPU_GICP_ALLOW_NS 0x8
+#define MASK_AON_SEC_APB_RF_APCPU_GICT_ALLOW_NS 0x4
+#define MASK_AON_SEC_APB_RF_APCPU_GICCDISABLE 0x2
+#define MASK_AON_SEC_APB_RF_APCPU_CRYPTODISABLE 0x1
+#define MASK_AON_SEC_APB_RF_AON_SEC_APB_RSV_0 0xffffffff
+#define MASK_AON_SEC_APB_RF_AON_SEC_APB_RSV_1 0xffffffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_LOCK_DONE 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_REF_SEL 0x30000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_N 0xffe0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_ICP 0x1c
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_OD_TWPLL_CLKOUT_EN 0x80000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV7_EN 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV5_EN 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV3_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV2_EN 0x8000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_DIV1_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_IBIAS 0xc000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_LPF 0x3800
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_RESERVED 0x7ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_LOCK_DONE 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_REF_SEL 0x30000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_N 0xffe0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_ICP 0x1c
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_OD_LPLL_CLKOUT_EN 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_DIV5_EN 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_DIV3_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_DIV2_EN 0x8000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_DIV1_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_IBIAS 0xc000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_LPF 0x3800
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_RESERVED 0x7ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_LOCK_DONE 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_REF_SEL 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_N 0xffe0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_ICP 0x1c
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_OD_ISPPLL_CLKOUT_EN 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_DIV3_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_DIV2_EN 0x8000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_DIV1_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_IBIAS 0xc000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_LPF 0x3800
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_RESERVED 0x7ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_LOCK_DONE 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_REF_SEL 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_N 0xffe0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_ICP 0x1c
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_OD_GPLL_CLKOUT_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_IBIAS 0xc000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_LPF 0x3800
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_RESERVED 0x7ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_LOCK_DONE 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_REF_SEL 0x30000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_N 0xffe0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_ICP 0x1c
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_OD_CPLL_CLKOUT_EN 0x20000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_DIV1_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_DIV2_EN 0x8000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_DIV13_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_IBIAS 0xc000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_LPF 0x3800
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_RESERVED 0x7ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TEST_CLK_EN 0x40000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TEST_CLK_DIV 0x30000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ANALOG_TESTMUX 0xffff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ANALOG_PLL_RESERVED 0x3fffffff
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_DIV1_EN 0x2000000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_REF_SEL 0x1000000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV5_EN 0x800000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV3_EN 0x400000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV2_EN 0x200000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV1_EN 0x100000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_RST 0x80000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_TWPLL_PD 0x40000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_REF_SEL 0x20000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV5_EN 0x10000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV3_EN 0x8000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV2_EN 0x4000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV1_EN 0x2000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_RST 0x1000
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_LPLL_PD 0x800
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_DIV2_EN 0x400
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_RST 0x200
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_PD 0x100
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_GPLL_CLKOUT_EN 0x80
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_GPLL_RST 0x40
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_GPLL_PD 0x20
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_CPLL_DIV2_EN 0x10
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_CPLL_DIV13_EN 0x8
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_CPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_CPLL_RST 0x2
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_PLL_TOP_CPLL_PD 0x1
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_RSTN 0x8000000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_RUN 0x4000000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_PD 0x2000000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_VALID 0x1000000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_BG_RBIAS_MODE 0x800000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_TEST_SEL 0x600000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_BP_MODE 0x100000
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_DATA 0xffc00
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_BP_DATA 0x3ff
+#define MASK_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM_RESERVED 0xffff
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_THM1_0_THM_RSTN 0x8
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_THM1_0_THM_RUN 0x4
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_THM1_0_THM_PD 0x2
+#define MASK_ANLG_PHY_GC_RF_DBG_SEL_ANALOG_THM1_0_THM_RESERVED 0x1
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_DATABUS16_8 0x10000000
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_DMPULLDOWN 0x8
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_DPPULLDOWN 0x10
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_PS_PD_L 0x8
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_PS_PD_S 0x10
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_RESERVED 0xffff
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_TFREGRES 0x1f80000
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_TUNEHSAMP 0x6000000
+#define MASK_ANLG_PHY_G2_ANALOG_USB20_USB20_VBUSVLDEXT 0x10000
+#define MASK_ANLG_PHY_G2_DBG_SEL_ANALOG_USB20_USB20_DMPULLDOWN 0x2
+#define MASK_ANLG_PHY_G2_DBG_SEL_ANALOG_USB20_USB20_DPPULLDOWN 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_LOCK_DONE 0x20000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CLKIN_SEL 0x10000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N 0xffe0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP 0x1c
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_SDM_EN 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_DIV_S 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_NINT 0x3f800000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_KINT 0x7fffff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_DIV32_EN 0x4000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV 0x2000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CCS_CTRL 0xff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_MOD_EN 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_RST 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_PD 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_R2_SEL 0xc00000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_R3_SEL 0x300000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_C1_SEL 0xc0000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_C2_SEL 0x30000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_KVCO_SEL 0xc000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCO_TEST_INTSEL 0x3800
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCO_TEST_INT 0x400
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CP_EN 0x200
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_LDO_TRIM 0x1e0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCO_TEST_EN 0x10
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_FBDIV_EN 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CP_OFFSET 0x6
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCOBUF_EN 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_RESERVED 0xffff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_BIST_EN 0x10000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_26MBUFFER_PD 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_MODE 0x60000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_INI 0x1f000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_TRIG 0x800
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_FREQ_DIFF_EN 0x400
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_WAITCNT 0x300
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_POLARITY 0x80
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_DONE 0x40
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_OUT 0x3e
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_CPPD 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCTRLH_SEL 0xe0000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCTRLL_SEL 0x1c000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_RG_CLOSELOOP_EN 0x2000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCO_BANK_SEL 0x1f00
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_VCTRL_HIGH 0x80
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CALI_VCTRL_LOW 0x40
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_VCO_BANK_SEL_OFFSET 0x20
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ADJ_MANUAL_PD 0x10
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ISO_SW_EN 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_TEST_CLK_EN 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_TEST_SEL 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_26MBUFFER_CLKOUT_EN 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX0 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX0 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX0 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX1 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX1 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX1 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX2 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX2 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX2 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX3 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX3 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX3 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX4 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX4 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX4 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX5 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX5 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX5 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX6 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX6 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX6 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_N_INDEX7 0x7ff0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_POSTDIV_INDEX7 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_ICP_INDEX7 0x7
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_N 0x80
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_ICP 0x40
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_DIV32_EN 0x20
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_POSTDIV 0x10
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_CLKOUT_EN 0x8
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_RST 0x4
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_PD 0x2
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_MPLL1_MPLL1_26MBUFFER_PD 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_RSTN 0x8000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_RUN 0x4000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_PD 0x2000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_VALID 0x1000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_BG_RBIAS_MODE 0x800000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_TEST_SEL 0x600000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_BP_MODE 0x100000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_DATA 0xffc00
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_BP_DATA 0x3ff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_THM2_THM_RESERVED 0xffff
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_THM2_THM_RSTN 0x8
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_THM2_THM_RUN 0x4
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_THM2_THM_PD 0x2
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_THM2_THM_RESERVED 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TESTCLK 0x1000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TESTDATAIN 0xff0000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TESTADDR 0xf000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TESTDATAOUTSEL 0x800
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TESTDATAOUT 0x780
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BIST_MODE 0x7c
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_T2RCOMP 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_LPBK_END 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_DATABUS16_8 0x10000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_SUSPENDM 0x8000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PORN 0x4000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_RESET 0x2000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_RXERROR 0x1000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_DRV_DP 0x800000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_DRV_DM 0x400000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_FS 0x200000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_IN_DP 0x100000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_IN_DM 0x80000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_OUT_DP 0x40000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BYPASS_OUT_DM 0x20000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_VBUSVLDEXT 0x10000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_RESERVED 0xffff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PS_PD_S 0x10
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PS_PD_L 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_REXTENABLE 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_DMPULLUP 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_SAMPLER_SEL 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_DPPULLDOWN 0x10
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_DMPULLDOWN 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TXBITSTUFFENABLE 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TXBITSTUFFENABLEH 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_SLEEPM 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNEHSAMP 0x6000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TFREGRES 0x1f80000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TFHSRES 0x7c000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNERISE 0x3000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNEOTG 0xe00
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNEDSC 0x180
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNESQ 0x78
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNEEQ 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TUNEPLLS 0x3c00
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PLL_PFD_DEADZONE 0x300
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PLL_PFD_DELAY 0xc0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PLL_CP_IOFFSET_EN 0x20
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PLL_CP_IOFFSET 0x1e
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PLL_REF_DOUBLER_EN 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BIST_MODE_EN 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_SUSPENDM 0x100
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_PORN 0x80
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_RESET 0x40
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_BYPASS_FS 0x20
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_BYPASS_IN_DM 0x10
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_SAMPLER_SEL 0x8
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_DPPULLDOWN 0x4
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_DMPULLDOWN 0x2
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_USB20_USB20_SLEEPM 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_TORG_EPLL_LOCK_DONE 0x200
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_N 0x1f8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_ICP 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_LPF 0x3800
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_RBIAS_MODE 0x400
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_FBDIV_EN 0x200
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_IGN26MSPUR_EN 0x100
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_TEST_SEL 0xc0
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_DIV32_CLKOUT_EN 0x20
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_POSTDIV 0x10
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_BG_PD 0x8
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_RST 0x2
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_PD 0x1
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CP_EN 0x80
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_LDO_TRIM 0x78
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CP_OFFSET 0x7
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_RESERVED 0xffff
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_BIST_EN 0x1000000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_BIST_CTRL 0xff0000
+#define MASK_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_TORG_EPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_EPLL_TOP_RG_EPLL_DIV32_CLKOUT_EN 0x10
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_EPLL_TOP_RG_EPLL_BG_PD 0x8
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_EPLL_TOP_RG_EPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_EPLL_TOP_RG_EPLL_RST 0x2
+#define MASK_ANLG_PHY_G2_RF_DBG_SEL_ANALOG_EPLL_TOP_RG_EPLL_PD 0x1
+#define MASK_AON_DBG_APB_RF_APCPU_AWSTASHLPIDENS 0x100000
+#define MASK_AON_DBG_APB_RF_APCPU_AWSTASHLPIDS 0xf0000
+#define MASK_AON_DBG_APB_RF_APCPU_CFGTE 0xff00
+#define MASK_AON_DBG_APB_RF_APCPU_AA64NAA32 0xff
+#define MASK_AON_DBG_APB_RF_APCPU_SPNIDEN 0x8
+#define MASK_AON_DBG_APB_RF_APCPU_SPIDEN 0x4
+#define MASK_AON_DBG_APB_RF_APCPU_NIDEN 0x2
+#define MASK_AON_DBG_APB_RF_APCPU_DBGEN 0x1
+#define MASK_AON_DBG_APB_RF_DAP_DEVICEEN 0x80000000
+#define MASK_AON_DBG_APB_RF_DAP_DBGEN 0x40000000
+#define MASK_AON_DBG_APB_RF_DAP_SPIDBGEN 0x20000000
+#define MASK_AON_DBG_APB_RF_CDMA2K_DBGEN 0x1000
+#define MASK_AON_DBG_APB_RF_VDSP_DBGEN 0x800
+#define MASK_AON_DBG_APB_RF_GPU_DBGEN 0x400
+#define MASK_AON_DBG_APB_RF_TG_JTAG_EN 0x200
+#define MASK_AON_DBG_APB_RF_LTE_JTAG_EN 0x100
+#define MASK_AON_DBG_APB_RF_AON_CM4_DBGEN 0x80
+#define MASK_AON_DBG_APB_RF_DJTAG_EN 0x40
+#define MASK_AON_DBG_APB_RF_AG_JTAG_EN 0x20
+#define MASK_AON_DBG_APB_RF_MJTAG_EN 0x10
+#define MASK_AON_DBG_APB_RF_CSSYS_NIDEN 0x8
+#define MASK_AON_DBG_APB_RF_CSSYS_SPNIDEN 0x4
+#define MASK_AON_DBG_APB_RF_CSSYS_SPIDEN 0x2
+#define MASK_AON_DBG_APB_RF_CSSYS_DBGEN 0x1
+#define MASK_AON_DBG_APB_RF_CR5_NIDEN 0x2
+#define MASK_AON_DBG_APB_RF_CR5_DBGEN 0x1
+#define MASK_AON_DBG_APB_RF_APCPU_SPNIDEN_NON_SEC 0x8
+#define MASK_AON_DBG_APB_RF_APCPU_SPIDEN_NON_SEC 0x4
+#define MASK_AON_DBG_APB_RF_APCPU_NIDEN_NON_SEC 0x2
+#define MASK_AON_DBG_APB_RF_APCPU_DBGEN_NON_SEC 0x1
+#define MASK_AON_DBG_APB_RF_DAP_DEVICEEN_NON_SEC 0x80000000
+#define MASK_AON_DBG_APB_RF_DAP_DBGEN_NON_SEC 0x40000000
+#define MASK_AON_DBG_APB_RF_DAP_SPIDBGEN_NON_SEC 0x20000000
+#define MASK_AON_DBG_APB_RF_CDMA2K_DBGEN_NON_SEC 0x1000
+#define MASK_AON_DBG_APB_RF_VDSP_DBGEN_NON_SEC 0x800
+#define MASK_AON_DBG_APB_RF_GPU_DBGEN_NON_SEC 0x400
+#define MASK_AON_DBG_APB_RF_TG_JTAG_EN_NON_SEC 0x200
+#define MASK_AON_DBG_APB_RF_LTE_JTAG_EN_NON_SEC 0x100
+#define MASK_AON_DBG_APB_RF_AON_CM4_DBGEN_NON_SEC 0x80
+#define MASK_AON_DBG_APB_RF_DJTAG_EN_NON_SEC 0x40
+#define MASK_AON_DBG_APB_RF_AG_JTAG_EN_NON_SEC 0x20
+#define MASK_AON_DBG_APB_RF_MJTAG_EN_NON_SEC 0x10
+#define MASK_AON_DBG_APB_RF_CSSYS_NIDEN_NON_SEC 0x8
+#define MASK_AON_DBG_APB_RF_CSSYS_SPNIDEN_NON_SEC 0x4
+#define MASK_AON_DBG_APB_RF_CSSYS_SPIDEN_NON_SEC 0x2
+#define MASK_AON_DBG_APB_RF_CSSYS_DBGEN_NON_SEC 0x1
+#define MASK_AON_DBG_APB_RF_CR5_NIDEN_NON_SEC 0x2
+#define MASK_AON_DBG_APB_RF_CR5_DBGEN_NON_SEC 0x1
+#define MASK_AON_DBG_APB_RF_EFUSE_DEBUG_BOND_OFF 0x80000000
+#define MASK_AON_DBG_APB_RF_EFUSE_SECURE_DEBUG 0x40000000
+#define MASK_SCC_APB_RF_VOLT_TUNE_VAL_MAX 0x3fe00
+#define MASK_SCC_APB_RF_VOLT_TUNE_VAL_MIN 0x1ff
+#define MASK_SCC_APB_RF_VOLT_TUNE_VAL 0x3fe00
+#define MASK_SCC_APB_RF_VOLT_OBS_VAL 0x1ff
+#define MASK_SCC_APB_RF_VOLT0_SELECT_OVERRIDE 0x80000000
+#define MASK_SCC_APB_RF_VOLT1_SELECT_OVERRIDE 0x40000000
+#define MASK_SCC_APB_RF_PAUSE_OCCUR_ERR_EN 0x100
+#define MASK_SCC_APB_RF_VOLT_TUNE_FORBID_EN 0x10
+#define MASK_SCC_APB_RF_VOLT_OBS_FORBID_EN 0x1
+#define MASK_SCC_APB_RF_VOLT_TUNE_DOWN_STEP 0x3ff0000
+#define MASK_SCC_APB_RF_VOLT_TUNE_UP_STEP 0x3ff
+#define MASK_SCC_APB_RF_RND_INTVAL_WAIT_NUM 0xffff0000
+#define MASK_SCC_APB_RF_VOLT_STB_WAIT_NUM 0xffff
+#define MASK_SCC_APB_RF_SCC_TUNE_DONE_INT_MASK_STATUS 0x2000
+#define MASK_SCC_APB_RF_SCC_TUNE_ERR_INT_MASK_STATUS 0x1000
+#define MASK_SCC_APB_RF_SCC_TUNE_DONE_INT_RAW_STATUS 0x200
+#define MASK_SCC_APB_RF_SCC_TUNE_ERR_INT_RAW_STATUS 0x100
+#define MASK_SCC_APB_RF_SCC_TUNE_DONE_INT_CLR 0x20
+#define MASK_SCC_APB_RF_SCC_TUNE_ERR_INT_CLR 0x10
+#define MASK_SCC_APB_RF_SCC_TUNE_DONE_INT_EN 0x2
+#define MASK_SCC_APB_RF_SCC_TUNE_ERR_INT_EN 0x1
+#define MASK_SCC_APB_RF_SCC_TUNE_DWN_MARK 0xffff0000
+#define MASK_SCC_APB_RF_SCC_TUNE_UP_MARK 0xffff
+#define MASK_SCC_APB_RF_SCC_FSM_STS 0x1f
+#define MASK_SCC_APB_RF_SCC_IDLE_MODE 0x80000000
+#define MASK_SCC_APB_RF_SCC_TUNE_BYPASS 0x40000000
+#define MASK_SCC_APB_RF_SCC_INIT_HALT_BYPASS 0x20000000
+#define MASK_SCC_APB_RF_SCC_AM_CLK_DIVIDER 0x18000000
+#define MASK_SCC_APB_RF_SCC_AM_ENABLE 0x4000000
+#define MASK_SCC_APB_RF_SCC_AM_OBS_EN 0x2000000
+#define MASK_SCC_APB_RF_SCC_RPT_READ_CTRL 0x1000
+#define MASK_SCC_APB_RF_SCC_ALL_ROSC_CHAIN 0x4
+#define MASK_SCC_APB_RF_SCC_ALL_ROSC_SEQ 0x2
+#define MASK_SCC_APB_RF_SCC_ROSC_REPEAT_MODE 0x1
+#define MASK_SCC_APB_RF_SCC_ROSC_DURATION 0xfffff000
+#define MASK_SCC_APB_RF_SCC_ROSC_SEL_Z 0xf00
+#define MASK_SCC_APB_RF_SCC_ROSC_SEL_Y 0xf0
+#define MASK_SCC_APB_RF_SCC_ROSC_SEL_X 0xf
+#define MASK_SCC_APB_RF_SCC_RPT_READ_NXT 0x80000000
+#define MASK_SCC_APB_RF_SCC_ROSC_GR_ENABLE 0x2
+#define MASK_SCC_APB_RF_SCC_ROSC_RUN 0x1
+#define MASK_SCC_APB_RF_SCC_INIT_PAT_FAIL 0x80000000
+#define MASK_SCC_APB_RF_SCC_ROSC_RPT_VALID 0x40000000
+#define MASK_SCC_APB_RF_SCC_ROSC_SETTING 0x1f00000
+#define MASK_SCC_APB_RF_SCC_ROSC_CNT 0xfffff
+#define MASK_SCC_APB_RF_SCC_ROSC_SW_RST 0xf
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_LOCK_DONE 0x40000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_REF_SEL 0x30000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_N 0xffe0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_ICP 0x1c
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_SDM_EN 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_DIV_S 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_NINT 0x3f800000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_KINT 0x7fffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_SINEO_RPLL_CLKOUT_EN 0x2000000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_26M_SEL 0x1000000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_VSET 0xe00000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_26M_DIV 0x1f8000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_DIV_EN 0x4000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_POSTDIV 0x2000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_SSC_CTRL 0xff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_MOD_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_RST 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CP_EN 0x100
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_LDO_TRIM 0xf0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_VCO_TEST_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_FBDIV_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CP_OFFSET 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_IBIAS 0x18
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_LPF 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_RESERVED 0x1fffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_BIST_EN 0x10000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_AAPC_PD 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_AAPC_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_REC_26MHZ_0_BUF_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_CLK26MHZ_AUD_EN 0x100000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_PROBE_SEL 0xfc000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_SINDRV_ENA 0x2000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_SINDRV_ENA_SQUARE 0x1000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_REC_26MHZ_SR_TRIM 0xf00
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_REC_26MHZ_0_CUR_SEL 0xc0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_CLK26M_RESERVED 0x3c
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_SINE_DRV_SEL 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_BB_CON_BG 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANALOG_TESTMUX 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_G0 0x3000000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_G1 0xc00000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_G2 0x300000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_AAPC_LOW_V_CON 0x80000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_AAPC_D 0x7ffe0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_AAPC_BPRES 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_APCOUT_SEL 0xc
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_S_AAPC_RESERVED 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_AAPC_D 0xfffc0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_AAPC_LOW_V_CON 0x20
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_AAPC_BPRES 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_APCOUT_SEL 0xc
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_M_AAPC_RESERVED 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANA_BB_RESERVED 0x3fffc
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_TO_LVDS_SEL 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_RSTB 0x400000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_EN 0x200000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_RESERVED 0x1fe000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_LDO_EN 0x1000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_LDO_BYPASS 0x800
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_LDO_VOLTAGE_SEL 0x600
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_LDO_BIAS_SEL 0x180
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_RC_C 0x7f
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_TEST_CLK_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_TEST_CLK_OD 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_TEST_CLK_DIV 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_MAX_RANGE 0x1fff8000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_MIN_RANGE 0x7ffe
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_RSTN 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_STEP_SEL 0x3c0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_RAMP_GEN_SEL 0x20
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_PD_SEL_RFTI_OR_PMU 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_RST_SEL_RFTI_OR_PMU 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_DBG_SEL_RTC100M_LDO_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_DBG_SEL_RTC100M_LDO_BYPASS 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RCO100M_POWER_MODE_SEL 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_BB_TOP_BB_BG_RBIAS_MODE 0x1
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_REF_SEL 0x80000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_N 0x40000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_SDM_EN 0x20000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_DIV_S 0x10000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_NINT 0x8000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_KINT 0x4000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_26M_DIV 0x2000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_DIV_EN 0x1000000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_MOD_EN 0x800000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_CLKOUT_EN 0x400000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_RST 0x200000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_PD 0x100000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_IBIAS 0x80000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_LPF 0x40000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_RESERVED 0x20000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_BIST_CTRL 0x10000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RPLL_BIST_EN 0x8000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_AAPC_PD 0x4000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_AAPC_PD 0x2000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_REC_26MHZ_0_BUF_PD 0x1000
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_CLK26MHZ_AUD_EN 0x800
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_SINDRV_ENA 0x400
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_SINDRV_ENA_SQUARE 0x200
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_AAPC_G0 0x100
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_AAPC_G1 0x80
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_AAPC_G2 0x40
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_AAPC_LOW_V_CON 0x20
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_AAPC_D 0x10
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_AAPC_BPRES 0x8
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_APCOUT_SEL 0x4
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_S_AAPC_RESERVED 0x2
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_AAPC_D 0x1
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_AAPC_LOW_V_CON 0x40
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_AAPC_BPRES 0x20
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_APCOUT_SEL 0x10
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_M_AAPC_RESERVED 0x8
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RTC100M_RSTB 0x4
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RTC100M_EN 0x2
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_BB_TOP_RTC100M_RC_C 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_LOCK_DONE 0x20000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CLKIN_SEL 0x10000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N 0xffe0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP 0x1c
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_SDM_EN 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_DIV_S 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_NINT 0x3f800000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_KINT 0x7fffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_DIV32_EN 0x4000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV 0x2000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CCS_CTRL 0xff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_MOD_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_RST 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_R2_SEL 0xc00000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_R3_SEL 0x300000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_C1_SEL 0xc0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_C2_SEL 0x30000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_KVCO_SEL 0xc000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCO_TEST_INTSEL 0x3800
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCO_TEST_INT 0x400
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CP_EN 0x200
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_LDO_TRIM 0x1e0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCO_TEST_EN 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_FBDIV_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CP_OFFSET 0x6
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCOBUF_EN 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_RESERVED 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_BIST_CTRL 0x1fe0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_BIST_EN 0x10000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_26MBUFFER_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_MODE 0x60000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_INI 0x1f000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_TRIG 0x800
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_FREQ_DIFF_EN 0x400
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_WAITCNT 0x300
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_POLARITY 0x80
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_DONE 0x40
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_OUT 0x3e
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_CPPD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCTRLH_SEL 0xe0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCTRLL_SEL 0x1c000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_RG_CLOSELOOP_EN 0x2000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCO_BANK_SEL 0x1f00
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_VCTRL_HIGH 0x80
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CALI_VCTRL_LOW 0x40
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_VCO_BANK_SEL_OFFSET 0x20
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ADJ_MANUAL_PD 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ISO_SW_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_TEST_CLK_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_TEST_SEL 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_26MBUFFER_CLKOUT_EN 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX0 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX0 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX0 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX1 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX1 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX1 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX2 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX2 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX2 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX3 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX3 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX3 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX4 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX4 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX4 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX5 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX5 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX5 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX6 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX6 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX6 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_N_INDEX7 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_POSTDIV_INDEX7 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_ICP_INDEX7 0x7
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_N 0x80
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_ICP 0x40
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_DIV32_EN 0x20
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_POSTDIV 0x10
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_CLKOUT_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_RST 0x4
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_PD 0x2
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL0_MPLL0_26MBUFFER_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_LOCK_DONE 0x10000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N 0xffe0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP 0x1c
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_SDM_EN 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_DIV_S 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_NINT 0x3f800000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_KINT 0x7fffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_DIV32_EN 0x4000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV 0x2000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_FREQ_DOUBLE_EN 0x1000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CCS_CTRL 0xff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_MOD_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_RST 0x2
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_PD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_R2_SEL 0xc00000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_R3_SEL 0x300000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_C1_SEL 0xc0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_C2_SEL 0x30000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_KVCO_SEL 0xc000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCO_TEST_INTSEL 0x3800
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCO_TEST_INT 0x400
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CP_EN 0x200
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_LDO_TRIM 0x1e0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCO_TEST_EN 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_FBDIV_EN 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CP_OFFSET 0x6
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCOBUF_EN 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_RESERVED 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_BIST_EN 0x1000000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_BIST_CTRL 0xff0000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_MODE 0x60000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_INI 0x1f000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_TRIG 0x800
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_FREQ_DIFF_EN 0x400
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_WAITCNT 0x300
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_POLARITY 0x80
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_DONE 0x40
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_OUT 0x3e
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_CPPD 0x1
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL_CLK_JITTER_MON_EN 0x4000000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL_CLK_JITTER_MON_SEL 0x3c00000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCTRLH_SEL 0x380000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCTRLL_SEL 0x70000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_RG_CLOSELOOP_EN 0x8000
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCO_BANK_SEL 0x7c00
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_VCTRL_HIGH 0x200
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CALI_VCTRL_LOW 0x100
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_VCO_BANK_SEL_OFFSET 0x80
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ADJ_MANUAL_PD 0x40
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ISO_SW_EN 0x20
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_TEST_CLK_EN 0x10
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_TEST_SEL 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL_RESERVED_BIT2 0x4
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL_RESERVED_BIT1_0 0x3
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX0 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX0 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX0 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX1 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX1 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX1 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX2 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX2 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX2 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX3 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX3 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX3 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX4 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX4 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX4 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX5 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX5 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX5 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX6 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX6 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX6 0x7
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_N_INDEX7 0x7ff0
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_POSTDIV_INDEX7 0x8
+#define MASK_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_ICP_INDEX7 0x7
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_N 0x40
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_ICP 0x20
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_DIV32_EN 0x10
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_POSTDIV 0x8
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_RST 0x2
+#define MASK_ANLG_PHY_G3_RF_DBG_SEL_ANALOG_MPLL2_MPLL2_PD 0x1
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_GPLL_SOFT_CNT_DONE 0x200000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_ISPPLL_936M_SOFT_CNT_DONE 0x100000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_ISPPLL_468M_SOFT_CNT_DONE 0x80000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_TWPLL_1536M_SOFT_CNT_DONE 0x40000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_TWPLL_768M_SOFT_CNT_DONE 0x20000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_TWPLL_512M_SOFT_CNT_DONE 0x10000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_TWPLL_307M_SOFT_CNT_DONE 0x8000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LTEPLL_1228M_SOFT_CNT_DONE 0x4000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LTEPLL_614M_SOFT_CNT_DONE 0x2000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LTEPLL_409M_SOFT_CNT_DONE 0x1000
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_LTEPLL_245M_SOFT_CNT_DONE 0x800
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_XBUF0_SOFT_CNT_DONE 0x400
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_XBUF1_SOFT_CNT_DONE 0x200
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_RPLL_390M_SOFT_CNT_DONE 0x100
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_RPLL_26M_SOFT_CNT_DONE 0x80
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_RCO_SOFT_CNT_DONE 0x40
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_MPLL0_SOFT_CNT_DONE 0x20
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_MPLL1_SOFT_CNT_DONE 0x10
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_MPLL2_SOFT_CNT_DONE 0x8
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_DPLL0_SOFT_CNT_DONE 0x4
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_CPLL_511M_SOFT_CNT_DONE 0x2
+#define MASK_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG_CPLL_78M_SOFT_CNT_DONE 0x1
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_GPLL_WAIT_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_ISPPLL_936M_WAIT_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_ISPPLL_468M_WAIT_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_TWPLL_1536M_WAIT_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_TWPLL_768M_WAIT_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_TWPLL_512M_WAIT_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_TWPLL_307M_WAIT_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LTEPLL_1228M_WAIT_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LTEPLL_614M_WAIT_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LTEPLL_409M_WAIT_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_LTEPLL_245M_WAIT_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_XBUF0_WAIT_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_XBUF1_WAIT_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_RPLL_390M_WAIT_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_RPLL_26M_WAIT_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_RCO_WAIT_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_MPLL0_WAIT_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_MPLL1_WAIT_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_MPLL2_WAIT_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_DPLL0_WAIT_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_CPLL_511M_WAIT_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG_CPLL_78M_WAIT_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_GPLL_WAIT_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_ISPPLL_936M_WAIT_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_ISPPLL_468M_WAIT_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_TWPLL_1536M_WAIT_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_TWPLL_768M_WAIT_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_TWPLL_512M_WAIT_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_TWPLL_307M_WAIT_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LTEPLL_1228M_WAIT_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LTEPLL_614M_WAIT_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LTEPLL_409M_WAIT_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_LTEPLL_245M_WAIT_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_XBUF0_WAIT_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_XBUF1_WAIT_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_RPLL_390M_WAIT_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_RPLL_26M_WAIT_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_RCO_WAIT_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_MPLL0_WAIT_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_MPLL1_WAIT_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_MPLL2_WAIT_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_DPLL0_WAIT_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_CPLL_511M_WAIT_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_CPLL_78M_WAIT_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_GPLL_DIV_40M_AUTO_GATE_SEL 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_ISPPLL_DIV_468M_29M2_AUTO_GATE_SEL 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_ISPPLL_DIV_468M_78M_AUTO_GATE_SEL 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_245M_122M9_AUTO_GATE_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_245M_61M4_AUTO_GATE_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_245M_30M7_AUTO_GATE_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_245M_49M2_AUTO_GATE_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_245M_24M6_AUTO_GATE_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_409M_204M8_AUTO_GATE_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_409M_102M4_AUTO_GATE_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_614M_307M2_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_LTEPLL_DIV_614M_153M6_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_4M_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_2M_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RCO_DIV_25M_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RPLL_DIV_390M_130M_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RPLL_DIV_390M_43M3_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RPLL_DIV_390M_78M_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RPLL_DIV_390M_55M7_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RTC_DIV_3K_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_RTC_DIV_1K_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_153M6_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_76M8_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_38M4_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_19M2_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_12M3_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_102M4_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_307M_51M2_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_512M_256M_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_512M_128M_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_512M_64M_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG_TWPLL_DIV_512M_170M7_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_512M_85M3_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_768M_384M_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_768M_192M_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_768M_96M_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_768M_48M_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_TWPLL_DIV_768M_12M_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_2M_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_1M_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_250K_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_13M_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_6M5_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_8M7_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG_XBUF0_DIV_4M3_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_GPLL_DIV_40M_FORCE_EN 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_ISPPLL_DIV_468M_29M2_FORCE_EN 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_ISPPLL_DIV_468M_78M_FORCE_EN 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_245M_122M9_FORCE_EN 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_245M_61M4_FORCE_EN 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_245M_30M7_FORCE_EN 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_245M_49M2_FORCE_EN 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_245M_24M6_FORCE_EN 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_409M_204M8_FORCE_EN 0x800000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_409M_102M4_FORCE_EN 0x400000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_614M_307M2_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_LTEPLL_DIV_614M_153M6_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_4M_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_2M_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RCO_DIV_25M_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RPLL_DIV_390M_130M_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RPLL_DIV_390M_43M3_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RPLL_DIV_390M_78M_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RPLL_DIV_390M_55M7_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RTC_DIV_3K_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_RTC_DIV_1K_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_153M6_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_76M8_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_38M4_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_19M2_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_12M3_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_102M4_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_307M_51M2_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_512M_256M_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_512M_128M_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_512M_64M_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG_TWPLL_DIV_512M_170M7_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_512M_85M3_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_768M_384M_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_768M_192M_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_768M_96M_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_768M_48M_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_TWPLL_DIV_768M_12M_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_2M_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_1M_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_250K_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_13M_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_6M5_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_8M7_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG_XBUF0_DIV_4M3_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_26M_APCPU_AUTO_GATE_SEL 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_LTEPLL_1228M8_APCPU_AUTO_GATE_SEL 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_1536M_APCPU_AUTO_GATE_SEL 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_768M_APCPU_AUTO_GATE_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_512M_APCPU_AUTO_GATE_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_384M_APCPU_AUTO_GATE_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_153M6_APCPU_AUTO_GATE_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_26M_AP_AUTO_GATE_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_XTL_1M_AP_AUTO_GATE_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_ISPPLL_936M_AP_AUTO_GATE_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_768M_AP_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_512M_AP_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_384M_AP_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_307M2_AP_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_256M_AP_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_192M_AP_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_153M6_AP_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_128M_AP_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_96M_AP_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_76M8_AP_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_64M_AP_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_51M2_AP_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_48M_AP_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_LTEPLL_614M4_AP_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_LTEPLL_409M6_AP_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_LTEPLL_204M8_AP_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_RPLL_390M_AP_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_384M_DISP_AP_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_307M2_DISP_AP_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_256M_DISP_AP_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_192M_DISP_AP_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG_CGM_TWPLL_153M6_DISP_AP_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_128M_DISP_AP_AUTO_GATE_SEL 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_96M_DISP_AP_AUTO_GATE_SEL 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_XTL_26M_GPU_AUTO_GATE_SEL 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_GPLL_800M_GPU_AUTO_GATE_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_LTEPLL_614M4_GPU_AUTO_GATE_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_768M_GPU_AUTO_GATE_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_512M_GPU_AUTO_GATE_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_384M_GPU_AUTO_GATE_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_XTL_26M_PUB_AUTO_GATE_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_128M_PUB_AUTO_GATE_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_XTL_26M_MM_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_512M_MM_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_ISPPLL_468M_MM_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_384M_MM_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_307M2_MM_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_256M_MM_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_192M_MM_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_153M6_MM_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_128M_MM_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_96M_MM_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_76M8_MM_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_48M_MM_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_512M_WTLCP_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_384M_WTLCP_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_307M2_WTLCP_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_256M_WTLCP_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_192M_WTLCP_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_153M6_WTLCP_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_128M_WTLCP_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_102M4_WTLCP_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_96M_WTLCP_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG_CGM_TWPLL_85M3_WTLCP_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_76M8_WTLCP_AUTO_GATE_SEL 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_64M_WTLCP_AUTO_GATE_SEL 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_51M2_WTLCP_AUTO_GATE_SEL 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_48M_WTLCP_AUTO_GATE_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_614M4_WTLCP_AUTO_GATE_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_307M2_WTLCP_AUTO_GATE_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_245M76_WTLCP_AUTO_GATE_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_204M8_WTLCP_AUTO_GATE_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_153M6_WTLCP_AUTO_GATE_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_122M88_WTLCP_AUTO_GATE_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_102M4_WTLCP_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_LTEPLL_61M44_WTLCP_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_RPLL_26M_WTLCP_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_CPLL_511M18_CDMA_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_CPLL_78M64_CDMA_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_RPLL_26M_CDMA_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_512M_PUBCP_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_384M_PUBCP_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_307M2_PUBCP_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_256M_PUBCP_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_192M_PUBCP_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_153M6_PUBCP_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_128M_PUBCP_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_96M_PUBCP_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_64M_PUBCP_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_51M2_PUBCP_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_48M_PUBCP_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_XTL_26M_PUBCP_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_512M_AUDCP_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_384M_AUDCP_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_307M2_AUDCP_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG_CGM_TWPLL_256M_AUDCP_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_192M_AUDCP_AUTO_GATE_SEL 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_153M6_AUDCP_AUTO_GATE_SEL 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_128M_AUDCP_AUTO_GATE_SEL 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_96M_AUDCP_AUTO_GATE_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_64M_AUDCP_AUTO_GATE_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_51M2_AUDCP_AUTO_GATE_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_48M_AUDCP_AUTO_GATE_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_38M4_AUDCP_AUTO_GATE_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_LTEPLL_614M4_AUDCP_AUTO_GATE_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_LTEPLL_24M576_AUDCP_AUTO_GATE_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_AUD_26M_AUDCP_AUTO_GATE_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RPLL_26M_AON_AUTO_GATE_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RPLL_390M_AON_AUTO_GATE_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_26M_AON_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_13M_AON_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_6M5_AON_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_4M_AON_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_2M_AON_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_1M_AON_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_XTL_250K_AON_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_AUD_26M_AON_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_100M_AON_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_25M_AON_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_4M_AON_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_RCO_2M_AON_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_GPLL_40M_AON_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_ISPPLL_29M25_AON_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_ISPPLL_78M_AON_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_768M_AON_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_512M_AON_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_384M_AON_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG_CGM_TWPLL_307M2_AON_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_256M_AON_AUTO_GATE_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_192M_AON_AUTO_GATE_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_153M6_AON_AUTO_GATE_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_128M_AON_AUTO_GATE_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_96M_AON_AUTO_GATE_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_76M8_AON_AUTO_GATE_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_64M_AON_AUTO_GATE_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_51M2_AON_AUTO_GATE_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_48M_AON_AUTO_GATE_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_38M4_AON_AUTO_GATE_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_19M2_AON_AUTO_GATE_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_12M288_AON_AUTO_GATE_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_TWPLL_12M_AON_AUTO_GATE_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_LTEPLL_409M6_AON_AUTO_GATE_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_LTEPLL_30M72_AON_AUTO_GATE_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_MPLL0_56M25_AON_AUTO_GATE_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_MPLL1_62M5_AON_AUTO_GATE_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_MPLL2_46M88_AON_AUTO_GATE_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG_CGM_DPLL0_50M_AON_AUTO_GATE_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_26M_APCPU_FORCE_EN 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_LTEPLL_1228M8_APCPU_FORCE_EN 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_1536M_APCPU_FORCE_EN 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_768M_APCPU_FORCE_EN 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_512M_APCPU_FORCE_EN 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_384M_APCPU_FORCE_EN 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_153M6_APCPU_FORCE_EN 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_26M_AP_FORCE_EN 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_XTL_1M_AP_FORCE_EN 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_ISPPLL_936M_AP_FORCE_EN 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_768M_AP_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_512M_AP_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_384M_AP_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_307M2_AP_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_256M_AP_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_192M_AP_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_153M6_AP_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_128M_AP_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_96M_AP_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_76M8_AP_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_64M_AP_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_51M2_AP_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_48M_AP_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_LTEPLL_614M4_AP_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_LTEPLL_409M6_AP_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_LTEPLL_204M8_AP_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_RPLL_390M_AP_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_384M_DISP_AP_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_307M2_DISP_AP_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_256M_DISP_AP_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_192M_DISP_AP_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG_CGM_TWPLL_153M6_DISP_AP_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_128M_DISP_AP_FORCE_EN 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_96M_DISP_AP_FORCE_EN 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_XTL_26M_GPU_FORCE_EN 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_GPLL_800M_GPU_FORCE_EN 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_LTEPLL_614M4_GPU_FORCE_EN 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_768M_GPU_FORCE_EN 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_512M_GPU_FORCE_EN 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_384M_GPU_FORCE_EN 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_XTL_26M_PUB_FORCE_EN 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_128M_PUB_FORCE_EN 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_XTL_26M_MM_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_512M_MM_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_ISPPLL_468M_MM_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_384M_MM_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_307M2_MM_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_256M_MM_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_192M_MM_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_153M6_MM_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_128M_MM_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_96M_MM_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_76M8_MM_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_48M_MM_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_512M_WTLCP_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_384M_WTLCP_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_307M2_WTLCP_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_256M_WTLCP_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_192M_WTLCP_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_153M6_WTLCP_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_128M_WTLCP_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_102M4_WTLCP_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_96M_WTLCP_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG_CGM_TWPLL_85M3_WTLCP_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_76M8_WTLCP_FORCE_EN 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_64M_WTLCP_FORCE_EN 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_51M2_WTLCP_FORCE_EN 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_48M_WTLCP_FORCE_EN 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_614M4_WTLCP_FORCE_EN 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_307M2_WTLCP_FORCE_EN 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_245M76_WTLCP_FORCE_EN 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_204M8_WTLCP_FORCE_EN 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_153M6_WTLCP_FORCE_EN 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_122M88_WTLCP_FORCE_EN 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_102M4_WTLCP_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_LTEPLL_61M44_WTLCP_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_RPLL_26M_WTLCP_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_CPLL_511M18_CDMA_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_CPLL_78M64_CDMA_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_RPLL_26M_CDMA_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_512M_PUBCP_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_384M_PUBCP_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_307M2_PUBCP_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_256M_PUBCP_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_192M_PUBCP_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_153M6_PUBCP_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_128M_PUBCP_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_96M_PUBCP_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_64M_PUBCP_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_51M2_PUBCP_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_48M_PUBCP_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_XTL_26M_PUBCP_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_512M_AUDCP_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_384M_AUDCP_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_307M2_AUDCP_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG_CGM_TWPLL_256M_AUDCP_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_192M_AUDCP_FORCE_EN 0x80000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_153M6_AUDCP_FORCE_EN 0x40000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_128M_AUDCP_FORCE_EN 0x20000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_96M_AUDCP_FORCE_EN 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_64M_AUDCP_FORCE_EN 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_51M2_AUDCP_FORCE_EN 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_48M_AUDCP_FORCE_EN 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_38M4_AUDCP_FORCE_EN 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_LTEPLL_614M4_AUDCP_FORCE_EN 0x800000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_LTEPLL_24M576_AUDCP_FORCE_EN 0x400000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_AUD_26M_AUDCP_FORCE_EN 0x200000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RPLL_26M_AON_FORCE_EN 0x100000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RPLL_390M_AON_FORCE_EN 0x80000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_26M_AON_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_13M_AON_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_6M5_AON_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_4M_AON_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_2M_AON_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_1M_AON_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_XTL_250K_AON_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_AUD_26M_AON_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_100M_AON_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_25M_AON_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_4M_AON_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_RCO_2M_AON_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_GPLL_40M_AON_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_ISPPLL_29M25_AON_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_ISPPLL_78M_AON_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_768M_AON_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_512M_AON_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_384M_AON_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG_CGM_TWPLL_307M2_AON_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_256M_AON_FORCE_EN 0x40000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_192M_AON_FORCE_EN 0x20000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_153M6_AON_FORCE_EN 0x10000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_128M_AON_FORCE_EN 0x8000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_96M_AON_FORCE_EN 0x4000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_76M8_AON_FORCE_EN 0x2000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_64M_AON_FORCE_EN 0x1000
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_51M2_AON_FORCE_EN 0x800
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_48M_AON_FORCE_EN 0x400
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_38M4_AON_FORCE_EN 0x200
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_19M2_AON_FORCE_EN 0x100
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_12M288_AON_FORCE_EN 0x80
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_TWPLL_12M_AON_FORCE_EN 0x40
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_LTEPLL_409M6_AON_FORCE_EN 0x20
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_LTEPLL_30M72_AON_FORCE_EN 0x10
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_MPLL0_56M25_AON_FORCE_EN 0x8
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_MPLL1_62M5_AON_FORCE_EN 0x4
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_MPLL2_46M88_AON_FORCE_EN 0x2
+#define MASK_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG_CGM_DPLL0_50M_AON_FORCE_EN 0x1
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_AP_SEL 0x10000000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_AP_SEL 0x8000000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_64M_AP_SEL 0x4000000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_AP_SEL 0x2000000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_DISP_AP_SEL 0x1000000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_DISP_AP_SEL 0x800000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_MM_SEL 0x400000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_MM_SEL 0x200000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_MM_SEL 0x100000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_WTLCP_SEL 0x80000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_WTLCP_SEL 0x40000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_64M_WTLCP_SEL 0x20000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_WTLCP_SEL 0x10000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_RPLL_26M_WTLCP_SEL 0x8000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_CPLL_511M18_CDMA_SEL 0x4000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_RPLL_26M_CDMA_SEL 0x2000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_PUBCP_SEL 0x1000
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_PUBCP_SEL 0x800
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_64M_PUBCP_SEL 0x400
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_PUBCP_SEL 0x200
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_AUDCP_SEL 0x100
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_AUDCP_SEL 0x80
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_64M_AUDCP_SEL 0x40
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_AUDCP_SEL 0x20
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_AUD_26M_AUDCP_SEL 0x10
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_192M_AON_SEL 0x8
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_96M_AON_SEL 0x4
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_64M_AON_SEL 0x2
+#define MASK_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG_CGM_TWPLL_48M_AON_SEL 0x1
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG_MONITOR_WAIT_EN_STATUS 0x3fffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS00_CFG_MONITOR_DIV_AUTO_EN_STATUS0 0xffffffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS10_CFG_MONITOR_DIV_AUTO_EN_STATUS1 0x1fff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS00_CFG_MONITOR_GATE_AUTO_EN_STATUS0 0xffffffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG_MONITOR_GATE_AUTO_EN_STATUS1 0xffffffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS20_CFG_MONITOR_GATE_AUTO_EN_STATUS2 0xffffffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS30_CFG_MONITOR_GATE_AUTO_EN_STATUS3 0xffffffff
+#define MASK_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS40_CFG_MONITOR_GATE_AUTO_EN_STATUS4 0x7ffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_FIX_VOLTAGE 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_FIX_VOLTAGE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_DVFS_UP_WINDOW 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_DVFS_DOWN_WINDOW 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_ACK 0x200000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_TUNE_EN 0x100000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_VOLTAGE_SW 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_JUDGE_VOLTAGE_SW 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_REQ_SW 0x1
+#define MASK_TOP_DVFS_APB_RF_REG_AUDCP_SYS_VOLTAGE_MEET_BYP 0x4
+#define MASK_TOP_DVFS_APB_RF_REG_GPU_TOP_VOLTAGE_MEET_BYP 0x2
+#define MASK_TOP_DVFS_APB_RF_REG_MM_SYS_VOLTAGE_MEET_BYP 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_JUDGE_VOLTAGE 0x3800000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_CURRENT_VOLTAGE 0x700000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_DVFS_CNT 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_DVFS_STATE 0xf
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_FIX_VOLTAGE 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_FIX_VOLTAGE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_UP_WINDOW 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_DOWN_WINDOW 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_ACK 0x200000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_TUNE_EN 0x100000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_VOLTAGE_SW 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_JUDGE_VOLTAGE_SW 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_REQ_SW 0x1
+#define MASK_TOP_DVFS_APB_RF_REG_AP_SYS_VOLTAGE_MEET_BYP 0x4
+#define MASK_TOP_DVFS_APB_RF_REG_PUBCP_SYS_VOLTAGE_MEET_BYP 0x2
+#define MASK_TOP_DVFS_APB_RF_REG_WTLCP_SYS_VOLTAGE_MEET_BYP 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_JUDGE_VOLTAGE 0x3800000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_CURRENT_VOLTAGE 0x700000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_CNT 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_STATE 0xf
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_FIX_VOLTAGE 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_FIX_VOLTAGE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_UP_WINDOW 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_DOWN_WINDOW 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY5 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY4 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY3 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY5 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY4 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY3 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_ACK 0x200000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_TUNE_EN 0x100000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_VOLTAGE_SW 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_JUDGE_VOLTAGE_SW 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_REQ_SW 0x1
+#define MASK_TOP_DVFS_APB_RF_REG_APCPU_TOP_VOLTAGE_MEET_BYP 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_JUDGE_VOLTAGE 0x3800000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_CURRENT_VOLTAGE 0x700000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_CNT 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_STATE 0xf
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_FIX_VOLTAGE 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_FIX_VOLTAGE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_UP_WINDOW 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_DOWN_WINDOW 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY5 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY4 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY3 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY5 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY4 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY3 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_SW_TUNE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_REG_PROMETHEUS_VOLTAGE_MEET_BYP 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_JUDGE_VOLTAGE 0x70000000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_CURRENT_VOLTAGE 0xe000000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_CNT 0x1fffe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_STATE_I2C 0x1f0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_STATE_ADI 0xf
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_STEP_TUNE_EN 0x10
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_STEP_TUNE_EN 0x8
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_STEP_TUNE_EN 0x4
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_STEP_TUNE_EN 0x2
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_STEP_TUNE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_TOP_DVFS_AUTO_SEL_RCO_EN 0x4
+#define MASK_TOP_DVFS_APB_RF_CGM_TOP_DVFS_FORCE_EN 0x2
+#define MASK_TOP_DVFS_APB_RF_CGM_TOP_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL7 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL6 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL5 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL4 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL3 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL2 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL1 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL0 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL7 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL6 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL5 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL4 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL3 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL2 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL1 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL0 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL7 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL6 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL5 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL4 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL3 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL2 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL1 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL0 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG3 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG7 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG6 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG5 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_CFG4 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG3 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG7 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG6 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG5 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_CFG4 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG3_ADI 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG2_ADI 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG1_ADI 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG0_ADI 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG7_ADI 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG6_ADI 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG5_ADI 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG4_ADI 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG3_ADI 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG2_ADI 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG1_ADI 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG0_ADI 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG7_ADI 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG6_ADI 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG5_ADI 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG4_ADI 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE2 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE1 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE0 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_BAK 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE3 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE2 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE1 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE0 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_BAK 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE3 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE2 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE1 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE0 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE5 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE4 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE3 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE7 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE6 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE2_ADI 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE1_ADI 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE0_ADI 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE5_ADI 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE4_ADI 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE3_ADI 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE7_ADI 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE6_ADI 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_STEP_VOLTAGE 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_STEP_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_STEP_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_STEP_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_STEP_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY7 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY6 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY7 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY6 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY7 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY6 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY7 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY6 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DIALOG_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG7_I2C 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG6_I2C 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG5_I2C 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG4_I2C 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG3_I2C 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG2_I2C 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG1_I2C 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_CFG0_I2C 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG7_I2C 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG6_I2C 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG5_I2C 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG4_I2C 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG3_I2C 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG2_I2C 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG1_I2C 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_CFG0_I2C 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE3_I2C 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE2_I2C 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE1_I2C 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE0_I2C 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE7_I2C 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE6_I2C 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE5_I2C 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE4_I2C 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_ACK_ADI 0x100000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_VOLTAGE_SW_ADI 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_JUDGE_VOLTAGE_SW_ADI 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_REQ_SW_ADI 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_ACK1_I2C 0x80000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_ACK0_I2C 0x40000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_JUDGE_VOLTAGE_SW_I2C 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_VOLTAGE_SW_I2C 0x7f00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_REQ1_SW_I2C 0x80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_DOWN_CFG_SW_I2C 0x70
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_UP_CFG_SW_I2C 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_REQ0_SW_I2C 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_VOLTAGE 0x7fff8000
+#define MASK_TOP_DVFS_APB_RF_AUDCP_SYS_VOLTAGE_MEET 0x4000
+#define MASK_TOP_DVFS_APB_RF_GPU_SYS_VOLTAGE_MEET 0x2000
+#define MASK_TOP_DVFS_APB_RF_MM_SYS_VOLTAGE_MEET 0x1000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_PRE_CURRENT_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_DVFS_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_PRE_VOTE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_VOTE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_VOLTAGE 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_AP_SYS_VOLTAGE_MEET 0x4000
+#define MASK_TOP_DVFS_APB_RF_PUBCP_SYS_VOLTAGE_MEET 0x2000
+#define MASK_TOP_DVFS_APB_RF_WTLCP_SYS_VOLTAGE_MEET 0x1000
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_PRE_CURRENT_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_PRE_VOTE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_VOTE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_VOLTAGE 0x1fffe000
+#define MASK_TOP_DVFS_APB_RF_APCPU_TOP_VOLTAGE_MEET 0x1000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_PRE_CURRENT_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_PRE_VOTE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_VOTE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_VOLTAGE_ADI 0x1fffe000
+#define MASK_TOP_DVFS_APB_RF_PROMETHUES_VOLTAGE_MEET 0x1000
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_PRE_CURRENT_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_PRE_VOTE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_VOTE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_CFG_I2C 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_VOLTAGE_I2C 0x7f
+#define MASK_TOP_DVFS_APB_RF_PUB_SW_DVFS_EN 0x100
+#define MASK_TOP_DVFS_APB_RF_APCPU_DCDC_CPU1_SW_DVFS_EN 0x80
+#define MASK_TOP_DVFS_APB_RF_APCPU_DCDC_CPU0_SW_DVFS_EN 0x40
+#define MASK_TOP_DVFS_APB_RF_AUDCP_SW_DVFS_EN 0x20
+#define MASK_TOP_DVFS_APB_RF_PUBCP_SW_DVFS_EN 0x10
+#define MASK_TOP_DVFS_APB_RF_WTLCP_SW_DVFS_EN 0x8
+#define MASK_TOP_DVFS_APB_RF_MM_SYS_SW_DVFS_EN 0x4
+#define MASK_TOP_DVFS_APB_RF_GPU_SYS_SW_DVFS_EN 0x2
+#define MASK_TOP_DVFS_APB_RF_AP_SYS_SW_DVFS_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_WTLCP_DVFS_URGENCY_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_CNT_CLR 0x200
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_CNT_EN 0x100
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_CNT_CLR 0x80
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_CNT_CLR 0x40
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_CNT_CLR 0x20
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_CNT_CLR 0x10
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_CNT_EN 0x8
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_CNT_EN 0x4
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_CNT_EN 0x2
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_CNT_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_MM_TUNE_CNT 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_MODEM_TUNE_CNT 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU0_TUNE_CNT 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_CPU1_TUNE_CNT 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_PUB_SYS_DVFS_IDLE_VOLTAGE 0x38000000
+#define MASK_TOP_DVFS_APB_RF_AUDCP_SYS_DVFS_IDLE_VOLTAGE 0x7000000
+#define MASK_TOP_DVFS_APB_RF_GPU_TOP_DVFS_IDLE_VOLTAGE 0xe00000
+#define MASK_TOP_DVFS_APB_RF_MM_SYS_DVFS_IDLE_VOLTAGE 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_WTLCP_SYS_DVFS_IDLE_VOLTAGE 0x38000
+#define MASK_TOP_DVFS_APB_RF_PUBCP_SYS_DVFS_IDLE_VOLTAGE 0x7000
+#define MASK_TOP_DVFS_APB_RF_AP_SYS_DVFS_IDLE_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_APCPU_TOP_DVFS_IDLE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_PROMETHEUS_DVFS_IDLE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_MM_MODEM_SHARE_DCDC_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_FIX_VOLTAGE 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_FIX_VOLTAGE_EN 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_UP_WINDOW 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_DOWN_WINDOW 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY_BAK 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY2 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY1 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY0 0xffff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_ACK 0x200000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_TUNE_EN 0x100000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_VOLTAGE_SW 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_JUDGE_VOLTAGE_SW 0xe
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_REQ_SW 0x1
+#define MASK_TOP_DVFS_APB_RF_REG_PUB_SYS_VOLTAGE_MEET_BYP 0x1
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_JUDGE_VOLTAGE 0x3800000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_CURRENT_VOLTAGE 0x700000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_CNT 0xffff0
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_STATE 0xf
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL7 0xe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL6 0x1c0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL5 0x38000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL4 0x7000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL3 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL2 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL1 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL0 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_CFG_BAK 0xfe00000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_CFG2 0x1fc000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_CFG1 0x3f80
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_CFG0 0x7f
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE2 0x7fc0000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE1 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE0 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_BAK 0x3fe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE3 0x1ff
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_VOLTAGE 0xffff0000
+#define MASK_TOP_DVFS_APB_RF_PUB_SYS_VOLTAGE_MEET 0x1000
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_PRE_CURRENT_VOLTAGE 0xe00
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_VOLTAGE 0x1c0
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_PRE_VOTE_VOLTAGE 0x38
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_VOTE_VOLTAGE 0x7
+#define MASK_TOP_DVFS_APB_RF_DCDC_TOP_TUNE_CNT 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_TOP_DVFS_APB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_MM_AHB_RF_FD_EB 0x400
+#define MASK_MM_AHB_RF_DVFS_EB 0x200
+#define MASK_MM_AHB_RF_ISP_AHB_EB 0x100
+#define MASK_MM_AHB_RF_CKG_EB 0x80
+#define MASK_MM_AHB_RF_CSI0_EB 0x40
+#define MASK_MM_AHB_RF_CSI1_EB 0x20
+#define MASK_MM_AHB_RF_CSI2_EB 0x10
+#define MASK_MM_AHB_RF_ISP_EB 0x8
+#define MASK_MM_AHB_RF_DCAM_EB 0x4
+#define MASK_MM_AHB_RF_JPG_EB 0x2
+#define MASK_MM_AHB_RF_CPP_EB 0x1
+#define MASK_MM_AHB_RF_FD_SOFT_RST_MASK 0x8000000
+#define MASK_MM_AHB_RF_FD_SOFT_RST 0x4000000
+#define MASK_MM_AHB_RF_DVFS_SOFT_RST 0x1000000
+#define MASK_MM_AHB_RF_DCAM_ALL_SOFT_RST 0x800000
+#define MASK_MM_AHB_RF_FD_VAU_SOFT_RST 0x400000
+#define MASK_MM_AHB_RF_CPP_VAU_SOFT_RST 0x200000
+#define MASK_MM_AHB_RF_JPG_VAU_SOFT_RST 0x100000
+#define MASK_MM_AHB_RF_JPG_SOFT_RST_MASK 0x80000
+#define MASK_MM_AHB_RF_CPP_SOFT_RST_MASK 0x40000
+#define MASK_MM_AHB_RF_MM_MAIN_SOFT_RST 0x20000
+#define MASK_MM_AHB_RF_CPP_SOFT_RST 0x10000
+#define MASK_MM_AHB_RF_CPP_PATH0_SOFT_RST 0x8000
+#define MASK_MM_AHB_RF_CPP_PATH1_SOFT_RST 0x4000
+#define MASK_MM_AHB_RF_CPP_DMA_SOFT_RST 0x2000
+#define MASK_MM_AHB_RF_ISP_AHB_SOFT_RST 0x1000
+#define MASK_MM_AHB_RF_ISP_VAU_SOFT_RST 0x800
+#define MASK_MM_AHB_RF_ISP_SOFT_RST 0x400
+#define MASK_MM_AHB_RF_MIPI_CSI0_SOFT_RST 0x200
+#define MASK_MM_AHB_RF_MIPI_CSI1_SOFT_RST 0x100
+#define MASK_MM_AHB_RF_MIPI_CSI2_SOFT_RST 0x80
+#define MASK_MM_AHB_RF_DCAM_VAU_SOFT_RST 0x40
+#define MASK_MM_AHB_RF_DCAM0_SOFT_RST 0x20
+#define MASK_MM_AHB_RF_DCAM1_SOFT_RST 0x10
+#define MASK_MM_AHB_RF_DCAM2_SOFT_RST 0x8
+#define MASK_MM_AHB_RF_DCAM_AXI_SOFT_RST 0x4
+#define MASK_MM_AHB_RF_JPG_SOFT_RST 0x2
+#define MASK_MM_AHB_RF_CKG_SOFT_RST 0x1
+#define MASK_MM_AHB_RF_CPHY_CFG_CKG_EN 0x100
+#define MASK_MM_AHB_RF_ISP_AXI_CKG_EN 0x80
+#define MASK_MM_AHB_RF_DCAM_AXI_CKG_EN 0x40
+#define MASK_MM_AHB_RF_MIPI_CSI0_CKG_EN 0x20
+#define MASK_MM_AHB_RF_MIPI_CSI1_CKG_EN 0x10
+#define MASK_MM_AHB_RF_MIPI_CSI2_CKG_EN 0x8
+#define MASK_MM_AHB_RF_SENSOR0_CKG_EN 0x4
+#define MASK_MM_AHB_RF_SENSOR1_CKG_EN 0x2
+#define MASK_MM_AHB_RF_SENSOR2_CKG_EN 0x1
+#define MASK_MM_AHB_RF_AR_QOS_THRESHOLD_MM 0xf0
+#define MASK_MM_AHB_RF_AW_QOS_THRESHOLD_MM 0xf
+#define MASK_MM_AHB_RF_CGM_ISP_AUTO_GATE_SEL 0x8
+#define MASK_MM_AHB_RF_CGM_DCAM_AXI_AUTO_GATE_SEL 0x4
+#define MASK_MM_AHB_RF_CGM_MM_MTX_S0_AUTO_GATE_EN 0x2
+#define MASK_MM_AHB_RF_MM_LPC_DISABLE 0x1
+#define MASK_MM_AHB_RF_PU_NUM_ISP 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_ISP 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_ISP 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_JPG 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_JPG 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_JPG 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_CPP 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_CPP 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_CPP 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_MM_MAIN_MTX_S0 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_MM_MAIN_MTX_S0 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_MM_MAIN_MTX_S0 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_AXI2AHB_M0 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_AXI2AHB_M0 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_AXI2AHB_M0 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_DCAM_ASYNC_BDG 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_DCAM_ASYNC_BDG 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_DCAM_ASYNC_BDG 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_MTX_ASYNC_BDG 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_MTX_ASYNC_BDG 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_MTX_ASYNC_BDG 0xffff
+#define MASK_MM_AHB_RF_ISP_INT_1_MASK 0x8000000
+#define MASK_MM_AHB_RF_ISP_INT_0_MASK 0x4000000
+#define MASK_MM_AHB_RF_DCAM_INT_2_MASK 0x2000000
+#define MASK_MM_AHB_RF_DCAM_INT_1_MASK 0x1000000
+#define MASK_MM_AHB_RF_DCAM_INT_0_MASK 0x800000
+#define MASK_MM_AHB_RF_CGM_DCAM_IF_FDIV_NUM 0x780000
+#define MASK_MM_AHB_RF_CGM_DCAM_IF_FDIV_DENOM 0x78000
+#define MASK_MM_AHB_RF_MIPI_CSI_DPHY_C2_SEL0 0x7000
+#define MASK_MM_AHB_RF_MIPI_CSI_DPHY_C1_SEL1 0xe00
+#define MASK_MM_AHB_RF_MIPI_CSI_DPHY_C1_SEL0 0x1c0
+#define MASK_MM_AHB_RF_MIPI_CSI_DPHY_C0_SEL1 0x38
+#define MASK_MM_AHB_RF_MIPI_CSI_DPHY_C0_SEL0 0x7
+#define MASK_MM_AHB_RF_CSYSACK_SYNC_SEL_DCAM_AS 0x4
+#define MASK_MM_AHB_RF_CACTIVE_SYNC_SEL_DCAM_AS 0x2
+#define MASK_MM_AHB_RF_ISP_BUSY_LSLP_EN 0x1
+#define MASK_MM_AHB_RF_FD_BUSY 0x10
+#define MASK_MM_AHB_RF_DCAM_BUSY 0x8
+#define MASK_MM_AHB_RF_ISP_BUSY 0x4
+#define MASK_MM_AHB_RF_JPG_BUSY 0x2
+#define MASK_MM_AHB_RF_CPP_BUSY 0x1
+#define MASK_MM_AHB_RF_AXI_DETECTOR_OVERFLOW_MTX_AS 0x8
+#define MASK_MM_AHB_RF_AXI_DETECTOR_OVERFLOW_DCAM_AS 0x4
+#define MASK_MM_AHB_RF_BRIDGE_TRANS_IDLE_MTX_AS 0x2
+#define MASK_MM_AHB_RF_BRIDGE_TRANS_IDLE_DCAM_AS 0x1
+#define MASK_MM_AHB_RF_PU_NUM_FD 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_FD 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_FD 0xffff
+#define MASK_MM_AHB_RF_PU_NUM_SLICE_ISP 0xff000000
+#define MASK_MM_AHB_RF_LP_EB_SLICE_ISP 0x10000
+#define MASK_MM_AHB_RF_LP_NUM_SLICE_ISP 0xffff
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_HOLD 0x1
+#define MASK_GPU_DVFS_APB_RF_GPU_TOP_MIN_VOLTAGE 0x7
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_ACK 0x100
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_VOLTAGE_SW 0x70
+#define MASK_GPU_DVFS_APB_RF_GPU_CURRENT_VOLTAGE_SW 0xe
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_REQ_SW 0x1
+#define MASK_GPU_DVFS_APB_RF_REG_GPU_CORE_FREQ_UPD_EN_BYP 0x4
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_DVFS_FORCE_EN 0x2
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_GPU_DVFS_APB_RF_GPU_CURRENT_VOLTAGE 0x7000
+#define MASK_GPU_DVFS_APB_RF_GPU_INTERNAL_VOTE_VOLTAGE 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_DVFS 0x7000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_DVFS 0xe00
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_DVFS 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_DVFS 0x7
+#define MASK_GPU_DVFS_APB_RF_GPU_TOP_DVFS_BUSY 0x80000
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_WINDOW_CNT 0x7fff8
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_STATE 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX0 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX0 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX0 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX0 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX0 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX1 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX1 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX1 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX1 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX1 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX2 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX2 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX2 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX2 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX2 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX3 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX3 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX3 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX3 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX3 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX4 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX4 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX4 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX4 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX4 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX5 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX5 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX5 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX5 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX5 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX6 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX6 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX6 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX6 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX6 0x7
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_SYS_DIV_INDEX7 0x700000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_MEM_DIV_INDEX7 0xe0000
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_VOL_INDEX7 0x1c000
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_DIV_INDEX7 0x38
+#define MASK_GPU_DVFS_APB_RF_CGM_GPU_CORE_SEL_INDEX7 0x7
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_INDEX 0x7
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_DVFS_INDEX_IDLE 0x7
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_GFREE_WAIT_DELAY 0x3ff
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_FREQ_UPD_DELAY_EN 0x2
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_FREQ_UPD_HDSK_EN 0x1
+#define MASK_GPU_DVFS_APB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_GPU_DVFS_APB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_GPU_DVFS_APB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_GPU_DVFS_APB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_UP_WINDOW 0xffff0000
+#define MASK_GPU_DVFS_APB_RF_GPU_DVFS_DOWN_WINDOW 0xffff
+#define MASK_GPU_DVFS_APB_RF_GPU_CORE_DFS_IDLE_DISABLE 0x1
+#define MASK_AP_APB_RF_CE_PUB_EB 0x80000000
+#define MASK_AP_APB_RF_CE_SEC_EB 0x40000000
+#define MASK_AP_APB_RF_EMMC_32K_EB 0x20000000
+#define MASK_AP_APB_RF_SDIO2_32K_EB 0x10000000
+#define MASK_AP_APB_RF_SDIO1_32K_EB 0x8000000
+#define MASK_AP_APB_RF_SDIO0_32K_EB 0x4000000
+#define MASK_AP_APB_RF_EMMC_EB 0x2000000
+#define MASK_AP_APB_RF_SDIO2_EB 0x1000000
+#define MASK_AP_APB_RF_SDIO1_EB 0x800000
+#define MASK_AP_APB_RF_SDIO0_EB 0x400000
+#define MASK_AP_APB_RF_SPI3_LCD_FMARK_IN_EB 0x200000
+#define MASK_AP_APB_RF_SPI2_LCD_FMARK_IN_EB 0x100000
+#define MASK_AP_APB_RF_SPI1_LCD_FMARK_IN_EB 0x80000
+#define MASK_AP_APB_RF_SPI0_LCD_FMARK_IN_EB 0x40000
+#define MASK_AP_APB_RF_SIM0_32K_EB 0x20000
+#define MASK_AP_APB_RF_UART2_EB 0x10000
+#define MASK_AP_APB_RF_UART1_EB 0x8000
+#define MASK_AP_APB_RF_UART0_EB 0x4000
+#define MASK_AP_APB_RF_I2C4_EB 0x2000
+#define MASK_AP_APB_RF_I2C3_EB 0x1000
+#define MASK_AP_APB_RF_I2C2_EB 0x800
+#define MASK_AP_APB_RF_I2C1_EB 0x400
+#define MASK_AP_APB_RF_I2C0_EB 0x200
+#define MASK_AP_APB_RF_SPI3_EB 0x100
+#define MASK_AP_APB_RF_SPI2_EB 0x80
+#define MASK_AP_APB_RF_SPI1_EB 0x40
+#define MASK_AP_APB_RF_SPI0_EB 0x20
+#define MASK_AP_APB_RF_APB_REG_EB 0x10
+#define MASK_AP_APB_RF_IIS2_EB 0x8
+#define MASK_AP_APB_RF_IIS1_EB 0x4
+#define MASK_AP_APB_RF_IIS0_EB 0x2
+#define MASK_AP_APB_RF_SIM0_EB 0x1
+#define MASK_AP_APB_RF_AP_DVFS_SOFT_RST 0x400000
+#define MASK_AP_APB_RF_CE_PUB_SOFT_RST 0x200000
+#define MASK_AP_APB_RF_CE_SEC_SOFT_RST 0x100000
+#define MASK_AP_APB_RF_EMMC_SOFT_RST 0x80000
+#define MASK_AP_APB_RF_SDIO2_SOFT_RST 0x40000
+#define MASK_AP_APB_RF_SDIO1_SOFT_RST 0x20000
+#define MASK_AP_APB_RF_SDIO0_SOFT_RST 0x10000
+#define MASK_AP_APB_RF_UART2_SOFT_RST 0x8000
+#define MASK_AP_APB_RF_UART1_SOFT_RST 0x4000
+#define MASK_AP_APB_RF_UART0_SOFT_RST 0x2000
+#define MASK_AP_APB_RF_I2C4_SOFT_RST 0x1000
+#define MASK_AP_APB_RF_I2C3_SOFT_RST 0x800
+#define MASK_AP_APB_RF_I2C2_SOFT_RST 0x400
+#define MASK_AP_APB_RF_I2C1_SOFT_RST 0x200
+#define MASK_AP_APB_RF_I2C0_SOFT_RST 0x100
+#define MASK_AP_APB_RF_SPI3_SOFT_RST 0x80
+#define MASK_AP_APB_RF_SPI2_SOFT_RST 0x40
+#define MASK_AP_APB_RF_SPI1_SOFT_RST 0x20
+#define MASK_AP_APB_RF_SPI0_SOFT_RST 0x10
+#define MASK_AP_APB_RF_IIS2_SOFT_RST 0x8
+#define MASK_AP_APB_RF_IIS1_SOFT_RST 0x4
+#define MASK_AP_APB_RF_IIS0_SOFT_RST 0x2
+#define MASK_AP_APB_RF_SIM0_SOFT_RST 0x1
+#define MASK_AP_APB_RF_I2C4_SEC_EB 0x4000
+#define MASK_AP_APB_RF_I2C3_SEC_EB 0x2000
+#define MASK_AP_APB_RF_I2C2_SEC_EB 0x1000
+#define MASK_AP_APB_RF_I2C1_SEC_EB 0x800
+#define MASK_AP_APB_RF_I2C0_SEC_EB 0x400
+#define MASK_AP_APB_RF_SPI3_SEC_EB 0x200
+#define MASK_AP_APB_RF_SPI2_SEC_EB 0x100
+#define MASK_AP_APB_RF_SPI1_SEC_EB 0x80
+#define MASK_AP_APB_RF_SPI0_SEC_EB 0x40
+#define MASK_AP_APB_RF_SPI3_FMARK_POLARITY_INV 0x20
+#define MASK_AP_APB_RF_SPI2_FMARK_POLARITY_INV 0x10
+#define MASK_AP_APB_RF_SPI1_FMARK_POLARITY_INV 0x8
+#define MASK_AP_APB_RF_SPI0_FMARK_POLARITY_INV 0x4
+#define MASK_AP_APB_RF_SIM_CLK_POLARITY 0x2
+#define MASK_PUB_QOSC_AHB_RF_QOS_CTRL_ENABLE 0x1
+#define MASK_PUB_QOSC_AHB_RF_QOS_URGENT_COUNT_RESET 0x2
+#define MASK_PUB_QOSC_AHB_RF_QOS_CTRL_RESET 0x1
+#define MASK_PUB_QOSC_AHB_RF_QOSC_CFG_CLK_AUTO_GATE_EN 0x200
+#define MASK_PUB_QOSC_AHB_RF_QOSC_CFG_CLK_EB 0x100
+#define MASK_PUB_QOSC_AHB_RF_QOSC_CLK_TICK_ENABLE 0x10
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMIT_AUTO_GATE_EN 0x2
+#define MASK_PUB_QOSC_AHB_RF_QOSC_PORT_CLK_AUTO_GATE_EN 0x1
+#define MASK_PUB_QOSC_AHB_RF_QOSC_PORT_ENABLE 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNTER_EN_RD 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNTER_EN_WR 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_ARURGENT_EN 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_AWURGENT_EN 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_EN_RD 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_EN_WR 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_NO_SV_BW_SLICE_BYPASS 0x10000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_DFS_FREQ 0x7000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_DFS_PAUSE_ENABLE 0x200000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_MODE 0x100000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_UG_ULTRA_OSTD_ENABLE 0x20000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_UG_HIGH_OSTD_ENABLE 0x10000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_NORM_BYPASS 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH2 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH2 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH3 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH3 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH4 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH4 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH5 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH5 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_WR_CH6 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH6 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH2 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH2 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH3 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH3 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH4 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH4 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH5 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH5 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_ULTRA_RD_CH6 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH6 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH0 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH1 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH2 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH3 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH4 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH5 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH6 0x3f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH7 0x70000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH6 0x7000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH5 0x700000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH4 0x70000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH3 0x7000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH2 0x700
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH1 0x70
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW_CH0 0x7
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH2 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH2 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH3 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH3 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH4 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH4 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH5 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH5 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_RD_CH6 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_WR_CH6 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_HIGH_EN_RD 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_HIGH_EN_WR 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_ULTRA_EN_RD 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_ULTRA_EN_WR 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_LATMON_ARURGENT_EN 0x7f0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_LATMON_AWURGENT_EN 0x7f
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH0 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH0 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH0 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH0 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH0 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH0 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH0 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH0 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH1 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH1 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH1 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH1 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH1 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH1 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH1 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH1 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH2 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH2 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH2 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH2 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH2 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH2 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH2 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH2 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH3 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH3 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH3 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH3 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH3 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH3 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH3 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH3 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH4 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH4 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH4 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH4 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH4 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH4 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH4 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH4 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH5 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH5 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH5 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH5 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH5 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH5 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH5 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH5 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_RD_CH6 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_ULTRA_WR_CH6 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_RD_CH6 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_HIGH_WR_CH6 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_RD_CH6 0xf000
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_NORM_WR_CH6 0xf00
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_RD_CH6 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_LOW_WR_CH6 0xf
+#define MASK_PUB_QOSC_AHB_RF_QOSC_STATUS0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_STATUS1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_STATUS2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH0 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH0 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH1 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH1 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH2 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH2 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH2 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH2 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH3 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH3 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH3 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH3 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH4 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH4 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH4 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH4 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH5 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH5 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH5 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH5 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_RD_CH6 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_RD_CH6 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_COUNT_WR_CH6 0xff00
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_COUNT_WR_CH6 0xff
+#define MASK_PUB_QOSC_AHB_RF_QOS_DBG_MON_SEL 0xf0
+#define MASK_PUB_QOSC_AHB_RF_QOS_DBG_MON_EB 0x2
+#define MASK_PUB_QOSC_AHB_RF_QOS_DBG_MON_START 0x1
+#define MASK_PUB_QOSC_AHB_RF_QOSC_MON_STATUS 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_QOSC_MON_OVERFLOW_CNT 0x1f
+#define MASK_PUB_QOSC_AHB_RF_M1_QOS_CTRL_ENABLE 0x1
+#define MASK_PUB_QOSC_AHB_RF_M1_QOS_CTRL_RESET 0x1
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_CFG_CLK_EB 0x100
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_CLK_TICK_ENABLE 0x30
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMIT_AUTO_GATE_EN 0x2
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_PORT_CLK_AUTO_GATE_EN 0x1
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_PORT_ENABLE 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNTER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNTER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_NO_SV_BW_SLICE_BYPASS 0x10000000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_DFS_PAUSE_ENABLE 0x200000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_MODE 0x100000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_UG_ULTRA_OSTD_ENABLE 0x20000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_UG_HIGH_OSTD_ENABLE 0x10000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_NORM_BYPASS 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_ULTRA_WR_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_ULTRA_WR_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_ULTRA_RD_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_ULTRA_RD_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNT_OFFSET_CH0 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNT_OFFSET_CH1 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_TIMING_WINDOW_CH1 0x70
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_TIMING_WINDOW_CH0 0x7
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_HIGH_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_HIGH_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_ULTRA_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_ULTRA_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_LATMON_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_LATMON_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_ULTRA_RD_CH0 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_ULTRA_WR_CH0 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_HIGH_RD_CH0 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_HIGH_WR_CH0 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_NORM_RD_CH0 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_NORM_WR_CH0 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_LOW_RD_CH0 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_LOW_WR_CH0 0xf
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_ULTRA_RD_CH1 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_ULTRA_WR_CH1 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_HIGH_RD_CH1 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_HIGH_WR_CH1 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_NORM_RD_CH1 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_NORM_WR_CH1 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_LOW_RD_CH1 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_LOW_WR_CH1 0xf
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_STATUS0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_STATUS1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M1_QOSC_STATUS2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_ULTRA_COUNT_RD_CH0 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_HIGH_COUNT_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_ULTRA_COUNT_WR_CH0 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_HIGH_COUNT_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_ULTRA_COUNT_RD_CH1 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_HIGH_COUNT_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_ULTRA_COUNT_WR_CH1 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M1_URGENT_HIGH_COUNT_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOS_CTRL_ENABLE 0x1
+#define MASK_PUB_QOSC_AHB_RF_M2_QOS_CTRL_RESET 0x1
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_CFG_CLK_EB 0x100
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_CLK_TICK_ENABLE 0x30
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMIT_AUTO_GATE_EN 0x2
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_PORT_CLK_AUTO_GATE_EN 0x1
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_PORT_ENABLE 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNTER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNTER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_NO_SV_BW_SLICE_BYPASS 0x10000000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_DFS_PAUSE_ENABLE 0x200000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_MODE 0x100000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_UG_ULTRA_OSTD_ENABLE 0x20000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_UG_HIGH_OSTD_ENABLE 0x10000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_NORM_BYPASS 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_ULTRA_WR_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_ULTRA_WR_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_ULTRA_RD_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_ULTRA_RD_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNT_OFFSET_CH0 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNT_OFFSET_CH1 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_TIMING_WINDOW_CH1 0x70
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_TIMING_WINDOW_CH0 0x7
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_HIGH_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_HIGH_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_ULTRA_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_ULTRA_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_LATMON_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_LATMON_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_ULTRA_RD_CH0 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_ULTRA_WR_CH0 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_HIGH_RD_CH0 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_HIGH_WR_CH0 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_NORM_RD_CH0 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_NORM_WR_CH0 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_LOW_RD_CH0 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_LOW_WR_CH0 0xf
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_ULTRA_RD_CH1 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_ULTRA_WR_CH1 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_HIGH_RD_CH1 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_HIGH_WR_CH1 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_NORM_RD_CH1 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_NORM_WR_CH1 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_LOW_RD_CH1 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_LOW_WR_CH1 0xf
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_STATUS0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_STATUS1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M2_QOSC_STATUS2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_ULTRA_COUNT_RD_CH0 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_HIGH_COUNT_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_ULTRA_COUNT_WR_CH0 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_HIGH_COUNT_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_ULTRA_COUNT_RD_CH1 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_HIGH_COUNT_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_ULTRA_COUNT_WR_CH1 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M2_URGENT_HIGH_COUNT_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_LATMON_SW_TIMER_EN 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_TIMER_SEL 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_LATMON2_SEL 0x10000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_AUTO_GATE_EN 0xf00
+#define MASK_PUB_QOSC_AHB_RF_LATMON_CLK_TICK_ENABLE 0xf0
+#define MASK_PUB_QOSC_AHB_RF_LATMON_ENABLE 0xf
+#define MASK_PUB_QOSC_AHB_RF_LATMON_COUNT_RESET 0xf00
+#define MASK_PUB_QOSC_AHB_RF_LATMON_RESET 0xf
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_RD_LM0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_WR_LM0 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_RD_LM0 0x3000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_WR_LM0 0x300
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_RD_LM0 0x30
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_WR_LM0 0x3
+#define MASK_PUB_QOSC_AHB_RF_LATMON_INIT_URGENT_DEB_LM0 0x70000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_SEL_LM0 0xc000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_VALUE_LM0 0xfff000
+#define MASK_PUB_QOSC_AHB_RF_LAT_SUB_ALL_RATIO_LM0 0x300
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_PERIOD_LM0 0xf
+#define MASK_PUB_QOSC_AHB_RF_LATMON_HW_DFS_TRIGGER_SEL_LM3 0x7000000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_HW_DFS_TRIGGER_SEL_LM2 0x70000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_HW_DFS_TRIGGER_SEL_LM1 0x7000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_HW_DFS_TRIGGER_SEL_LM0 0x700
+#define MASK_PUB_QOSC_AHB_RF_LATMON_HW_DFS_TRIGGER_EN 0xf
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_RD_LM1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_WR_LM1 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_RD_LM1 0x3000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_WR_LM1 0x300
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_RD_LM1 0x30
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_WR_LM1 0x3
+#define MASK_PUB_QOSC_AHB_RF_LATMON_INIT_URGENT_DEB_LM1 0x70000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_SEL_LM1 0xc000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_VALUE_LM1 0xfff000
+#define MASK_PUB_QOSC_AHB_RF_LAT_SUB_ALL_RATIO_LM1 0x300
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_PERIOD_LM1 0xf
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_RD_LM2 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_WR_LM2 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_RD_LM2 0x3000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_WR_LM2 0x300
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_RD_LM2 0x30
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_WR_LM2 0x3
+#define MASK_PUB_QOSC_AHB_RF_LATMON_INIT_URGENT_DEB_LM2 0x70000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_SEL_LM2 0xc000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_VALUE_LM2 0xfff000
+#define MASK_PUB_QOSC_AHB_RF_LAT_SUB_ALL_RATIO_LM2 0x300
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_PERIOD_LM2 0xf
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_RD_LM3 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_WR_LM3 0xff
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_RD_LM3 0x3000
+#define MASK_PUB_QOSC_AHB_RF_URGENT_ULTRA_RATIO_WR_LM3 0x300
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_RD_LM3 0x30
+#define MASK_PUB_QOSC_AHB_RF_URGENT_HIGH_RATIO_WR_LM3 0x3
+#define MASK_PUB_QOSC_AHB_RF_LATMON_INIT_URGENT_DEB_LM3 0x70000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_SEL_LM3 0xc000000
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_VALUE_LM3 0xfff000
+#define MASK_PUB_QOSC_AHB_RF_LAT_SUB_ALL_RATIO_LM3 0x300
+#define MASK_PUB_QOSC_AHB_RF_TIMER_LAT_SUB_PERIOD_LM3 0xf
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_WR_LM0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_WR_LM0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_RD_LM0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_RD_LM0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_WR_LM1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_WR_LM1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_RD_LM1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_RD_LM1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_WR_LM2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_WR_LM2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_RD_LM2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_RD_LM2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_WR_LM3 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_WR_LM3 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_ACTUAL_RD_LM3 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATENCY_TARGET_RD_LM3 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_LATMON3_UPDATE_FLAG_CLR 0x800000
+#define MASK_PUB_QOSC_AHB_RF_LATMON2_UPDATE_FLAG_CLR 0x400000
+#define MASK_PUB_QOSC_AHB_RF_LATMON1_UPDATE_FLAG_CLR 0x200000
+#define MASK_PUB_QOSC_AHB_RF_LATMON0_UPDATE_FLAG_CLR 0x100000
+#define MASK_PUB_QOSC_AHB_RF_LATMON3_UPDATE_FLAG 0x80000
+#define MASK_PUB_QOSC_AHB_RF_LATMON2_UPDATE_FLAG 0x40000
+#define MASK_PUB_QOSC_AHB_RF_LATMON1_UPDATE_FLAG 0x20000
+#define MASK_PUB_QOSC_AHB_RF_LATMON0_UPDATE_FLAG 0x10000
+#define MASK_PUB_QOSC_AHB_RF_LATMON_COUNTER_OV_ST 0xffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON_F_UP_REQ_EN 0x7000
+#define MASK_PUB_QOSC_AHB_RF_BWMON_RBW_EN 0x700
+#define MASK_PUB_QOSC_AHB_RF_BWMON_WBW_EN 0x70
+#define MASK_PUB_QOSC_AHB_RF_BWMON_ENABLE 0x7
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_UP_WBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_UP_RBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_UP_WBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_UP_RBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_UP_WBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_UP_RBW_SET 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_UPDATE_FLAG_CLR 0x400
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_UPDATE_FLAG_CLR 0x200
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_UPDATE_FLAG_CLR 0x100
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_UPDATE_FLAG 0x4
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_UPDATE_FLAG 0x2
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_UPDATE_FLAG 0x1
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_WBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON0_RBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_WBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON1_RBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_WBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_BWMON2_RBW_CNT 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOS_CTRL_ENABLE 0x1
+#define MASK_PUB_QOSC_AHB_RF_M3_QOS_CTRL_RESET 0x1
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_CFG_CLK_EB 0x100
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_CLK_TICK_ENABLE 0x30
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMIT_AUTO_GATE_EN 0x2
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_PORT_CLK_AUTO_GATE_EN 0x1
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_PORT_ENABLE 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNTER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNTER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_NO_SV_BW_SLICE_BYPASS 0x10000000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_DFS_PAUSE_ENABLE 0x200000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_MODE 0x100000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_UG_ULTRA_OSTD_ENABLE 0x20000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_UG_HIGH_OSTD_ENABLE 0x10000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_NORM_BYPASS 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_ULTRA_WR_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_ULTRA_WR_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_ULTRA_RD_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_ULTRA_RD_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNT_OFFSET_CH0 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNT_OFFSET_CH1 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_TIMING_WINDOW_CH1 0x70
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_TIMING_WINDOW_CH0 0x7
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_HIGH_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_HIGH_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_ULTRA_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_ULTRA_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_LATMON_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_LATMON_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_ULTRA_RD_CH0 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_ULTRA_WR_CH0 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_HIGH_RD_CH0 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_HIGH_WR_CH0 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_NORM_RD_CH0 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_NORM_WR_CH0 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_LOW_RD_CH0 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_LOW_WR_CH0 0xf
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_ULTRA_RD_CH1 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_ULTRA_WR_CH1 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_HIGH_RD_CH1 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_HIGH_WR_CH1 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_NORM_RD_CH1 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_NORM_WR_CH1 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_LOW_RD_CH1 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_LOW_WR_CH1 0xf
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_STATUS0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_STATUS1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M3_QOSC_STATUS2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_ULTRA_COUNT_RD_CH0 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_HIGH_COUNT_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_ULTRA_COUNT_WR_CH0 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_HIGH_COUNT_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_ULTRA_COUNT_RD_CH1 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_HIGH_COUNT_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_ULTRA_COUNT_WR_CH1 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M3_URGENT_HIGH_COUNT_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOS_CTRL_ENABLE 0x1
+#define MASK_PUB_QOSC_AHB_RF_M4_QOS_CTRL_RESET 0x1
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_CFG_CLK_EB 0x100
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_CLK_TICK_ENABLE 0x30
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMIT_AUTO_GATE_EN 0x2
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_PORT_CLK_AUTO_GATE_EN 0x1
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_PORT_ENABLE 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNTER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNTER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_NO_SV_BW_SLICE_BYPASS 0x10000000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_DFS_PAUSE_ENABLE 0x200000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_MODE 0x100000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_UG_ULTRA_OSTD_ENABLE 0x20000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_UG_HIGH_OSTD_ENABLE 0x10000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_NORM_BYPASS 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_ULTRA_WR_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_ULTRA_WR_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_ULTRA_RD_CH0 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_ULTRA_RD_CH1 0x3ff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x3ff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNT_OFFSET_CH0 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNT_OFFSET_CH1 0x3f
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_TIMING_WINDOW_CH1 0x70
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_TIMING_WINDOW_CH0 0x7
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_WR_CH1 0xff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_HIGH_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_HIGH_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_ULTRA_EN_RD 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_ULTRA_EN_WR 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_LATMON_ARURGENT_EN 0x30000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_LATMON_AWURGENT_EN 0x3
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_ULTRA_RD_CH0 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_ULTRA_WR_CH0 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_HIGH_RD_CH0 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_HIGH_WR_CH0 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_NORM_RD_CH0 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_NORM_WR_CH0 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_LOW_RD_CH0 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_LOW_WR_CH0 0xf
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_ULTRA_RD_CH1 0xf0000000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_ULTRA_WR_CH1 0xf000000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_HIGH_RD_CH1 0xf00000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_HIGH_WR_CH1 0xf0000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_NORM_RD_CH1 0xf000
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_NORM_WR_CH1 0xf00
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_LOW_RD_CH1 0xf0
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_LOW_WR_CH1 0xf
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_STATUS0 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_STATUS1 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M4_QOSC_STATUS2 0xffffffff
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_ULTRA_COUNT_RD_CH0 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_HIGH_COUNT_RD_CH0 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_ULTRA_COUNT_WR_CH0 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_HIGH_COUNT_WR_CH0 0xff
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_ULTRA_COUNT_RD_CH1 0xff000000
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_HIGH_COUNT_RD_CH1 0xff0000
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_ULTRA_COUNT_WR_CH1 0xff00
+#define MASK_PUB_QOSC_AHB_RF_M4_URGENT_HIGH_COUNT_WR_CH1 0xff
+#define MASK_GPU_APB_RF_SYS_SOFT_RST_REQ_CORE 0x2
+#define MASK_GPU_APB_RF_GPU_CORE_SOFT_RST 0x1
+#define MASK_GPU_APB_RF_CGM_GPU_CORE_FDIV_DENOM 0xf00000
+#define MASK_GPU_APB_RF_CGM_GPU_CORE_FDIV_NUM 0xf0000
+#define MASK_GPU_APB_RF_CGM_GPU_CORE_DIV 0x700
+#define MASK_GPU_APB_RF_CGM_GPU_CORE_SEL 0x70
+#define MASK_GPU_APB_RF_CGM_GPU_CORE_EB 0x1
+#define MASK_GPU_APB_RF_CGM_GPU_MEM_FDIV_DENOM 0xf00000
+#define MASK_GPU_APB_RF_CGM_GPU_MEM_FDIV_NUM 0xf0000
+#define MASK_GPU_APB_RF_CGM_GPU_MEM_DIV 0x700
+#define MASK_GPU_APB_RF_CGM_GPU_MEM_SEL 0x70
+#define MASK_GPU_APB_RF_CGM_GPU_MEM_EB 0x1
+#define MASK_GPU_APB_RF_CGM_GPU_SYS_DIV 0x70
+#define MASK_GPU_APB_RF_CGM_GPU_SYS_EB 0x1
+#define MASK_GPU_APB_RF_GPU_QOS_SEL 0x10000
+#define MASK_GPU_APB_RF_AWQOS_THRESHOLD_GPU 0xf000
+#define MASK_GPU_APB_RF_ARQOS_THRESHOLD_GPU 0xf00
+#define MASK_GPU_APB_RF_AWQOS_GPU 0xf0
+#define MASK_GPU_APB_RF_ARQOS_GPU 0xf
+#define MASK_GPU_APB_RF_PU_NUM_AB_W 0xff000000
+#define MASK_GPU_APB_RF_AXI_LP_CTRL_DISABLE 0x100000
+#define MASK_GPU_APB_RF_LP_EB_AB_W 0x10000
+#define MASK_GPU_APB_RF_LP_NUM_AB_W 0xffff
+#define MASK_GPU_APB_RF_PU_NUM_M0 0xff000000
+#define MASK_GPU_APB_RF_LP_EB_M0 0x10000
+#define MASK_GPU_APB_RF_LP_NUM_M0 0xffff
+#define MASK_GPU_APB_RF_PU_NUM_S0 0xff000000
+#define MASK_GPU_APB_RF_LP_EB_S0 0x10000
+#define MASK_GPU_APB_RF_LP_NUM_S0 0xffff
+#define MASK_GPU_APB_RF_PU_NUM_S1 0xff000000
+#define MASK_GPU_APB_RF_LP_EB_S1 0x10000
+#define MASK_GPU_APB_RF_LP_NUM_S1 0xffff
+#define MASK_GPU_APB_RF_RST_SUBSYS 0x4
+#define MASK_GPU_APB_RF_BRIDGE_TRANS_IDLE 0x2
+#define MASK_GPU_APB_RF_AXI_DETECTOR_OVERFLOW 0x1
+#define MASK_GPU_APB_RF_LP_EB_GONDUL 0x10000
+#define MASK_GPU_APB_RF_LP_NUM_GONDUL 0xffff
+#define MASK_GPU_APB_RF_PDC_PWRUP_INT_ST0 0x200
+#define MASK_GPU_APB_RF_PDC_ISOLATE_N_INT_ST0 0x100
+#define MASK_GPU_APB_RF_CUR_ST_ST0 0xf0
+#define MASK_GPU_APB_RF_NEW_POINT_SEL_ST0 0x4
+#define MASK_GPU_APB_RF_CORE_FORCE_RST_ISO_OFF_ST0 0x2
+#define MASK_GPU_APB_RF_FORCE_POWER_ON_ST0 0x1
+#define MASK_GPU_APB_RF_PDC_PWRUP_INT_ST1 0x200
+#define MASK_GPU_APB_RF_PDC_ISOLATE_N_INT_ST1 0x100
+#define MASK_GPU_APB_RF_CUR_ST_ST1 0xf0
+#define MASK_GPU_APB_RF_NEW_POINT_SEL_ST1 0x4
+#define MASK_GPU_APB_RF_CORE_FORCE_RST_ISO_OFF_ST1 0x2
+#define MASK_GPU_APB_RF_FORCE_POWER_ON_ST1 0x1
+#define MASK_GPU_APB_RF_TEXFMTENABLE 0xffffffff
+#define MASK_GPU_APB_RF_CGM_GPU_26M_EN 0x80000000
+#define MASK_GPU_APB_RF_NIDEN 0x20
+#define MASK_GPU_APB_RF_DBGEN 0x10
+#define MASK_GPU_APB_RF_STRIPING_GONDUL 0x7
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATECLK 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSCLKNOT 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RXCLKACTIVEHS 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOTCLK 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSESC_0 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOT_0 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSESC_1 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOT_1 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_DIRECTION_0 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_0 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATEDATA_0 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_DIRECTION_1 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_1 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATEDATA_1 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTHS_0 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTSYNCHS_0 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRESC_0 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSYNCESC_0 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRCONTROL_0 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTHS_1 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTSYNCHS_1 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRESC_1 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRSYNCESC_1 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ERRCONTROL_1 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_SHUTDOWNZ 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RSTZ 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_0 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_1 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ENABLECLK 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_IF_SEL 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_BISTON 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_BISTOK 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_S 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_L 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RX_RCTL 0xf
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_FORCE_CSI_PHY_SHUTDOWNZ 0x4000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_FORCE_DSI_PHY_SHUTDOWNZ 0x2000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_FORCE_CSI_S_PHY_SHUTDOWNZ 0x1000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_FORCE_DSI_DBG_PHY_SHUTDOWNZ 0x800000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_M_EN 0x400000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_M_SEL 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_M 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_S_EN 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_S_SEL 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2P2L_TESTCLR_S 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_REFDIV 0x1e000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_TXREQHSCLK_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_RXBYTECLK_SEL 0xc00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_D0_TXSRC_SEL 0x300
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_D1_TXSRC_SEL 0xc0
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_D2_TXSRC_SEL 0x30
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_D3_TXSRC_SEL 0xc
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_TEST_SEL 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_BERT_REFCLK_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RESERVEDO 0xff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_ANALOG_CSI_DUMY_IN 0xffff0000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_ANALOG_CSI_DUMY_OUT 0xffff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_RESERVED 0xff
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_0 0x1000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_1 0x800
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_SHUTDOWNZ 0x400
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_RSTZ 0x200
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_0 0x100
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_1 0x80
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLECLK 0x40
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_IF_SEL 0x20
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_BISTON 0x10
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_S 0x8
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_L 0x4
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ISO_SW_EN 0x2
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_RESERVED 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATECLK_M 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSCLKNOT_M 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXCLKACTIVEHS_M 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOTCLK_M 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_1_M 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_0_M 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_0_M 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_0_M 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_M 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_0_M 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_0_M 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_0_M 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_0_M 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_0_M 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_0_M 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_1_M 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_1_M 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_M 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_1_M 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_1_M 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_1_M 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_1_M 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_1_M 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_1_M 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_M 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_M 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_M 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_M 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_M 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_M 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_M 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTOK_M 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_MODE_SEL 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RX_RCTL 0xf
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATECLK_S 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSCLKNOT_S 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXCLKACTIVEHS_S 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOTCLK_S 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_1_S 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_0_S 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_0_S 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_0_S 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_S 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_0_S 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_0_S 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_0_S 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_0_S 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_0_S 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_0_S 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_1_S 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_1_S 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_S 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_1_S 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_1_S 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_1_S 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_1_S 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_1_S 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_1_S 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_S 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_S 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_S 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_S 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_S 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_S 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_S 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTOK_S 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RESERVED 0xff00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RESERVEDO 0xff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTHSCLK_DB 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSCLK_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXITCLK_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATECLK_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOTCLK_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_0_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_0_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_0_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_0_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_0_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_0_DB 0x3c
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_0_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_0_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_1_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_1_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_1_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_1_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_1_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_1_DB 0x3c
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_1_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_1_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_2_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_2_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_2_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_2_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_2_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_2_DB 0x3c
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_2_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_2_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_3_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_3_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_3_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_3_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_3_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_3_DB 0x3c
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_3_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_0_DB 0xff000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_1_DB 0xff0000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_2_DB 0xff00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_3_DB 0xff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_0_DB 0x8000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_0_DB 0x4000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_0_DB 0x3c00000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_0_DB 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_1_DB 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_1_DB 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_1_DB 0x78000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_1_DB 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_2_DB 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_2_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_2_DB 0xf00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_2_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_3_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_3_DB 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_3_DB 0x1e
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_0_DB 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_1_DB 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_2_DB 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_3_DB 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_0_DB 0xff00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_1_DB 0xff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_2_DB 0xff000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_3_DB 0xff0
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_0_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_1_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_2_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_1_DB 0x800000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_0_DB 0x400000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_0_DB 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_0_DB 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_0_DB 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_0_DB 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_0_DB 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_1_DB 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_1_DB 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_1_DB 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_1_DB 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_1_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_2_DB 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_2_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_2_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_2_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_2_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_2_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_3_DB 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_3_DB 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_3_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_3_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_3_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_0_DB 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_0_DB 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_0_DB 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_0_DB 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_0_DB 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_1_DB 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_1_DB 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_1_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_1_DB 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_1_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_2_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_2_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_2_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_2_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_2_DB 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_3_DB 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_3_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_3_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_3_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_SHUTDOWNZ_DB 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_RSTZ_DB 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_0_DB 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_1_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_2_DB 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_3_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLECLK_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCEPLL_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_BISTON_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_BISTDONE_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_IF_SEL_DB 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DEBUG_EN_DB 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TRIMBG_DB 0xf
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTDIN_DB 0x7f800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTDOUT_DB 0x7f8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTEN_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTCLK_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTCLR_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCALHS_0_M 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_DONE_0_M 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_FAIL_0_M 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCALHS_1_M 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_DONE_1_M 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_FAIL_1_M 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCALHS_0_S 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_DONE_0_S 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_FAIL_0_S 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCALHS_1_S 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_DONE_1_S 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_RXSKEWCAL_FAIL_1_S 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_0_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_1_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_2_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_ATE_TEST_SEL 0x3
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_M 0x80000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_M 0x40000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_M 0x20000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_M 0x10000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_M 0x8000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_M 0x4000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_M 0x2000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_M 0x1000000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_M 0x800000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S 0x400000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L 0x200000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_S 0x100000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_S 0x80000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_S 0x40000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_S 0x20000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_S 0x10000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_S 0x8000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_S 0x4000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_S 0x2000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_S 0x1000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTHSCLK_DB 0x800
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_0_DB 0x400
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_1_DB 0x200
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_2_DB 0x100
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_3_DB 0x80
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_SHUTDOWNZ_DB 0x40
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_IF_SEL_DB 0x20
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DEBUG_EN_DB 0x10
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_0_DB 0x8
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_1_DB 0x4
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_2_DB 0x2
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXSKEWCALHS_3_DB 0x1
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_STOPSTATECLK 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXULPSCLKNOT 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXCLKACTIVEHS 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ULPSACTIVENOTCLK 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXULPSESC_0 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ULPSACTIVENOT_0 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXULPSESC_1 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ULPSACTIVENOT_1 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXULPSESC_2 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ULPSACTIVENOT_2 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXULPSESC_3 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ULPSACTIVENOT_3 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_DIRECTION_0 0x80000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_0 0x40000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_STOPSTATEDATA_0 0x20000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_DIRECTION_1 0x10000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_1 0x8000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_STOPSTATEDATA_1 0x4000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_DIRECTION_2 0x2000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_2 0x1000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_STOPSTATEDATA_2 0x800000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_DIRECTION_3 0x400000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_3 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_STOPSTATEDATA_3 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTHS_0 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTSYNCHS_0 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRESC_0 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSYNCESC_0 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRCONTROL_0 0x8000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTHS_1 0x4000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTSYNCHS_1 0x2000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRESC_1 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSYNCESC_1 0x800
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRCONTROL_1 0x400
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTHS_2 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTSYNCHS_2 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRESC_2 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSYNCESC_2 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRCONTROL_2 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTHS_3 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSOTSYNCHS_3 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRESC_3 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRSYNCESC_3 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ERRCONTROL_3 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_SHUTDOWNZ 0x200
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RSTZ 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_0 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_1 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_2 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_3 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ENABLECLK 0x8
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_IF_SEL 0x4
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_BISTON 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_BISTOK 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_PS_PD_S 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_PS_PD_L 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RX_RCTL 0xf
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RESERVEDO 0xffff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_ISO_SW_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCALHS_0 0x8000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_DONE_0 0x4000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_FAIL_0 0x2000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCALHS_1 0x1000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_DONE_1 0x800000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_FAIL_1 0x400000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCALHS_2 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_DONE_2 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_FAIL_2 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCALHS_3 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_DONE_3 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXSKEWCAL_FAIL_3 0x10000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RESERVED 0xffff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_FORCE_CSI_PHY_SHUTDOWNZ 0x4000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_FORCE_DSI_PHY_SHUTDOWNZ 0x2000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_FORCE_CSI_S_PHY_SHUTDOWNZ 0x1000000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_FORCE_DSI_DBG_PHY_SHUTDOWNZ 0x800000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_M_EN 0x400000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_M_SEL 0x200000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_M 0x100000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_S_EN 0x80000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_S_SEL 0x40000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_2P2L_TESTCLR_S 0x20000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_REFDIV 0x1e000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_TXREQHSCLK_DB 0x1000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_RXBYTECLK_SEL 0xc00
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_D0_TXSRC_SEL 0x300
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_D1_TXSRC_SEL 0xc0
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_D2_TXSRC_SEL 0x30
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_D3_TXSRC_SEL 0xc
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_TEST_SEL 0x2
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_MIPI_BERT_REFCLK_EN 0x1
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_ANALOG_CSI_DUMY_OUT 0xffff0000
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_ANALOG_CSI_DUMY_IN 0xffff
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXINVALIDCODEHS_0 0x100
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXINVALIDCODEHS_1 0x80
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_RXINVALIDCODEHS_2 0x40
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_PHY_SEL 0x20
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_TEST_REG_SEL 0x10
+#define MASK_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_RG_CSI_LDO_VOUT_SEL 0xf
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_PHY_SEL 0x80000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_TEST_REG_SEL 0x40000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_RG_CSI_LDO_VOUT_S 0x20000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_0 0x10000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_1 0x8000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_2 0x4000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_FORCERXMODE_3 0x2000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_SHUTDOWNZ 0x1000
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_RSTZ 0x800
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_0 0x400
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_1 0x200
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_2 0x100
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ENABLE_3 0x80
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ENABLECLK 0x40
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_IF_SEL 0x20
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_BISTON 0x10
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_PS_PD_S 0x8
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_PS_PD_L 0x4
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_ISO_SW_EN 0x2
+#define MASK_ANLG_PHY_G10_RF_DBG_SEL_ANALOG_MIPI_CSI_COMBO_CSI_RESERVED 0x1
+#define MASK_AON_CLK_CORE_CGM_AON_APB_CFG_CGM_AON_APB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_AON_APB_CFG_CGM_AON_APB_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_ADI_CFG_CGM_ADI_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_AUX0_CFG_CGM_AUX0_DIV 0xf00
+#define MASK_AON_CLK_CORE_CGM_AUX0_CFG_CGM_AUX0_SEL 0x1f
+#define MASK_AON_CLK_CORE_CGM_AUX1_CFG_CGM_AUX1_DIV 0xf00
+#define MASK_AON_CLK_CORE_CGM_AUX1_CFG_CGM_AUX1_SEL 0x1f
+#define MASK_AON_CLK_CORE_CGM_AUX2_CFG_CGM_AUX2_DIV 0xf00
+#define MASK_AON_CLK_CORE_CGM_AUX2_CFG_CGM_AUX2_SEL 0x1f
+#define MASK_AON_CLK_CORE_CGM_PROBE_CFG_CGM_PROBE_DIV 0xf00
+#define MASK_AON_CLK_CORE_CGM_PROBE_CFG_CGM_PROBE_SEL 0x1f
+#define MASK_AON_CLK_CORE_CGM_PWM0_CFG_CGM_PWM0_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_PWM1_CFG_CGM_PWM1_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_PWM2_CFG_CGM_PWM2_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_PWM3_CFG_CGM_PWM3_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_EFUSE_CFG_CGM_EFUSE_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_UART0_CFG_CGM_UART0_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_UART1_CFG_CGM_UART1_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_32K_OUT_CFG_CGM_32K_OUT_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_THM0_CFG_CGM_THM0_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_THM1_CFG_CGM_THM1_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_THM2_CFG_CGM_THM2_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_THM3_CFG_CGM_THM3_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_CM4_I3C0_CFG_CGM_CM4_I3C0_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_CM4_I3C1_CFG_CGM_CM4_I3C1_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_CM4_SPI_CFG_CGM_CM4_SPI_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_CM4_SPI_CFG_CGM_CM4_SPI_DIV 0x700
+#define MASK_AON_CLK_CORE_CGM_CM4_SPI_CFG_CGM_CM4_SPI_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_AON_I2C_CFG_CGM_AON_I2C_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_AON_IIS_CFG_CGM_AON_IIS_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_SCC_CFG_CGM_SCC_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_APCPU_DAP_CFG_CGM_APCPU_DAP_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_APCPU_DAP_MTCK_CFG_CGM_APCPU_DAP_MTCK_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_APCPU_TS_CFG_CGM_APCPU_TS_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_DEBUG_TS_CFG_CGM_DEBUG_TS_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_DSI_TEST_S_CFG_CGM_DSI_TEST_S_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_RFTI_SBI_CFG_CGM_RFTI_SBI_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_RFTI1_XO_CFG_CGM_RFTI1_XO_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_RFTI_LTH_CFG_CGM_RFTI_LTH_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_RFTI2_XO_CFG_CGM_RFTI2_XO_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_RCO100M_REF_CFG_CGM_RCO100M_REF_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_RCO100M_FDK_CFG_CGM_RCO100M_FDK_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_DJTAG_TCK_CFG_CGM_DJTAG_TCK_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_DJTAG_TCK_CFG_CGM_DJTAG_TCK_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_DJTAG_TCK_HW_CFG_CGM_DJTAG_TCK_HW_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_SP_AHB_CFG_CGM_SP_AHB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_SP_AHB_CFG_CGM_SP_AHB_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_TMR_CFG_CGM_TMR_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_DET_32K_CFG_CGM_DET_32K_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_PMU_CFG_CGM_PMU_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_DEBOUNCE_CFG_CGM_DEBOUNCE_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_APCPU_PMU_CFG_CGM_APCPU_PMU_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_FUNC_DMA_CFG_CGM_FUNC_DMA_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_TOP_DVFS_CFG_CGM_TOP_DVFS_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_OTG_UTMI_CFG_CGM_OTG_UTMI_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_OTG_REF_CFG_CGM_OTG_REF_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_CSSYS_CFG_CGM_CSSYS_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_CSSYS_CFG_CGM_CSSYS_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_CSSYS_PUB_CFG_CGM_CSSYS_PUB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_CSSYS_APB_CFG_CGM_CSSYS_APB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_AP_AXI_CFG_CGM_AP_AXI_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_AP_MM_CFG_CGM_AP_MM_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_SDIO2_2X_CFG_CGM_SDIO2_2X_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG_CGM_ANALOG_IO_APB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG_CGM_ANALOG_IO_APB_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_DMC_REF_CFG_CGM_DMC_REF_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_USB20_SCAN_ONLY_CFG_CGM_USB20_SCAN_ONLY_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_EMC_CFG_CGM_EMC_SEL 0x3
+#define MASK_AON_CLK_CORE_CGM_USB_CFG_CGM_USB_PAD_SEL 0x10000
+#define MASK_AON_CLK_CORE_CGM_USB_CFG_CGM_USB_DIV 0x300
+#define MASK_AON_CLK_CORE_CGM_USB_CFG_CGM_USB_SEL 0x7
+#define MASK_AON_CLK_CORE_CGM_AAPC_TEST_CFG_CGM_AAPC_TEST_DIV 0xf00
+#define MASK_AON_CLK_CORE_CGM_AAPC_TEST_CFG_CGM_AAPC_TEST_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_26M_PMU_CFG_CGM_26M_PMU_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_CPHY_CFG_CFG_CGM_CPHY_CFG_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_CSI_PHY_SCAN_ONLY_CFG_CGM_CSI_PHY_SCAN_ONLY_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_WCDMA_SLICE_SCAN_ONLY_CFG_CGM_WCDMA_SLICE_SCAN_ONLY_SEL 0x1
+#define MASK_AON_CLK_CORE_CGM_26M_ETC_CFG_CGM_26M_ETC_SEL 0x1
+#define MASK_AUD_CP_AHB_RF_DVFS_ASHB_EB 0x800000
+#define MASK_AUD_CP_AHB_RF_TMR_26M_EB 0x400000
+#define MASK_AUD_CP_AHB_RF_VBC_24M_EB 0x200000
+#define MASK_AUD_CP_AHB_RF_AUDIF_CKG_AUTO_EN 0x100000
+#define MASK_AUD_CP_AHB_RF_AUD_EB 0x80000
+#define MASK_AUD_CP_AHB_RF_DMA_CP_ASHB_EB 0x40000
+#define MASK_AUD_CP_AHB_RF_DMA_AP_ASHB_EB 0x20000
+#define MASK_AUD_CP_AHB_RF_ICU_EB 0x10000
+#define MASK_AUD_CP_AHB_RF_SPINLOCK_EB 0x8000
+#define MASK_AUD_CP_AHB_RF_VBC_EB 0x4000
+#define MASK_AUD_CP_AHB_RF_VBCIFD_EB 0x2000
+#define MASK_AUD_CP_AHB_RF_MCDT_EB 0x1000
+#define MASK_AUD_CP_AHB_RF_SRC48K_EB 0x400
+#define MASK_AUD_CP_AHB_RF_DMA_AP_EB 0x40
+#define MASK_AUD_CP_AHB_RF_DMA_CP_EB 0x20
+#define MASK_AUD_CP_AHB_RF_UART_EB 0x10
+#define MASK_AUD_CP_AHB_RF_IIS2_EB 0x4
+#define MASK_AUD_CP_AHB_RF_IIS1_EB 0x2
+#define MASK_AUD_CP_AHB_RF_IIS0_EB 0x1
+#define MASK_AUD_CP_AHB_RF_DVFS_SOFT_RST 0x4000000
+#define MASK_AUD_CP_AHB_RF_AUD_SOFT_RST 0x2000000
+#define MASK_AUD_CP_AHB_RF_UART_SOFT_RST 0x10000
+#define MASK_AUD_CP_AHB_RF_IIS2_SOFT_RST 0x4000
+#define MASK_AUD_CP_AHB_RF_IIS1_SOFT_RST 0x2000
+#define MASK_AUD_CP_AHB_RF_IIS0_SOFT_RST 0x1000
+#define MASK_AUD_CP_AHB_RF_DMA_CP_SOFT_RST 0x800
+#define MASK_AUD_CP_AHB_RF_SPINLOCK_SOFT_RST 0x400
+#define MASK_AUD_CP_AHB_RF_VBC_SOFT_RST 0x200
+#define MASK_AUD_CP_AHB_RF_VBCIFD_SOFT_RST 0x100
+#define MASK_AUD_CP_AHB_RF_MCDT_SOFT_RST 0x80
+#define MASK_AUD_CP_AHB_RF_SRC48K_SOFT_RST 0x20
+#define MASK_AUD_CP_AHB_RF_DMA_AP_SOFT_RST 0x2
+#define MASK_AUD_CP_AHB_RF_VBC_24M_SOFT_RST 0x1
+#define MASK_AUD_CP_AHB_RF_SLAVE0_PUB0_FRC_LSLP 0x10000
+#define MASK_AUD_CP_AHB_RF_MASTER4_PUB0_FRC_LSLP 0x4000
+#define MASK_AUD_CP_AHB_RF_MASTER3_PUB0_FRC_LSLP 0x2000
+#define MASK_AUD_CP_AHB_RF_MASTER2_PUB0_FRC_LSLP 0x1000
+#define MASK_AUD_CP_AHB_RF_MASTER1_PUB0_FRC_LSLP 0x800
+#define MASK_AUD_CP_AHB_RF_MASTER0_PUB0_FRC_LSLP 0x400
+#define MASK_AUD_CP_AHB_RF_DMA_CHN2_GRP2_LSLP_EN 0x200
+#define MASK_AUD_CP_AHB_RF_DMA_CHN2_GRP1_LSLP_EN 0x100
+#define MASK_AUD_CP_AHB_RF_AUD_DSP_CORE_FRC_SLEEP 0x80
+#define MASK_AUD_CP_AHB_RF_PMU_CPDMA_FRC_SLP 0x8
+#define MASK_AUD_CP_AHB_RF_PMU_APDMA_FRC_SLP 0x4
+#define MASK_AUD_CP_AHB_RF_AHB_ARCH_EB 0x1
+#define MASK_AUD_CP_AHB_RF_DSP_CORE_SLEEP 0x1
+#define MASK_AUD_CP_AHB_RF_DSP_SYS_SLEEP_EN 0x1
+#define MASK_AUD_CP_AHB_RF_MCACHE_STRAP_POST_NUM 0xf0
+#define MASK_AUD_CP_AHB_RF_MCACHE_STRAP_PRE_NUM 0xf
+#define MASK_AUD_CP_AHB_RF_MCU_STATUS 0xfff
+#define MASK_AUD_CP_AHB_RF_AUD_IIS2_EXT_SEL 0x4
+#define MASK_AUD_CP_AHB_RF_AUD_IIS1_EXT_SEL 0x2
+#define MASK_AUD_CP_AHB_RF_AUD_IIS0_EXT_SEL 0x1
+#define MASK_AUD_CP_AHB_RF_HIGH_RESERVED 0xffff0000
+#define MASK_AUD_CP_AHB_RF_LOW_RESERVED 0xffff
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S7 0x8000
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_ASYNC_BRIDGE 0x4000
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S6 0x2000
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S5 0x1000
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S4 0x800
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S3 0x400
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S2 0x200
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S1 0x100
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_S0 0x80
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_MAIN 0x40
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_M4 0x10
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_M3 0x8
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_M2 0x4
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_M1 0x2
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_EB_M0 0x1
+#define MASK_AUD_CP_AHB_RF_LP_AUD_CP_MTX_NUM 0xffff
+#define MASK_AUD_CP_AHB_RF_AWQOS_M0 0xf00000
+#define MASK_AUD_CP_AHB_RF_AWQOS_M1 0xf0000
+#define MASK_AUD_CP_AHB_RF_AWQOS_M2 0xf000
+#define MASK_AUD_CP_AHB_RF_AWQOS_M4 0xf0
+#define MASK_AUD_CP_AHB_RF_ARQOS_M0 0xf00000
+#define MASK_AUD_CP_AHB_RF_ARQOS_M1 0xf0000
+#define MASK_AUD_CP_AHB_RF_ARQOS_M2 0xf000
+#define MASK_AUD_CP_AHB_RF_ARQOS_M4 0xf0
+#define MASK_AUD_CP_AHB_RF_PERI_FRC_OFF 0x4
+#define MASK_AUD_CP_AHB_RF_PERI_FRC_ON 0x2
+#define MASK_AUD_CP_AHB_RF_SLAVE0_PUB0_FRC_DSLP 0x200
+#define MASK_AUD_CP_AHB_RF_DMA_CHN2_GRP2_FRC_DSLP 0x100
+#define MASK_AUD_CP_AHB_RF_DMA_CHN2_GRP1_FRC_DSLP 0x80
+#define MASK_AUD_CP_AHB_RF_MASTER4_PUB0_FRC_DSLP 0x10
+#define MASK_AUD_CP_AHB_RF_MASTER3_PUB0_FRC_DSLP 0x8
+#define MASK_AUD_CP_AHB_RF_MASTER2_PUB0_FRC_DSLP 0x4
+#define MASK_AUD_CP_AHB_RF_MASTER1_PUB0_FRC_DSLP 0x2
+#define MASK_AUD_CP_AHB_RF_MASTER0_PUB0_FRC_DSLP 0x1
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_DEBUG_SIGNAL_W 0xffffffff
+#define MASK_AUD_CP_AHB_RF_DMA_CP_PROT 0xf0
+#define MASK_AUD_CP_AHB_RF_DMA_AP_PROT 0xf
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_AXI_DETECTOR_OVERFLOW 0x2
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_TRANS_IDLE 0x1
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AF_LVL_AW_CH 0x38000000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AF_LVL_W_CH 0x7000000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AF_LVL_B_CH 0xe00000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AF_LVL_AR_CH 0x1c0000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AF_LVL_R_CH 0x38000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AE_LVL_AW_CH 0x7000
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AE_LVL_W_CH 0xe00
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AE_LVL_B_CH 0x1c0
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AE_LVL_AR_CH 0x38
+#define MASK_AUD_CP_AHB_RF_AUD_BRIDGE_FIFO_AE_LVL_R_CH 0x7
+#define MASK_AUD_CP_AHB_RF_ARCACHE_SRC_CFG 0xf00000
+#define MASK_AUD_CP_AHB_RF_AWCACHE_SRC_CFG 0xf0000
+#define MASK_AUD_CP_AHB_RF_ARCACHE_DMA_CP_CFG 0xf000
+#define MASK_AUD_CP_AHB_RF_AWCACHE_DMA_CP_CFG 0xf00
+#define MASK_AUD_CP_AHB_RF_ARCACHE_DMA_CFG 0xf0
+#define MASK_AUD_CP_AHB_RF_AWCACHE_DMA_CFG 0xf
+#define MASK_AUD_CP_AHB_RF_CEVA_PDMA_IACKN 0x2
+#define MASK_AUD_CP_AHB_RF_CEVA_DDMA_IACK 0x1
+#define MASK_AUD_CP_AHB_RF_TL42X_PSU_SYS_PSHTDWN_R 0x7fc000
+#define MASK_AUD_CP_AHB_RF_TL42X_PSU_PSHTDWN_R 0x3ff8
+#define MASK_AUD_CP_AHB_RF_TL42X_PSU_CORE_IDLE_R 0x4
+#define MASK_AUD_CP_AHB_RF_TL42X_PSU_DSP_IDLE_R 0x2
+#define MASK_AUD_CP_AHB_RF_TL42X_PSU_CORE_WAIT_R 0x1
+#define MASK_AUD_CP_AHB_RF_FORCE_DMA_CP_BUSY 0x2
+#define MASK_AUD_CP_AHB_RF_FORCE_DMA_AP_BUSY 0x1
+#define MASK_AUD_CP_AHB_RF_WAKEUP_EN_INT_H 0xffff
+#define MASK_AUD_CP_AHB_RF_WAKEUP_EN_INT_L 0xffffffff
+#define MASK_AUD_CP_AHB_RF_DSP_L2CC_ENDIAN 0x2
+#define MASK_AUD_CP_AHB_RF_DSP_L2CC_DBG_LIMIT 0x1
+#define MASK_AUD_CP_AHB_RF_ARQOS_THRESHOLD 0xf0
+#define MASK_AUD_CP_AHB_RF_AWQOS_THRESHOLD 0xf
+#define MASK_AUD_CP_AHB_RF_AUDCP_AUTO_FREQ_DE 0x800
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_FUNC_M4 0x400
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_FUNC_M2 0x200
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_FUNC_M0_1 0x100
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_FUNC_M0_0 0x80
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_MAIN 0x40
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_M4 0x20
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_M3 0x10
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_M2 0x8
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_M1 0x4
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_ON_MTX_M0 0x2
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_EB 0x1
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_FUNC_M4 0x200
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_FUNC_M2 0x100
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_FUNC_M0_1 0x80
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_FUNC_M0_0 0x40
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_MAIN 0x20
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_M4 0x10
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_M3 0x8
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_M2 0x4
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_M1 0x2
+#define MASK_AUD_CP_AHB_RF_AUTO_FREQ_DE_FRC_OFF_MTX_M0 0x1
+#define MASK_AUD_CP_AHB_RF_DBG_DUMMG_REG 0xffffffff
+#define MASK_AUD_CP_AHB_RF_CGM_DVFS_ROOT_AUTO_GATE_EN 0x1
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE7 0x1000000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE6 0x800000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE5 0x400000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE4 0x200000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE3 0x100000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE2 0x80000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE1 0x40000
+#define MASK_AUD_CP_AHB_RF_DISABLE_CGM_MASTER_2_SLAVE0 0x20000
+#define MASK_AUD_CP_AHB_RF_ASYNC_BRIDGE_AUTO_GATE_EN 0x10000
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S7_AUTO_GATE_EN 0x2000
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S6_AUTO_GATE_EN 0x1000
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S5_AUTO_GATE_EN 0x800
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S4_AUTO_GATE_EN 0x400
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S3_AUTO_GATE_EN 0x200
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S2_AUTO_GATE_EN 0x100
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S1_AUTO_GATE_EN 0x80
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_S0_AUTO_GATE_EN 0x40
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_MAIN_AUTO_GATE_EN 0x20
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_M4_AUTO_GATE_EN 0x10
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_M3_AUTO_GATE_EN 0x8
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_M2_AUTO_GATE_EN 0x4
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_M1_AUTO_GATE_EN 0x2
+#define MASK_AUD_CP_AHB_RF_CGM_MTX_M0_AUTO_GATE_EN 0x1
+#define MASK_AUD_CP_AHB_RF_DMAAP_SLAVE_2_AHB_BYPASS 0x8000
+#define MASK_AUD_CP_AHB_RF_DMACP_SLAVE_2_AHB_BYPASS 0x4000
+#define MASK_AUD_CP_AHB_RF_DVFS_2_AHB_BYPASS 0x2000
+#define MASK_AUD_CP_AHB_RF_PCLK_S4_EN_AUTO 0x1000
+#define MASK_AUD_CP_AHB_RF_DSP_CORE_CLK_EB 0x800
+#define MASK_AUD_CP_AHB_RF_DSP_APB_CLK_EB 0x400
+#define MASK_AUD_CP_AHB_RF_DSP_AHB_CLK_EB 0x200
+#define MASK_AUD_CP_AHB_RF_DSP_AXI_CLK_EB 0x100
+#define MASK_AUD_CP_AHB_RF_FRC_CLK_CORE_EN 0x80
+#define MASK_AUD_CP_AHB_RF_FRC_CLK_APB_EN 0x40
+#define MASK_AUD_CP_AHB_RF_FRC_CLK_AHB_EN 0x20
+#define MASK_AUD_CP_AHB_RF_FRC_CLK_AXI_EN 0x10
+#define MASK_AUD_CP_AHB_RF_CLK_CORE_AUTO_GATE_EN 0x8
+#define MASK_AUD_CP_AHB_RF_CLK_APB_AUTO_GATE_EN 0x4
+#define MASK_AUD_CP_AHB_RF_CLK_AHB_AUTO_GATE_EN 0x2
+#define MASK_AUD_CP_AHB_RF_CLK_AXI_AUTO_GATE_EN 0x1
+#define MASK_AUD_CP_AHB_RF_CSYSACK_SYNC_SEL_M1 0x8
+#define MASK_AUD_CP_AHB_RF_CACTIVE_SYNC_SEL_M1 0x4
+#define MASK_AUD_CP_AHB_RF_CSYSACK_SYNC_SEL_M0 0x2
+#define MASK_AUD_CP_AHB_RF_CACTIVE_SYNC_SEL_M0 0x1
+#define MASK_AUD_CP_AHB_RF_BUSMON_4_EB 0x8
+#define MASK_AUD_CP_AHB_RF_BUSMON_3_EB 0x4
+#define MASK_AUD_CP_AHB_RF_BUSMON_2_EB 0x2
+#define MASK_AUD_CP_AHB_RF_BUSMON_1_EB 0x1
+#define MASK_AUD_CP_AHB_RF_SYS_DBG_BUS 0xffffffff
+#define MASK_AUD_CP_AHB_RF_PU_NUM_M0 0xff000000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_M1 0xff0000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_M2 0xff00
+#define MASK_AUD_CP_AHB_RF_PU_NUM_M3 0xff
+#define MASK_AUD_CP_AHB_RF_PU_NUM_M4 0xff000000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_MAIN 0xff0000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S0 0xff00
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S1 0xff
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S2 0xff000000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S3 0xff0000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S4 0xff00
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S5 0xff
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S6 0xff0000
+#define MASK_AUD_CP_AHB_RF_PU_NUM_S7 0xff00
+#define MASK_AUD_CP_AHB_RF_PU_NUM_ASYNC_BRIDGE 0xff
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_HOLD 0x1
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_UP_WINDOW 0xffff0000
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_DOWN_WINDOW 0xffff
+#define MASK_MM_DVFS_AHB_RF_MM_DCAM_AXI_AUTO_TUNE_EN 0x80
+#define MASK_MM_DVFS_AHB_RF_FD_DFS_EN 0x40
+#define MASK_MM_DVFS_AHB_RF_DCAM_DFS_EN 0x20
+#define MASK_MM_DVFS_AHB_RF_JPG_DFS_EN 0x8
+#define MASK_MM_DVFS_AHB_RF_CPP_DFS_EN 0x4
+#define MASK_MM_DVFS_AHB_RF_ISP_DFS_EN 0x2
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_AUTO_TUNE_EN 0x1
+#define MASK_MM_DVFS_AHB_RF_FD_DFS_SW_TRIG 0x40
+#define MASK_MM_DVFS_AHB_RF_DCAM_DFS_SW_TRIG 0x20
+#define MASK_MM_DVFS_AHB_RF_JPG_DFS_SW_TRIG 0x8
+#define MASK_MM_DVFS_AHB_RF_CPP_DFS_SW_TRIG 0x4
+#define MASK_MM_DVFS_AHB_RF_ISP_DFS_SW_TRIG 0x2
+#define MASK_MM_DVFS_AHB_RF_MM_SYS_MIN_VOLTAGE 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_ACK 0x100
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_VOLTAGE_SW 0x70
+#define MASK_MM_DVFS_AHB_RF_MM_CURRENT_VOLTAGE_SW 0xe
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_REQ_SW 0x1
+#define MASK_MM_DVFS_AHB_RF_REG_FD_FREQ_UPD_EN_BYP 0x40
+#define MASK_MM_DVFS_AHB_RF_REG_DCAM_IF_FREQ_UPD_EN_BYP 0x20
+#define MASK_MM_DVFS_AHB_RF_REG_JPG_FREQ_UPD_EN_BYP 0x10
+#define MASK_MM_DVFS_AHB_RF_REG_CPP_FREQ_UPD_EN_BYP 0x8
+#define MASK_MM_DVFS_AHB_RF_REG_ISP_FREQ_UPD_EN_BYP 0x4
+#define MASK_MM_DVFS_AHB_RF_REG_MM_MTX_FREQ_UPD_EN_BYP 0x2
+#define MASK_MM_DVFS_AHB_RF_REG_DCAM_AXI_FREQ_UPD_EN_BYP 0x1
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_DVFS_FORCE_EN 0x2
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_DVFS_AUTO_GATE_SEL 0x1
+#define MASK_MM_DVFS_AHB_RF_MM_CURRENT_VOLTAGE 0x7000000
+#define MASK_MM_DVFS_AHB_RF_FD_VOLTAGE 0xe00000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOLTAGE 0x1c0000
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOLTAGE 0x38000
+#define MASK_MM_DVFS_AHB_RF_JPG_VOLTAGE 0x7000
+#define MASK_MM_DVFS_AHB_RF_CPP_VOLTAGE 0xe00
+#define MASK_MM_DVFS_AHB_RF_ISP_VOLTAGE 0x1c0
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOLTAGE 0x38
+#define MASK_MM_DVFS_AHB_RF_MM_INTERNAL_VOTE_VOLTAGE 0x7
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_DVFS 0x1800000
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_DVFS 0x780000
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_DVFS 0x78000
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_DVFS 0x7000
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_DVFS 0xc00
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_DVFS 0x300
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_DVFS 0xc0
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_DVFS 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_DVFS 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_BUSY 0x80000
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_WINDOW_CNT 0x7fff8
+#define MASK_MM_DVFS_AHB_RF_MM_DVFS_STATE 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX0 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX0 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX0 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX1 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX1 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX1 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX2 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX2 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX2 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX3 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX3 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX3 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX4 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX4 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX4 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX5 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX5 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX5 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX6 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX6 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX6 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_VOL_INDEX7 0x1c0
+#define MASK_MM_DVFS_AHB_RF_ISP_VOTE_MTX_INDEX7 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_ISP_SEL_INDEX7 0x7
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX0 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX0 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX0 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX1 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX1 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX1 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX2 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX2 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX2 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX3 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX3 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX3 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX4 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX4 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX4 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX5 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX5 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX5 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX6 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX6 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX6 0x3
+#define MASK_MM_DVFS_AHB_RF_JPG_VOL_INDEX7 0xe0
+#define MASK_MM_DVFS_AHB_RF_JPG_VOTE_MTX_INDEX7 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_JPG_SEL_INDEX7 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX0 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX0 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX0 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX1 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX1 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX1 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX2 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX2 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX2 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX3 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX3 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX3 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX4 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX4 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX4 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX5 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX5 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX5 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX6 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX6 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX6 0x3
+#define MASK_MM_DVFS_AHB_RF_CPP_VOL_INDEX7 0xe0
+#define MASK_MM_DVFS_AHB_RF_CPP_VOTE_MTX_INDEX7 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_CPP_SEL_INDEX7 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX0 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX0 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX0 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX0 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX0 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX1 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX1 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX1 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX1 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX1 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX2 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX2 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX2 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX2 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX2 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX3 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX3 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX3 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX3 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX3 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX4 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX4 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX4 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX4 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX4 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX5 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX5 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX5 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX5 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX5 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX6 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX6 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX6 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX6 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX6 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOTE_AXI_INDEX7 0x1c000
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_VOL_INDEX7 0x3800
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_DENOM_INDEX7 0x780
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_FDIV_NUM_INDEX7 0x78
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_IF_SEL_INDEX7 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX0 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX0 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX1 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX1 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX2 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX2 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX3 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX3 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX4 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX4 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX5 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX5 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX6 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX6 0x3
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_VOL_INDEX7 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_DCAM_AXI_SEL_INDEX7 0x3
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX0 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX0 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX1 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX1 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX2 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX2 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX3 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX3 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX4 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX4 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX5 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX5 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX6 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX6 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_VOL_INDEX7 0x38
+#define MASK_MM_DVFS_AHB_RF_CGM_MM_MTX_SEL_INDEX7 0x7
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX0 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX0 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX0 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX1 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX1 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX1 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX2 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX2 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX2 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX3 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX3 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX3 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX4 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX4 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX4 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX5 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX5 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX5 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX6 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX6 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX6 0x3
+#define MASK_MM_DVFS_AHB_RF_FD_VOL_INDEX7 0xe0
+#define MASK_MM_DVFS_AHB_RF_FD_VOTE_MTX_INDEX7 0x1c
+#define MASK_MM_DVFS_AHB_RF_CGM_FD_SEL_INDEX7 0x3
+#define MASK_MM_DVFS_AHB_RF_ISP_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_ISP_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_JPG_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_JPG_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_CPP_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_CPP_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_FD_DVFS_INDEX 0x7
+#define MASK_MM_DVFS_AHB_RF_FD_DVFS_INDEX_IDLE 0x7
+#define MASK_MM_DVFS_AHB_RF_FD_DVFS_FREQ_UPD_STATE 0xf000000
+#define MASK_MM_DVFS_AHB_RF_JPG_DVFS_FREQ_UPD_STATE 0xf00000
+#define MASK_MM_DVFS_AHB_RF_CPP_DVFS_FREQ_UPD_STATE 0xf0000
+#define MASK_MM_DVFS_AHB_RF_ISP_DVFS_FREQ_UPD_STATE 0xf000
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_DVFS_FREQ_UPD_STATE 0xf00
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_DVFS_FREQ_UPD_STATE 0xf0
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_DVFS_FREQ_UPD_STATE 0xf
+#define MASK_MM_DVFS_AHB_RF_ISP_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_MM_DVFS_AHB_RF_CPP_GFREE_WAIT_DELAY 0xffc00
+#define MASK_MM_DVFS_AHB_RF_JPG_GFREE_WAIT_DELAY 0x3ff
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_GFREE_WAIT_DELAY 0x3ff00000
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_GFREE_WAIT_DELAY 0xffc00
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_GFREE_WAIT_DELAY 0x3ff
+#define MASK_MM_DVFS_AHB_RF_FD_GFREE_WAIT_DELAY 0x3ff
+#define MASK_MM_DVFS_AHB_RF_FD_FREQ_UPD_DELAY_EN 0x2000
+#define MASK_MM_DVFS_AHB_RF_FD_FREQ_UPD_HDSK_EN 0x1000
+#define MASK_MM_DVFS_AHB_RF_ISP_FREQ_UPD_DELAY_EN 0x800
+#define MASK_MM_DVFS_AHB_RF_ISP_FREQ_UPD_HDSK_EN 0x400
+#define MASK_MM_DVFS_AHB_RF_CPP_FREQ_UPD_DELAY_EN 0x200
+#define MASK_MM_DVFS_AHB_RF_CPP_FREQ_UPD_HDSK_EN 0x100
+#define MASK_MM_DVFS_AHB_RF_JPG_FREQ_UPD_DELAY_EN 0x80
+#define MASK_MM_DVFS_AHB_RF_JPG_FREQ_UPD_HDSK_EN 0x40
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_FREQ_UPD_DELAY_EN 0x20
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_FREQ_UPD_HDSK_EN 0x10
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_FREQ_UPD_DELAY_EN 0x8
+#define MASK_MM_DVFS_AHB_RF_DCAM_AXI_FREQ_UPD_HDSK_EN 0x4
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_FREQ_UPD_DELAY_EN 0x2
+#define MASK_MM_DVFS_AHB_RF_DCAM_IF_FREQ_UPD_HDSK_EN 0x1
+#define MASK_MM_DVFS_AHB_RF_MM_MTX_DFS_IDLE_DISABLE 0x40
+#define MASK_MM_DVFS_AHB_RF_MM_FD_DFS_IDLE_DISABLE 0x20
+#define MASK_MM_DVFS_AHB_RF_MM_ISP_DFS_IDLE_DISABLE 0x10
+#define MASK_MM_DVFS_AHB_RF_MM_CPP_DFS_IDLE_DISABLE 0x8
+#define MASK_MM_DVFS_AHB_RF_MM_JPG_DFS_IDLE_DISABLE 0x4
+#define MASK_MM_DVFS_AHB_RF_MM_DCAM_AXI_DFS_IDLE_DISABLE 0x2
+#define MASK_MM_DVFS_AHB_RF_MM_DCAM_IF_DFS_IDLE_DISABLE 0x1
+#define MASK_MM_DVFS_AHB_RF_DVFS_RES_REG0 0xffffffff
+#define MASK_MM_DVFS_AHB_RF_DVFS_RES_REG1 0xffffffff
+#define MASK_MM_DVFS_AHB_RF_DVFS_RES_REG2 0xffffffff
+#define MASK_MM_DVFS_AHB_RF_DVFS_RES_REG3 0xffffffff
+#define MASK_AON_APB_ANA_EB 0x1000
+#define MASK_AON_APB_CGM_DPHY_REF_EN 0x400
+#define MASK_AON_APB_CGM_OTG_REF_EN 0x1000
+#define MASK_AON_APB_OTG_PHY_SOFT_RST 0x200
+#define MASK_AON_APB_OTG_UTMI_EB 0x100
+#define MASK_AON_APB_OTG_UTMI_SOFT_RST 0x100
+#define MASK_AON_APB_OTG_VBUS_VALID_PHYREG 0x1000000
+#define MASK_AON_APB_OTG_VBUS_VALID_PHYREG_SEL 0x800000
+#define MASK_AON_APB_USB2_PHY_IDDIG 0x8
+#define MASK_AON_APB_UTMI_WIDTH_SEL 0x40000000
+#define MASK_AON_APB_RF_SERDES_DPHY_REF_EB 0x100000
+#define MASK_AON_APB_RF_SERDES_DPHY_CFG_EB 0x80000
+#define MASK_AON_APB_RF_LVDIS_PLL_DIV_EN 0x40000
+#define MASK_AON_APB_RF_CSSYS_PUB_EB 0x20000
+#define MASK_AON_APB_RF_CSSYS_APB_EB 0x10000
+#define MASK_AON_APB_RF_CSSYS_EB 0x8000
+#define MASK_AON_APB_RF_APCPU_DAP_EB 0x4000
+#define MASK_AON_APB_RF_MSPI_EB 0x1000
+#define MASK_AON_APB_RF_GPU_EB 0x800
+#define MASK_AON_APB_RF_SP_AHB_CLK_SOFT_EB 0x400
+#define MASK_AON_APB_RF_MM_EB 0x200
+#define MASK_AON_APB_RF_PROBE_EB 0x80
+#define MASK_AON_APB_RF_AUX2_EB 0x40
+#define MASK_AON_APB_RF_AUX1_EB 0x20
+#define MASK_AON_APB_RF_AUX0_EB 0x10
+#define MASK_AON_APB_RF_DJTAG_EB 0x8
+#define MASK_AON_APB_RF_DJTAG_TCK_EB 0x4
+#define MASK_AON_APB_RF_RFTI_EB 0x2
+#define MASK_AON_APB_RF_RC100M_CAL_EB 0x1
+#define MASK_AON_APB_RF_SCC_EB 0x100000
+#define MASK_AON_APB_RF_AON_IIS_EB 0x80000
+#define MASK_AON_APB_RF_APB_BUSMON_EB 0x40000
+#define MASK_AON_APB_RF_APCPU_TS0_EB 0x20000
+#define MASK_AON_APB_RF_DJTAG_CTRL_EB 0x10000
+#define MASK_AON_APB_RF_CPALL_EIC_EB 0x8000
+#define MASK_AON_APB_RF_ETC_EB 0x4000
+#define MASK_AON_APB_RF_CKG_EB 0x2000
+#define MASK_AON_APB_RF_ANA_EB 0x1000
+#define MASK_AON_APB_RF_PIN_EB 0x800
+#define MASK_AON_APB_RF_SPLK_EB 0x400
+#define MASK_AON_APB_RF_OTG_UTMI_EB 0x100
+#define MASK_AON_APB_RF_DVFS_TOP_EB 0x80
+#define MASK_AON_APB_RF_AON_TMR_EB 0x40
+#define MASK_AON_APB_RF_AP_SYST_EB 0x20
+#define MASK_AON_APB_RF_AON_SYST_EB 0x10
+#define MASK_AON_APB_RF_KPD_EB 0x8
+#define MASK_AON_APB_RF_MBOX_EB 0x4
+#define MASK_AON_APB_RF_GPIO_EB 0x2
+#define MASK_AON_APB_RF_EFUSE_EB 0x1
+#define MASK_AON_APB_RF_SERDES_EB 0x80000000
+#define MASK_AON_APB_RF_APCPU_WDG_EB 0x40000000
+#define MASK_AON_APB_RF_AP_WDG_EB 0x20000000
+#define MASK_AON_APB_RF_PWM3_EB 0x10000000
+#define MASK_AON_APB_RF_PWM2_EB 0x8000000
+#define MASK_AON_APB_RF_PWM1_EB 0x4000000
+#define MASK_AON_APB_RF_PWM0_EB 0x2000000
+#define MASK_AON_APB_RF_AP_TMR2_EB 0x1000000
+#define MASK_AON_APB_RF_AP_TMR1_EB 0x800000
+#define MASK_AON_APB_RF_AP_TMR0_EB 0x400000
+#define MASK_AON_APB_RF_WTLCP_INTC_EB 0x200000
+#define MASK_AON_APB_RF_WTLCP_LDSP_INTC_EB 0x100000
+#define MASK_AON_APB_RF_WTLCP_TGDSP_INTC_EB 0x80000
+#define MASK_AON_APB_RF_PUBCP_INTC_EB 0x40000
+#define MASK_AON_APB_RF_AUDCP_INTC_EB 0x20000
+#define MASK_AON_APB_RF_AP_INTC5_EB 0x10000
+#define MASK_AON_APB_RF_AP_INTC4_EB 0x8000
+#define MASK_AON_APB_RF_AP_INTC3_EB 0x4000
+#define MASK_AON_APB_RF_AP_INTC2_EB 0x2000
+#define MASK_AON_APB_RF_AP_INTC1_EB 0x1000
+#define MASK_AON_APB_RF_AP_INTC0_EB 0x800
+#define MASK_AON_APB_RF_EIC_EB 0x400
+#define MASK_AON_APB_RF_ADI_EB 0x200
+#define MASK_AON_APB_RF_PMU_EB 0x100
+#define MASK_AON_APB_RF_I2C_EB 0x80
+#define MASK_AON_APB_RF_PUBCP_SIM2_AON_TOP_EB 0x40
+#define MASK_AON_APB_RF_PUBCP_SIM1_AON_TOP_EB 0x20
+#define MASK_AON_APB_RF_PUBCP_SIM0_AON_TOP_EB 0x10
+#define MASK_AON_APB_RF_AP_SIM_AON_TOP_EB 0x8
+#define MASK_AON_APB_RF_THM2_EB 0x4
+#define MASK_AON_APB_RF_THM1_EB 0x2
+#define MASK_AON_APB_RF_THM0_EB 0x1
+#define MASK_AON_APB_RF_PUBCP_SDIO0_SOFT_RST 0x4000
+#define MASK_AON_APB_RF_AP_SDIO2_SOFT_RST 0x2000
+#define MASK_AON_APB_RF_AP_SDIO1_SOFT_RST 0x1000
+#define MASK_AON_APB_RF_AP_SDIO0_SOFT_RST 0x800
+#define MASK_AON_APB_RF_AP_EMMC_SOFT_RST 0x400
+#define MASK_AON_APB_RF_SERDES_DPHY_APB_SOFT_RST 0x200
+#define MASK_AON_APB_RF_SERDES_DPHY_SOFT_RST 0x100
+#define MASK_AON_APB_RF_LVDSDIS_SOFT_RST 0x80
+#define MASK_AON_APB_RF_DAP_MTX_SOFT_RST 0x40
+#define MASK_AON_APB_RF_MSPI1_SOFT_RST 0x20
+#define MASK_AON_APB_RF_MSPI0_SOFT_RST 0x10
+#define MASK_AON_APB_RF_BB_CAL_SOFT_RST 0x8
+#define MASK_AON_APB_RF_DCXO_LC_SOFT_RST 0x4
+#define MASK_AON_APB_RF_RFTI_SOFT_RST 0x2
+#define MASK_AON_APB_RF_RC100M_CAL_SOFT_RST 0x1
+#define MASK_AON_APB_RF_SCC_SOFT_RST 0x100000
+#define MASK_AON_APB_RF_AON_IIS_SOFT_RST 0x80000
+#define MASK_AON_APB_RF_APB_BUSMON_SOFT_RST 0x40000
+#define MASK_AON_APB_RF_APCPU_TS0_SOFT_RST 0x20000
+#define MASK_AON_APB_RF_DJTAG_CTRL_SOFT_RST 0x10000
+#define MASK_AON_APB_RF_CPALL_EIC_SOFT_RST 0x8000
+#define MASK_AON_APB_RF_ETC_SOFT_RST 0x4000
+#define MASK_AON_APB_RF_CKG_SOFT_RST 0x2000
+#define MASK_AON_APB_RF_ANA_SOFT_RST 0x1000
+#define MASK_AON_APB_RF_PIN_SOFT_RST 0x800
+#define MASK_AON_APB_RF_SPLK_SOFT_RST 0x400
+#define MASK_AON_APB_RF_OTG_PHY_SOFT_RST 0x200
+#define MASK_AON_APB_RF_OTG_UTMI_SOFT_RST 0x100
+#define MASK_AON_APB_RF_DVFS_TOP_SOFT_RST 0x80
+#define MASK_AON_APB_RF_AON_TMR_SOFT_RST 0x40
+#define MASK_AON_APB_RF_AP_SYST_SOFT_RST 0x20
+#define MASK_AON_APB_RF_AON_SYST_SOFT_RST 0x10
+#define MASK_AON_APB_RF_KPD_SOFT_RST 0x8
+#define MASK_AON_APB_RF_MBOX_SOFT_RST 0x4
+#define MASK_AON_APB_RF_GPIO_SOFT_RST 0x2
+#define MASK_AON_APB_RF_EFUSE_SOFT_RST 0x1
+#define MASK_AON_APB_RF_SERDES_SOFT_RST 0x80000000
+#define MASK_AON_APB_RF_APCPU_WDG_SOFT_RST 0x40000000
+#define MASK_AON_APB_RF_AP_WDG_SOFT_RST 0x20000000
+#define MASK_AON_APB_RF_PWM3_SOFT_RST 0x10000000
+#define MASK_AON_APB_RF_PWM2_SOFT_RST 0x8000000
+#define MASK_AON_APB_RF_PWM1_SOFT_RST 0x4000000
+#define MASK_AON_APB_RF_PWM0_SOFT_RST 0x2000000
+#define MASK_AON_APB_RF_AP_TMR2_SOFT_RST 0x1000000
+#define MASK_AON_APB_RF_AP_TMR1_SOFT_RST 0x800000
+#define MASK_AON_APB_RF_AP_TMR0_SOFT_RST 0x400000
+#define MASK_AON_APB_RF_WTLCP_INTC_SOFT_RST 0x200000
+#define MASK_AON_APB_RF_WTLCP_LDSP_INTC_SOFT_RST 0x100000
+#define MASK_AON_APB_RF_WTLCP_TGDSP_INTC_SOFT_RST 0x80000
+#define MASK_AON_APB_RF_PUBCP_INTC_SOFT_RST 0x40000
+#define MASK_AON_APB_RF_AUDCP_INTC_SOFT_RST 0x20000
+#define MASK_AON_APB_RF_AP_INTC5_SOFT_RST 0x10000
+#define MASK_AON_APB_RF_AP_INTC4_SOFT_RST 0x8000
+#define MASK_AON_APB_RF_AP_INTC3_SOFT_RST 0x4000
+#define MASK_AON_APB_RF_AP_INTC2_SOFT_RST 0x2000
+#define MASK_AON_APB_RF_AP_INTC1_SOFT_RST 0x1000
+#define MASK_AON_APB_RF_AP_INTC0_SOFT_RST 0x800
+#define MASK_AON_APB_RF_EIC_SOFT_RST 0x400
+#define MASK_AON_APB_RF_ADI_SOFT_RST 0x200
+#define MASK_AON_APB_RF_PMU_SOFT_RST 0x100
+#define MASK_AON_APB_RF_I2C_SOFT_RST 0x80
+#define MASK_AON_APB_RF_PUBCP_SIM2_AON_TOP_SOFT_RST 0x40
+#define MASK_AON_APB_RF_PUBCP_SIM1_AON_TOP_SOFT_RST 0x20
+#define MASK_AON_APB_RF_PUBCP_SIM0_AON_TOP_SOFT_RST 0x10
+#define MASK_AON_APB_RF_AP_SIM_AON_TOP_SOFT_RST 0x8
+#define MASK_AON_APB_RF_THM2_SOFT_RST 0x4
+#define MASK_AON_APB_RF_THM1_SOFT_RST 0x2
+#define MASK_AON_APB_RF_THM0_SOFT_RST 0x1
+#define MASK_AON_APB_RF_PUBCP_SDIO0_RTC_EB 0x40000
+#define MASK_AON_APB_RF_AP_SDIO2_RTC_EB 0x20000
+#define MASK_AON_APB_RF_AP_SDIO1_RTC_EB 0x10000
+#define MASK_AON_APB_RF_AP_SDIO0_RTC_EB 0x8000
+#define MASK_AON_APB_RF_AP_EMMC_RTC_EB 0x4000
+#define MASK_AON_APB_RF_BB_CAL_RTC_EB 0x2000
+#define MASK_AON_APB_RF_DCXO_LC_RTC_EB 0x1000
+#define MASK_AON_APB_RF_AP_TMR2_RTC_EB 0x800
+#define MASK_AON_APB_RF_AP_TMR1_RTC_EB 0x400
+#define MASK_AON_APB_RF_AP_TMR0_RTC_EB 0x200
+#define MASK_AON_APB_RF_APCPU_WDG_RTC_EB 0x100
+#define MASK_AON_APB_RF_AP_WDG_RTC_EB 0x80
+#define MASK_AON_APB_RF_EIC_RTCDV5_EB 0x40
+#define MASK_AON_APB_RF_EIC_RTC_EB 0x20
+#define MASK_AON_APB_RF_AON_TMR_RTC_EB 0x10
+#define MASK_AON_APB_RF_AP_SYST_RTC_EB 0x8
+#define MASK_AON_APB_RF_AON_SYST_RTC_EB 0x4
+#define MASK_AON_APB_RF_KPD_RTC_EB 0x2
+#define MASK_AON_APB_RF_ARCH_RTC_EB 0x1
+#define MASK_AON_APB_RF_EFUSE_PWON_RD_END_FLAG 0x4
+#define MASK_AON_APB_RF_DBG_TRACE_CTRL_EN 0x10000
+#define MASK_AON_APB_RF_EVENTACK_RESTARTREQ_TS01 0x10
+#define MASK_AON_APB_RF_EVENT_RESTARTREQ_TS01 0x2
+#define MASK_AON_APB_RF_EVENT_HALTREQ_TS01 0x1
+#define MASK_AON_APB_RF_PTEST_FUNC_ATSPEED_SEL 0x100
+#define MASK_AON_APB_RF_PTEST_FUNC_MODE 0x80
+#define MASK_AON_APB_RF_FUNCTST_DMA_EB 0x40
+#define MASK_AON_APB_RF_PTEST_BIST_MODE 0x20
+#define MASK_AON_APB_RF_USB_DLOAD_EN 0x10
+#define MASK_AON_APB_RF_ARM_BOOT_MD3 0x8
+#define MASK_AON_APB_RF_ARM_BOOT_MD2 0x4
+#define MASK_AON_APB_RF_ARM_BOOT_MD1 0x2
+#define MASK_AON_APB_RF_ARM_BOOT_MD0 0x1
+#define MASK_AON_APB_RF_BB_BG_AUTO_PD_EN 0x8
+#define MASK_AON_APB_RF_BB_BG_SLP_PD_EN 0x4
+#define MASK_AON_APB_RF_BB_BG_FORCE_ON 0x2
+#define MASK_AON_APB_RF_BB_BG_FORCE_PD 0x1
+#define MASK_AON_APB_RF_AGCP_DSP_JTAG_MODE 0x8
+#define MASK_AON_APB_RF_CP_ARM_JTAG_PIN_SEL 0x7
+#define MASK_AON_APB_RF_DCXO_LC_FLAG 0x100
+#define MASK_AON_APB_RF_DCXO_LC_FLAG_CLR 0x2
+#define MASK_AON_APB_RF_DCXO_LC_CNT_CLR 0x1
+#define MASK_AON_APB_RF_DCXO_LC_CNT 0xffffffff
+#define MASK_AON_APB_RF_AUDCP_BOOTCTRL_PROT 0x80000000
+#define MASK_AON_APB_RF_AUDCP_REG_PROT_VAL 0xffff
+#define MASK_AON_APB_RF_LDSP_CTRL_PROT 0x80000000
+#define MASK_AON_APB_RF_REG_PROT_VAL 0xffff
+#define MASK_AON_APB_RF_CGM_AON_APB_LP_SEL 0x7
+#define MASK_AON_APB_RF_DAP_DBGPWRUP_SOFT_EN 0x4
+#define MASK_AON_APB_RF_DAP_SYSPWRUP_SOFT_EN 0x2
+#define MASK_AON_APB_RF_DAP_DJTAG_EN 0x1
+#define MASK_AON_APB_RF_USER_RSV_FLAG1_B1 0x2
+#define MASK_AON_APB_RF_USER_RSV_FLAG1_B0 0x1
+#define MASK_AON_APB_RF_CM4_SYS_SOFT_RST 0x10
+#define MASK_AON_APB_RF_CM4_CORE_SOFT_RST 0x1
+#define MASK_AON_APB_RF_MDAR_SYS_HSDL_CFG 0xffffffff
+#define MASK_AON_APB_RF_CGM_AP_AXI_APCPU_AUTO_GATE_SEL 0x80000000
+#define MASK_AON_APB_RF_CGM_AP_MM_AP_FORCE_EN 0x40000000
+#define MASK_AON_APB_RF_CGM_AP_MM_AP_AUTO_GATE_SEL 0x20000000
+#define MASK_AON_APB_RF_CGM_EMC_FORCE_EN 0x10000000
+#define MASK_AON_APB_RF_CGM_EMC_AUTO_GATE_SEL 0x8000000
+#define MASK_AON_APB_RF_CGM_MM_ISP_RAW_FORCE_EN 0x4000000
+#define MASK_AON_APB_RF_CGM_MM_ISP_RAW_AUTO_GATE_SEL 0x2000000
+#define MASK_AON_APB_RF_CGM_MM_ISP_YUV_FORCE_EN 0x1000000
+#define MASK_AON_APB_RF_CGM_MM_ISP_YUV_AUTO_GATE_SEL 0x800000
+#define MASK_AON_APB_RF_CGM_AON_APB_PUB_FORCE_EN 0x400000
+#define MASK_AON_APB_RF_CGM_AON_APB_PUB_AUTO_GATE_SEL 0x200000
+#define MASK_AON_APB_RF_CGM_AON_APB_AUDCP_FORCE_EN 0x100000
+#define MASK_AON_APB_RF_CGM_AON_APB_AUDCP_AUTO_GATE_SEL 0x80000
+#define MASK_AON_APB_RF_CGM_AON_APB_PUBCP_FORCE_EN 0x40000
+#define MASK_AON_APB_RF_CGM_AON_APB_PUBCP_AUTO_GATE_SEL 0x20000
+#define MASK_AON_APB_RF_CGM_AON_APB_WTLCP_FORCE_EN 0x10000
+#define MASK_AON_APB_RF_CGM_AON_APB_WTLCP_AUTO_GATE_SEL 0x8000
+#define MASK_AON_APB_RF_CGM_AON_APB_AP_FORCE_EN 0x4000
+#define MASK_AON_APB_RF_CGM_AON_APB_AP_AUTO_GATE_SEL 0x2000
+#define MASK_AON_APB_RF_CGM_AP_AXI_FORCE_EN 0x1000
+#define MASK_AON_APB_RF_CGM_AP_AXI_AUTO_GATE_SEL 0x800
+#define MASK_AON_APB_RF_CGM_AP_MM_ROOT_FORCE_EN 0x400
+#define MASK_AON_APB_RF_CGM_AP_MM_ROOT_AUTO_GATE_SEL 0x200
+#define MASK_AON_APB_RF_CGM_AP_MM_MM_FORCE_EN 0x100
+#define MASK_AON_APB_RF_CGM_AP_MM_MM_AUTO_GATE_SEL 0x80
+#define MASK_AON_APB_RF_CGM_AP_MM_GPU_FORCE_EN 0x40
+#define MASK_AON_APB_RF_CGM_AP_MM_GPU_AUTO_GATE_SEL 0x20
+#define MASK_AON_APB_RF_CGM_GPU_MEM_FORCE_EN 0x10
+#define MASK_AON_APB_RF_CGM_GPU_MEM_AUTO_GATE_SEL 0x8
+#define MASK_AON_APB_RF_CGM_APCPU_PMU_AUTO_GATE_SEL 0x4
+#define MASK_AON_APB_RF_CGM_APCPU_PMU_FORCE_EN 0x2
+#define MASK_AON_APB_RF_MBOX_AUTO_GATE_SEL 0x1
+#define MASK_AON_APB_RF_CGM_PUB_CLK_ANLG_IO_APB_EN 0x20
+#define MASK_AON_APB_RF_CGM_DMC_REF_AUTO_GATE_SEL 0x10
+#define MASK_AON_APB_RF_CGM_TOP_DVFS_ROOT_AUTO_GATE_SEL 0x8
+#define MASK_AON_APB_RF_CGM_TOP_DVFS_ROOT_FORCE_EN 0x4
+#define MASK_AON_APB_RF_CGM_AP_AXI_AUTO_FREQ_DOWN_CTRL_SEL 0x8
+#define MASK_AON_APB_RF_CGM_AP_AXI_AUTO_FREQ_DOWN_EN 0x4
+#define MASK_AON_APB_RF_CGM_AP_AXI_SEL_IDLE 0x3
+#define MASK_AON_APB_RF_AON_CHIP_ID0 0xffffffff
+#define MASK_AON_APB_RF_AON_CHIP_ID1 0xffffffff
+#define MASK_AON_APB_RF_AON_PLAT_ID0 0xffffffff
+#define MASK_AON_APB_RF_AON_PLAT_ID1 0xffffffff
+#define MASK_AON_APB_RF_AON_IMPL_ID 0xffffffff
+#define MASK_AON_APB_RF_AON_MFT_ID 0xffffffff
+#define MASK_AON_APB_RF_AON_VER_ID 0xffffffff
+#define MASK_AON_APB_RF_AON_CHIP_ID 0xffffffff
+#define MASK_AON_APB_RF_ANALOG_PLL_RSV 0xffff0000
+#define MASK_AON_APB_RF_ANALOG_TESTMUX 0xffff
+#define MASK_AON_APB_RF_PLL_BG_RSV 0x3f
+#define MASK_AON_APB_RF_LVDSDIS_LOG_SEL 0x6
+#define MASK_AON_APB_RF_LVDSDIS_DBG_SEL 0x1
+#define MASK_AON_APB_RF_CGM_WCDMA_ROOT_FORCE_EN 0x20
+#define MASK_AON_APB_RF_CGM_WCDMA_ROOT_AUTO_GATE_SEL 0x10
+#define MASK_AON_APB_RF_CGM_WCDMA_PUBCP_FORCE_EN 0x8
+#define MASK_AON_APB_RF_CGM_WCDMA_PUBCP_AUTO_GATE_SEL 0x4
+#define MASK_AON_APB_RF_CGM_WCDMA_WTLCP_FORCE_EN 0x2
+#define MASK_AON_APB_RF_CGM_WCDMA_WTLCP_AUTO_GATE_SEL 0x1
+#define MASK_AON_APB_RF_CGM_PERIPH_AUTO_GATE_EN 0x2000
+#define MASK_AON_APB_RF_CGM_GIC_AUTO_GATE_EN 0x1000
+#define MASK_AON_APB_RF_CGM_ACP_AUTO_GATE_EN 0x800
+#define MASK_AON_APB_RF_CGM_AXI_PERIPH_AUTO_GATE_EN 0x400
+#define MASK_AON_APB_RF_CGM_ACE_AUTO_GATE_EN 0x200
+#define MASK_AON_APB_RF_CGM_SCU_AUTO_GATE_EN 0x100
+#define MASK_AON_APB_RF_CGM_CORE7_AUTO_GATE_EN 0x80
+#define MASK_AON_APB_RF_CGM_CORE6_AUTO_GATE_EN 0x40
+#define MASK_AON_APB_RF_CGM_CORE5_AUTO_GATE_EN 0x20
+#define MASK_AON_APB_RF_CGM_CORE4_AUTO_GATE_EN 0x10
+#define MASK_AON_APB_RF_CGM_CORE3_AUTO_GATE_EN 0x8
+#define MASK_AON_APB_RF_CGM_CORE2_AUTO_GATE_EN 0x4
+#define MASK_AON_APB_RF_CGM_CORE1_AUTO_GATE_EN 0x2
+#define MASK_AON_APB_RF_CGM_CORE0_AUTO_GATE_EN 0x1
+#define MASK_AON_APB_RF_APCPU_CORE_WAKEUP_ACE_CLK_EN 0x2
+#define MASK_AON_APB_RF_APCPU_CORE_WAKEUP_SCU_CLK_EN 0x1
+#define MASK_AON_APB_RF_SP_AHB_CLK_SOFT_EN 0x80
+#define MASK_AON_APB_RF_CM4_SLEEPING_STAT 0x40
+#define MASK_AON_APB_RF_CM4_LOCKUP_STAT 0x20
+#define MASK_AON_APB_RF_CM4_SOFT_MPUDIS 0x10
+#define MASK_AON_APB_RF_MMTX_SLEEP_CM4_PUB_WR 0x8
+#define MASK_AON_APB_RF_MMTX_SLEEP_CM4_PUB_RD 0x4
+#define MASK_AON_APB_RF_INT_REQ_CM4_SOFT 0x2
+#define MASK_AON_APB_RF_SP_CFG_BUS_SLEEP 0x1
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_RESET_BAR 0x2000
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_DORMANT 0x1000
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_SEC_BIST_STRT 0x800
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_PVDDOFFB_AON 0x400
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_AVDDOFFB_AON 0x200
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_AVDDISOB_AON 0x100
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_DVDDOFFB_AON 0x80
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_DVDDISOB_AON 0x40
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_POR_ISOB_AON 0x20
+#define MASK_AON_APB_RF_R2G_ANALOG_ETEK_ET8212_POR_ISO_AON 0x10
+#define MASK_AON_APB_RF_G2R_ANALOG_ETEK_ET8212_ALARM_TOGGLE_INT 0x8
+#define MASK_AON_APB_RF_G2R_ANALOG_ETEK_ET8212_ATCLIM_TOGGLE_INT 0x4
+#define MASK_AON_APB_RF_G2R_ANALOG_ETEK_ET8212_SEC_BIST_DONE 0x2
+#define MASK_AON_APB_RF_G2R_ANALOG_ETEK_ET8212_SEC_BIST_PASS 0x1
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_RESET_BAR 0x200
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_DORMANT 0x100
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_SEC_BIST_STRT 0x80
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_PVDDOFFB_AON 0x40
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_AVDDOFFB_AON 0x20
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_AVDDISOB_AON 0x10
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_DVDDOFFB_AON 0x8
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_DVDDISOB_AON 0x4
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_POR_ISOB_AON 0x2
+#define MASK_AON_APB_RF_DBG_SEL_ANALOG_ETEK_ET8212_POR_ISO_AON 0x1
+#define MASK_AON_APB_RF_DJTAG_SOFT_RST 0x400
+#define MASK_AON_APB_RF_DJTAG_PUB0_SOFT_RST 0x200
+#define MASK_AON_APB_RF_DJTAG_AON_SOFT_RST 0x100
+#define MASK_AON_APB_RF_DJTAG_AUDCP_SOFT_RST 0x80
+#define MASK_AON_APB_RF_DJTAG_WTLCP_SOFT_RST 0x40
+#define MASK_AON_APB_RF_DJTAG_PUBCP_SOFT_RST 0x20
+#define MASK_AON_APB_RF_DJTAG_MM_SOFT_RST 0x10
+#define MASK_AON_APB_RF_DJTAG_CDMA2K_SOFT_RST 0x8
+#define MASK_AON_APB_RF_DJTAG_GPU_SOFT_RST 0x4
+#define MASK_AON_APB_RF_DJTAG_APCPU_SOFT_RST 0x2
+#define MASK_AON_APB_RF_DJTAG_AP_SOFT_RST 0x1
+#define MASK_AON_APB_RF_RF_RTC_CAL_CTL 0x1fc00000
+#define MASK_AON_APB_RF_RF_RTC_CAL_SEL 0x200000
+#define MASK_AON_APB_RF_RF_RTC_CAL_PRECISION 0x1fe000
+#define MASK_AON_APB_RF_RC100M_DIV 0x1f80
+#define MASK_AON_APB_RF_RC100M_CAL_DONE 0x40
+#define MASK_AON_APB_RF_RC100M_CAL_START 0x20
+#define MASK_AON_APB_RF_RC100M_ANA_SOFT_RST 0x10
+#define MASK_AON_APB_RF_RC100M_FORCE_EN 0x2
+#define MASK_AON_APB_RF_RC100M_AUTO_GATE_EN 0x1
+#define MASK_AON_APB_RF_LTE_PCCSCC_RFTI_CLK_SW_CFG 0xff000000
+#define MASK_AON_APB_RF_CGM_LPLL1_WTLCP_SEL 0x200000
+#define MASK_AON_APB_RF_CGM_LPLL0_WTLCP_SEL 0x100000
+#define MASK_AON_APB_RF_CGM_CM4_TMR2_EN 0x80000
+#define MASK_AON_APB_RF_DET_32K_EB 0x40000
+#define MASK_AON_APB_RF_CGM_DEBOUNCE_EN 0x20000
+#define MASK_AON_APB_RF_CGM_RC100M_FDK_EN 0x10000
+#define MASK_AON_APB_RF_CGM_RC100M_REF_EN 0x8000
+#define MASK_AON_APB_RF_CGM_TMR_EN 0x4000
+#define MASK_AON_APB_RF_CGM_TSEN_EN 0x2000
+#define MASK_AON_APB_RF_CGM_OTG_REF_EN 0x1000
+#define MASK_AON_APB_RF_CGM_DMC_REF_EN 0x800
+#define MASK_AON_APB_RF_CGM_DPHY_REF_EN 0x400
+#define MASK_AON_APB_RF_CGM_DJTAG_TCK_EN 0x200
+#define MASK_AON_APB_RF_CGM_DSI_CSI_TEST_EB 0x100
+#define MASK_AON_APB_RF_CGM_MDAR_CHK_EN 0x80
+#define MASK_AON_APB_RF_CGM_LVDSRF_CALI_EN 0x20
+#define MASK_AON_APB_RF_CGM_RFTI2_XO_EN 0x8
+#define MASK_AON_APB_RF_CGM_RFTI1_XO_EN 0x2
+#define MASK_AON_APB_RF_CGM_RFTI_SBI_EN 0x1
+#define MASK_AON_APB_RF_SOFT_DDR0_CKG_1X_EN 0x4000000
+#define MASK_AON_APB_RF_SOFT_DDR0_DATA_RET 0x800000
+#define MASK_AON_APB_RF_LIGHT_SLEEP_DDR0_DATA_RET_EN 0x200000
+#define MASK_AON_APB_RF_EMC0_CKG_SEL_LOAD 0x80000
+#define MASK_AON_APB_RF_CLK_DEBUG_TS_EB 0x40000
+#define MASK_AON_APB_RF_AAPC_CLK_TEST_EB 0x10000
+#define MASK_AON_APB_RF_CGM_CPHY_CFG_EN 0x8000
+#define MASK_AON_APB_RF_ALL_PLL_TEST_EB 0x4000
+#define MASK_AON_APB_RF_CGM_WCDMA_ICI_EN 0x2000
+#define MASK_AON_APB_RF_CGM_RFTI_RX_WD_EN 0x1000
+#define MASK_AON_APB_RF_CGM_RFTI_TX_WD_EN 0x800
+#define MASK_AON_APB_RF_CGM_WCDMA_EN 0x400
+#define MASK_AON_APB_RF_CGM_EMMC_2X_EN 0x200
+#define MASK_AON_APB_RF_CGM_EMMC_1X_EN 0x100
+#define MASK_AON_APB_RF_CGM_SDIO2_1X_EN 0x80
+#define MASK_AON_APB_RF_CGM_SDIO2_2X_EN 0x40
+#define MASK_AON_APB_RF_CGM_SDIO1_1X_EN 0x20
+#define MASK_AON_APB_RF_CGM_SDIO1_2X_EN 0x10
+#define MASK_AON_APB_RF_CGM_SDIO0_1X_EN 0x8
+#define MASK_AON_APB_RF_CGM_SDIO0_2X_EN 0x4
+#define MASK_AON_APB_RF_CGM_AP_AXI_EN 0x2
+#define MASK_AON_APB_RF_CGM_CSSYS_EN 0x1
+#define MASK_AON_APB_RF_AUDCP_DSP_BOOT_VECTOR 0xffffffff
+#define MASK_AON_APB_RF_AUDCP_STCK_DSP 0x2000
+#define MASK_AON_APB_RF_AUDCP_STMS_DSP 0x1000
+#define MASK_AON_APB_RF_AUDCP_STDO_DSP 0x800
+#define MASK_AON_APB_RF_AUDCP_STDI_DSP 0x400
+#define MASK_AON_APB_RF_AUDCP_STRTCK_DSP 0x200
+#define MASK_AON_APB_RF_AUDCP_SW_JTAG_ENA_DSP 0x100
+#define MASK_AON_APB_RF_AUDCP_DSP_EXTERNAL_WAIT 0x2
+#define MASK_AON_APB_RF_AUDCP_DSP_BOOT 0x1
+#define MASK_AON_APB_RF_CM4_2_AUD_ACCESS_EN 0x40
+#define MASK_AON_APB_RF_AP_2_AUD_ACCESS_EN 0x20
+#define MASK_AON_APB_RF_CR5_2_AUD_ACCESS_EN 0x10
+#define MASK_AON_APB_RF_LDSP_2_AUD_ACCESS_EN 0x8
+#define MASK_AON_APB_RF_TGDSP_2_AUD_ACCESS_EN 0x4
+#define MASK_AON_APB_RF_AUDCP_FRC_CLK_DSP_EN 0x2
+#define MASK_AON_APB_RF_TOP_2_AUD_ACCESS_EN 0x1
+#define MASK_AON_APB_RF_WTLCP_LDSP_BOOT_VECTOR 0xffffffff
+#define MASK_AON_APB_RF_WTLCP_STCK_LDSP 0x2000
+#define MASK_AON_APB_RF_WTLCP_STMS_LDSP 0x1000
+#define MASK_AON_APB_RF_WTLCP_STDO_LDSP 0x800
+#define MASK_AON_APB_RF_WTLCP_STDI_LDSP 0x400
+#define MASK_AON_APB_RF_WTLCP_STRTCK_LDSP 0x200
+#define MASK_AON_APB_RF_WTLCP_SW_JTAG_ENA_LDSP 0x100
+#define MASK_AON_APB_RF_WTLCP_LDSP_EXTERNAL_WAIT 0x2
+#define MASK_AON_APB_RF_WTLCP_LDSP_BOOT 0x1
+#define MASK_AON_APB_RF_WTLCP_TDSP_BOOT_VECTOR 0xffffffff
+#define MASK_AON_APB_RF_WTLCP_STCK_TDSP 0x2000
+#define MASK_AON_APB_RF_WTLCP_STMS_TDSP 0x1000
+#define MASK_AON_APB_RF_WTLCP_STDO_TDSP 0x800
+#define MASK_AON_APB_RF_WTLCP_STDI_TDSP 0x400
+#define MASK_AON_APB_RF_WTLCP_STRTCK_TDSP 0x200
+#define MASK_AON_APB_RF_WTLCP_SW_JTAG_ENA_TDSP 0x100
+#define MASK_AON_APB_RF_WTLCP_TDSP_EXTERNAL_WAIT 0x2
+#define MASK_AON_APB_RF_WTLCP_TDSP_BOOT 0x1
+#define MASK_AON_APB_RF_WTLCP_EIC_SOFT_RST 0x100
+#define MASK_AON_APB_RF_WTLCP_EIC_EB 0x80
+#define MASK_AON_APB_RF_WTLCP_EIC_RTCDV5_EB 0x40
+#define MASK_AON_APB_RF_WTLCP_EIC_RTC_EB 0x20
+#define MASK_AON_APB_RF_WTLCP_AON_FRC_WSYS_LT_STOP 0x10
+#define MASK_AON_APB_RF_WTLCP_AON_FRC_WSYS_STOP 0x8
+#define MASK_AON_APB_RF_WTLCP_DSP_DEEP_SLEEP_EN 0x4
+#define MASK_AON_APB_RF_WTLCP_WCMDA_EB 0x10000
+#define MASK_AON_APB_RF_WCDMA_AUTO_GATE_EN 0x100
+#define MASK_AON_APB_RF_WTLCP_WTLSYS_RFTI_TX_EB 0x2
+#define MASK_AON_APB_RF_WTLCP_WTLSYS_RFTI_RX_EB 0x1
+#define MASK_AON_APB_RF_PUBCP_SYST_RTC_EB 0x800
+#define MASK_AON_APB_RF_PUBCP_TMR_EB 0x400
+#define MASK_AON_APB_RF_PUBCP_TMR_RTC_EB 0x200
+#define MASK_AON_APB_RF_PUBCP_SYST_EB 0x100
+#define MASK_AON_APB_RF_PUBCP_WDG_EB 0x80
+#define MASK_AON_APB_RF_PUBCP_WDG_RTC_EB 0x40
+#define MASK_AON_APB_RF_PUBCP_ARCH_RTC_EB 0x20
+#define MASK_AON_APB_RF_PUBCP_EIC_EB 0x10
+#define MASK_AON_APB_RF_PUBCP_EIC_RTCDV5_EB 0x8
+#define MASK_AON_APB_RF_PUBCP_EIC_RTC_EB 0x4
+#define MASK_AON_APB_RF_PUBCP_CR5_CORE_SOFT_RST 0x400
+#define MASK_AON_APB_RF_PUBCP_CR5_DBG_SOFT_RST 0x200
+#define MASK_AON_APB_RF_PUBCP_CR5_ETM_SOFT_RST 0x100
+#define MASK_AON_APB_RF_PUBCP_CR5_MP_SOFT_RST 0x80
+#define MASK_AON_APB_RF_PUBCP_CR5_CS_DBG_SOFT_RST 0x40
+#define MASK_AON_APB_RF_PUBCP_TMR_SOFT_RST 0x20
+#define MASK_AON_APB_RF_PUBCP_SYST_SOFT_RST 0x10
+#define MASK_AON_APB_RF_PUBCP_WDG_SOFT_RST 0x8
+#define MASK_AON_APB_RF_PUBCP_EIC_SOFT_RST 0x4
+#define MASK_AON_APB_RF_AON_ACCESS_PUBCP 0x2000
+#define MASK_AON_APB_RF_PUBCP_CR5_STANDBYWFI_N 0x1000
+#define MASK_AON_APB_RF_PUBCP_CR5_STANDBYWFE_N 0x800
+#define MASK_AON_APB_RF_PUBCP_CR5_CLKSTOPPED0_N 0x400
+#define MASK_AON_APB_RF_PUBCP_CR5_L2IDLE 0x200
+#define MASK_AON_APB_RF_PUBCP_CR5_VALIRQ0_N 0x100
+#define MASK_AON_APB_RF_PUBCP_CR5_VALFIQ0_N 0x80
+#define MASK_AON_APB_RF_PUBCP_CR5_STOP 0x40
+#define MASK_AON_APB_RF_PUBCP_CR5_CSYSACK_ATB 0x20
+#define MASK_AON_APB_RF_PUBCP_CR5_CACTIVE_ATB 0x10
+#define MASK_AON_APB_RF_PUBCP_CR5_CSSYNC_REQ 0x8
+#define MASK_AON_APB_RF_PUBCP_CR5_CSYSREQ_ATB 0x4
+#define MASK_AON_APB_RF_PUBCP_CR5_NODBGCLK 0x2
+#define MASK_AON_APB_RF_PUBCP_CR5_CFGEE 0x1
+#define MASK_AON_APB_RF_WTLCP_FRC_STOP_ACK 0x100
+#define MASK_AON_APB_RF_WTLCP_FRC_STOP_REQ 0x1
+#define MASK_AON_APB_RF_PUBCP_FRC_STOP_ACK 0x100
+#define MASK_AON_APB_RF_PUBCP_FRC_STOP_REQ 0x1
+#define MASK_AON_APB_RF_USB_BUSCLK_SEL_SOC 0x4
+#define MASK_AON_APB_RF_USB_DIVN_MUX_SEL 0x2
+#define MASK_AON_APB_RF_AON_IIS_SEL 0x1
+#define MASK_AON_APB_RF_BSMTMR_SOFT_RST 0x80
+#define MASK_AON_APB_RF_RFTI2_LTH_SOFT_RST 0x40
+#define MASK_AON_APB_RF_RFTI1_LTH_SOFT_RST 0x20
+#define MASK_AON_APB_RF_CSSYS_SOFT_RST 0x10
+#define MASK_AON_APB_RF_RFTI_SBI_SOFT_RST 0x2
+#define MASK_AON_APB_RF_LVDSRF_CALI_SOFT_RST 0x1
+#define MASK_AON_APB_RF_INT_REQ_DCAM2_ARM_STAT 0x200
+#define MASK_AON_APB_RF_INT_REQ_DCAM1_ARM_STAT 0x100
+#define MASK_AON_APB_RF_INT_REQ_DCAM0_ARM_STAT 0x80
+#define MASK_AON_APB_RF_INT_REQ_ISP_CH1_STAT 0x40
+#define MASK_AON_APB_RF_INT_REQ_ISP_CH0_STAT 0x20
+#define MASK_AON_APB_RF_INT_REQ_DCAM2_ARM_MASK 0x10
+#define MASK_AON_APB_RF_INT_REQ_DCAM1_ARM_MASK 0x8
+#define MASK_AON_APB_RF_INT_REQ_DCAM0_ARM_MASK 0x4
+#define MASK_AON_APB_RF_INT_REQ_ISP_CH1_MASK 0x2
+#define MASK_AON_APB_RF_INT_REQ_ISP_CH0_MASK 0x1
+#define MASK_AON_APB_RF_BSM_TMR_EB 0x2
+#define MASK_AON_APB_RF_DBGSYS_CSSYS_STM_NSGUAREN 0x10000
+#define MASK_AON_APB_RF_DJTAG_SRC_MUX_SEL 0x1
+#define MASK_AON_APB_RF_FUSEBOX_SELECT_BUFFER_SW 0x8
+#define MASK_AON_APB_RF_EFUSE_MUX_SEL_SW_DEFUALT0 0x4
+#define MASK_AON_APB_RF_EFUSE_MUX_SEL_SW_DEFUALT1 0x2
+#define MASK_AON_APB_RF_EFUSE_MUX_SEL_SW 0x1
+#define MASK_AON_APB_RF_OTG_TXPREEMPPULSETUNE 0x100000
+#define MASK_AON_APB_RF_OTG_TXRESTUNE 0xc0000
+#define MASK_AON_APB_RF_OTG_TXHSXVTUNE 0x30000
+#define MASK_AON_APB_RF_OTG_TXVREFTUNE 0xf000
+#define MASK_AON_APB_RF_OTG_TXPREEMPAMPTUNE 0xc00
+#define MASK_AON_APB_RF_OTG_TXRISETUNE 0x300
+#define MASK_AON_APB_RF_OTG_TXFSLSTUNE 0xf0
+#define MASK_AON_APB_RF_OTG_SQRXTUNE 0x7
+#define MASK_AON_APB_RF_OTG_ATERESET 0x80000000
+#define MASK_AON_APB_RF_OTG_VBUS_VALID_PHYREG 0x1000000
+#define MASK_AON_APB_RF_OTG_VBUS_VALID_PHYREG_SEL 0x800000
+#define MASK_AON_APB_RF_OTG_TESTBURNIN 0x200000
+#define MASK_AON_APB_RF_OTG_LOOPBACKENB 0x100000
+#define MASK_AON_APB_RF_OTG_TESTDATAOUT 0xf0000
+#define MASK_AON_APB_RF_OTG_VATESTENB 0xc000
+#define MASK_AON_APB_RF_USB2_CON_TESTMODE 0x80000000
+#define MASK_AON_APB_RF_UTMI_WIDTH_SEL 0x40000000
+#define MASK_AON_APB_RF_OTG_SS_SCALEDOWNMODE 0x6000000
+#define MASK_AON_APB_RF_OTG_DMPULLDOWN 0x200000
+#define MASK_AON_APB_RF_OTG_DPPULLDOWN 0x100000
+#define MASK_AON_APB_RF_OTG_COMMONONN 0x100
+#define MASK_AON_APB_RF_USB2_PHY_IDDIG 0x8
+#define MASK_AON_APB_RF_OTG_FSEL 0x7
+#define MASK_AON_APB_RF_USB20_SAMPLER_SEL 0x100000
+#define MASK_AON_APB_RF_HSIC_PLLON 0x10000
+#define MASK_AON_APB_RF_USB20_S_ID 0x4000
+#define MASK_AON_APB_RF_USB_REF_CLK_MUX_SEL 0x1
+#define MASK_AON_APB_RF_THM0_CALI_RSVD 0xff
+#define MASK_AON_APB_RF_THM1_CALI_RSVD 0xff
+#define MASK_AON_APB_RF_THM2_CALI_RSVD 0xff
+#define MASK_AON_APB_RF_THM2_INT_ADIE_EN 0x400
+#define MASK_AON_APB_RF_THM1_INT_ADIE_EN 0x200
+#define MASK_AON_APB_RF_THM0_INT_ADIE_EN 0x100
+#define MASK_AON_APB_RF_THM2_OVERHEAT_ALARM_ADIE_EN 0x40
+#define MASK_AON_APB_RF_THM1_OVERHEAT_ALARM_ADIE_EN 0x20
+#define MASK_AON_APB_RF_THM0_OVERHEAT_ALARM_ADIE_EN 0x10
+#define MASK_AON_APB_RF_THM2_OVERHEAT_RST_DDIE_EN 0x4
+#define MASK_AON_APB_RF_THM1_OVERHEAT_RST_DDIE_EN 0x2
+#define MASK_AON_APB_RF_THM0_OVERHEAT_RST_DDIE_EN 0x1
+#define MASK_AON_APB_RF_CP_SIM1_CLK_PL 0x20
+#define MASK_AON_APB_RF_CP_SIM1_DETECT_EN 0x10
+#define MASK_AON_APB_RF_CP_BAT1_DETECT_EN 0x8
+#define MASK_AON_APB_RF_CP_SIM1_DETECT_POL 0x4
+#define MASK_AON_APB_RF_CP_BAT1_DETECT_POL 0x2
+#define MASK_AON_APB_RF_CP_SIM1_OFF_PD_EN 0x1
+#define MASK_AON_APB_RF_CP_SIM2_CLK_PL 0x20
+#define MASK_AON_APB_RF_CP_SIM2_DETECT_EN 0x10
+#define MASK_AON_APB_RF_CP_BAT2_DETECT_EN 0x8
+#define MASK_AON_APB_RF_CP_SIM2_DETECT_POL 0x4
+#define MASK_AON_APB_RF_CP_BAT2_DETECT_POL 0x2
+#define MASK_AON_APB_RF_CP_SIM2_OFF_PD_EN 0x1
+#define MASK_AON_APB_RF_CP_SIM3_CLK_PL 0x20
+#define MASK_AON_APB_RF_CP_SIM3_DETECT_EN 0x10
+#define MASK_AON_APB_RF_CP_BAT3_DETECT_EN 0x8
+#define MASK_AON_APB_RF_CP_SIM3_DETECT_POL 0x4
+#define MASK_AON_APB_RF_CP_BAT3_DETECT_POL 0x2
+#define MASK_AON_APB_RF_CP_SIM3_OFF_PD_EN 0x1
+#define MASK_AON_APB_RF_AP_SIM_CLK_PL 0x20
+#define MASK_AON_APB_RF_AP_SIM_DETECT_EN 0x10
+#define MASK_AON_APB_RF_AP_BAT_DETECT_EN 0x8
+#define MASK_AON_APB_RF_AP_SIM_DETECT_POL 0x4
+#define MASK_AON_APB_RF_AP_BAT_DETECT_POL 0x2
+#define MASK_AON_APB_RF_AP_SIM_OFF_PD_EN 0x1
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M3 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M2 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M1 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M0 0xff
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_MAIN 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M6 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M5 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_M4 0xff
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S3 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S2 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S1 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S0 0xff
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S7 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S6 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S5 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S4 0xff
+#define MASK_AON_APB_RF_PU_NUM_AXI_CM4_TO_AON 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AON2DDR_ASYNC_BRIDGE_W 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S9 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AON_MTX_S8 0xff
+#define MASK_AON_APB_RF_PU_NUM_WCDMA_REGSLICE 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_APCPU_AP_REGSLICE 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AP_MM_REGSLICE 0xff00
+#define MASK_AON_APB_RF_PU_NUM_AP_GPU_REGSLICE 0xff
+#define MASK_AON_APB_RF_PU_NUM_ISP2DDR_REGSLICE 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_AP2DDR_REGSLICE 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_DPU2DDR_REGSLICE 0xff00
+#define MASK_AON_APB_RF_PU_NUM_GPU2DDR_REGSLICE 0xff
+#define MASK_AON_APB_RF_PU_NUM_PUBCP2WTLCP_REGSLICE 0xff000000
+#define MASK_AON_APB_RF_PU_NUM_APCPU2DDR_REGSLICE 0xff0000
+#define MASK_AON_APB_RF_PU_NUM_AUDCP2DDR_REGSLICE 0xff00
+#define MASK_AON_APB_RF_PU_NUM_DCAM2DDR_REGSLICE 0xff
+#define MASK_AON_APB_RF_PU_NUM_VDSP2DDR_REGSLICE 0xff00
+#define MASK_AON_APB_RF_PU_NUM_PUBCP2WTL_ASYNC_BRIDGE 0xff
+#define MASK_AON_APB_RF_MONITOR_GATE_AUTO_EN_STATUS 0xf0
+#define MASK_AON_APB_RF_MONITOR_WAIT_EN_STATUS 0xf
+#define MASK_AON_APB_RF_APCPU_LP_NUM_DEBUG_PWR 0x1fffe
+#define MASK_AON_APB_RF_APCPU_LP_EB_DEBUG_PWR 0x1
+#define MASK_AON_APB_RF_APCPU_LP_NUM_GIC_COL 0x1fffe
+#define MASK_AON_APB_RF_APCPU_LP_EB_GIC_COL 0x1
+#define MASK_AON_APB_RF_APCPU_CLUSTER_ATB_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_CLUSTER_ATB_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_CLUSTER_APB_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_CLUSTER_APB_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_CLUSTER_GIC_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_CLUSTER_GIC_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_GIC600_GIC_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_GIC600_GIC_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_DBG_BLK_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_DBG_BLK_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_LP_NUM 0x1fffe00
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_MIAN_LP_EB 0x100
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_S3_LP_EB 0x80
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_S2_LP_EB 0x40
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_S1_LP_EB 0x20
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_S0_LP_EB 0x10
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_M3_LP_EB 0x8
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_M2_LP_EB 0x4
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_M1_LP_EB 0x2
+#define MASK_AON_APB_RF_APCPU_TOP_MTX_M0_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_ACE_PU_NUM 0xff00
+#define MASK_AON_APB_RF_APCPU_MTX_PU_NUM 0xff
+#define MASK_AON_APB_RF_APCPU_CLUSTER_SCU_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_CLUSTER_SCU_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU_DDR_AB_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU_DDR_AB_LP_EB 0x1
+#define MASK_AON_APB_RF_QOS_DAP_APCPU 0xf00000
+#define MASK_AON_APB_RF_QOS_ETR_APCPU 0xf0000
+#define MASK_AON_APB_RF_ARQOS_THRESHOLD_APCPU 0xf000
+#define MASK_AON_APB_RF_AWQOS_THRESHOLD_APCPU 0xf00
+#define MASK_AON_APB_RF_ARQOS_APCPU 0xf0
+#define MASK_AON_APB_RF_AWQOS_APCPU 0xf
+#define MASK_AON_APB_RF_CGM_MPLL0_APCPU_FORCE_EN 0x200
+#define MASK_AON_APB_RF_CGM_MPLL0_APCPU_AUTO_GATE_SEL 0x100
+#define MASK_AON_APB_RF_MPLL0_WAIT_FORCE_EN 0x4
+#define MASK_AON_APB_RF_MPLL0_WAIT_AUTO_GATE_SEL 0x2
+#define MASK_AON_APB_RF_MPLL0_SOFT_CNT_DONE 0x1
+#define MASK_AON_APB_RF_CGM_MPLL1_APCPU_FORCE_EN 0x200
+#define MASK_AON_APB_RF_CGM_MPLL1_APCPU_AUTO_GATE_SEL 0x100
+#define MASK_AON_APB_RF_MPLL1_WAIT_FORCE_EN 0x4
+#define MASK_AON_APB_RF_MPLL1_WAIT_AUTO_GATE_SEL 0x2
+#define MASK_AON_APB_RF_MPLL1_SOFT_CNT_DONE 0x1
+#define MASK_AON_APB_RF_CGM_MPLL2_APCPU_FORCE_EN 0x200
+#define MASK_AON_APB_RF_CGM_MPLL2_APCPU_AUTO_GATE_SEL 0x100
+#define MASK_AON_APB_RF_MPLL2_WAIT_FORCE_EN 0x4
+#define MASK_AON_APB_RF_MPLL2_WAIT_AUTO_GATE_SEL 0x2
+#define MASK_AON_APB_RF_MPLL2_SOFT_CNT_DONE 0x1
+#define MASK_AON_APB_RF_CGM_DPLL1_1600M_PUB_FORCE_EN 0x200
+#define MASK_AON_APB_RF_CGM_DPLL0_2666M_PUB_FORCE_EN 0x100
+#define MASK_AON_APB_RF_CGM_DPLL1_1600M_PUB_AUTO_GATE_SEL 0x80
+#define MASK_AON_APB_RF_CGM_DPLL0_2666M_PUB_AUTO_GATE_SEL 0x40
+#define MASK_AON_APB_RF_DPLL1_WAIT_FORCE_EN 0x20
+#define MASK_AON_APB_RF_DPLL0_WAIT_FORCE_EN 0x10
+#define MASK_AON_APB_RF_DPLL1_WAIT_AUTO_GATE_SEL 0x8
+#define MASK_AON_APB_RF_DPLL0_WAIT_AUTO_GATE_SEL 0x4
+#define MASK_AON_APB_RF_DPLL1_SOFT_CNT_DONE 0x2
+#define MASK_AON_APB_RF_DPLL0_SOFT_CNT_DONE 0x1
+#define MASK_AON_APB_RF_PUB_APB_FW_EB 0x20000
+#define MASK_AON_APB_RF_PUB_REG_EB 0x10000
+#define MASK_AON_APB_RF_DMC_EB 0x8000
+#define MASK_AON_APB_RF_PHY_VREF_ADJ 0x3fc
+#define MASK_AON_APB_RF_PHY_VREF_PD 0x2
+#define MASK_AON_APB_RF_PHY_VREF_HI_C 0x1
+#define MASK_AON_APB_RF_VDSP2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_VDSP2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_PUBCP2WTL_ASYNC_BRIDGE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_PUBCP2WTL_ASYNC_BRIDGE_LP_EB 0x1
+#define MASK_AON_APB_RF_CM4_TO_AON_AXI_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_CM4_TO_AON_AXI_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_MAIN_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_MAIN_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M0_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M0_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M1_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M1_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M2_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M2_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M3_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M3_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M4_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M4_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M5_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M5_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_M6_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_M6_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S0_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S0_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S1_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S1_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S2_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S2_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S3_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S3_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S4_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S4_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S5_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S5_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S6_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S6_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S7_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S7_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S8_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S8_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_MTX_S9_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON_MTX_S9_LP_EB 0x1
+#define MASK_AON_APB_RF_AP2GPU_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AP2GPU_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_AP2MM_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AP2MM_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_WTLCP2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_WTLCP2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU2AP_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU2AP_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_AUDCP2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AUDCP2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_APCPU2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_APCPU2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_AON2DDR_ASYNC_BRIDGE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AON2DDR_ASYNC_BRIDGE_LP_EB 0x1
+#define MASK_AON_APB_RF_PUBCP2WTLCP_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_PUBCP2WTLCP_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_DCAM2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_DCAM2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_DPU2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_DPU2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_GPU2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_GPU2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_ISP2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_ISP2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_AP2DDR_SLICE_LP_NUM 0x1fffe
+#define MASK_AON_APB_RF_AP2DDR_SLICE_LP_EB 0x1
+#define MASK_AON_APB_RF_AON_APB_MASTER_BUSY 0xfc
+#define MASK_AON_APB_RF_AON_APB_FREQ_CTRL_EN 0x2
+#define MASK_AON_APB_RF_AON_APB_IDLE_EN 0x1
+#define MASK_AON_APB_RF_CLK_26MHZ_AUD_CP_ADC_EN 0x10
+#define MASK_AON_APB_RF_CLK_26MHZ_AUD_AP_ADC_EN 0x8
+#define MASK_AON_APB_RF_CLK_26MHZ_AUD_CAL_EN 0x4
+#define MASK_AON_APB_RF_CLK_26MHZ_AUD_DVFS_EN 0x2
+#define MASK_AON_APB_RF_CLK_26MHZ_AUD_EN 0x1
+#define MASK_AON_APB_RF_ANALOG_BB_TOP_SINDRV_ENA_AUTO_EN 0x40
+#define MASK_AON_APB_RF_R2G_ANALOG_BB_TOP_SINDRV_ENA 0x20
+#define MASK_AON_APB_RF_M2G_ANALOG_BB_TOP_SINDRV_ENA 0x10
+#define MASK_AON_APB_RF_R2G_ANALOG_BB_TOP_SINDRV_ENA_SQUARE 0x8
+#define MASK_AON_APB_RF_R2G_ANALOG_BB_TOP_SINDRV_ENA_ADC 0x4
+#define MASK_AON_APB_RF_R2G_ANALOG_BB_TOP_SINDRV_ENA_DVFS 0x2
+#define MASK_AON_APB_RF_R2G_ANALOG_BB_TOP_SINDRV_ENA_CAL 0x1
+#define MASK_AON_APB_RF_AP_EMMC_IO_POWER_OFF_DELAY 0x2000000
+#define MASK_AON_APB_RF_AP_EMMC_IO_POWER_OFF 0x1000000
+#define MASK_AON_APB_RF_AP_EMMC_CARDDET_DBNC_THD_32K 0xff0000
+#define MASK_AON_APB_RF_AP_EMMC_BATTERY_DBNC_THD_32K 0xff00
+#define MASK_AON_APB_RF_AP_EMMC_CARDDET_DBNC_EN_32K 0x80
+#define MASK_AON_APB_RF_AP_EMMC_BATTERY_DBNC_EN_32K 0x40
+#define MASK_AON_APB_RF_AP_EMMC_BATTERY_DEB_EN_32K 0x20
+#define MASK_AON_APB_RF_AP_EMMC_BATTERY_PRESENT_32K 0x10
+#define MASK_AON_APB_RF_AP_EMMC_CARD_PROTECT_32K 0x8
+#define MASK_AON_APB_RF_AP_EMMC_CARD_PRESENT_32K 0x4
+#define MASK_AON_APB_RF_AP_EMMC_BATTERY_DET 0x2
+#define MASK_AON_APB_RF_AP_EMMC_CARD_DET 0x1
+#define MASK_AON_APB_RF_AP_SDIO0_IO_POWER_OFF_DELAY 0x2000000
+#define MASK_AON_APB_RF_AP_SDIO0_IO_POWER_OFF 0x1000000
+#define MASK_AON_APB_RF_AP_SDIO0_CARDDET_DBNC_THD_32K 0xff0000
+#define MASK_AON_APB_RF_AP_SDIO0_BATTERY_DBNC_THD_32K 0xff00
+#define MASK_AON_APB_RF_AP_SDIO0_CARDDET_DBNC_EN_32K 0x80
+#define MASK_AON_APB_RF_AP_SDIO0_BATTERY_DBNC_EN_32K 0x40
+#define MASK_AON_APB_RF_AP_SDIO0_BATTERY_DEB_EN_32K 0x20
+#define MASK_AON_APB_RF_AP_SDIO0_BATTERY_PRESENT_32K 0x10
+#define MASK_AON_APB_RF_AP_SDIO0_CARD_PROTECT_32K 0x8
+#define MASK_AON_APB_RF_AP_SDIO0_CARD_PRESENT_32K 0x4
+#define MASK_AON_APB_RF_AP_SDIO0_BATTERY_DET 0x2
+#define MASK_AON_APB_RF_AP_SDIO0_CARD_DET 0x1
+#define MASK_AON_APB_RF_AP_SDIO1_IO_POWER_OFF_DELAY 0x2000000
+#define MASK_AON_APB_RF_AP_SDIO1_IO_POWER_OFF 0x1000000
+#define MASK_AON_APB_RF_AP_SDIO1_CARDDET_DBNC_THD_32K 0xff0000
+#define MASK_AON_APB_RF_AP_SDIO1_BATTERY_DBNC_THD_32K 0xff00
+#define MASK_AON_APB_RF_AP_SDIO1_CARDDET_DBNC_EN_32K 0x80
+#define MASK_AON_APB_RF_AP_SDIO1_BATTERY_DBNC_EN_32K 0x40
+#define MASK_AON_APB_RF_AP_SDIO1_BATTERY_DEB_EN_32K 0x20
+#define MASK_AON_APB_RF_AP_SDIO1_BATTERY_PRESENT_32K 0x10
+#define MASK_AON_APB_RF_AP_SDIO1_CARD_PROTECT_32K 0x8
+#define MASK_AON_APB_RF_AP_SDIO1_CARD_PRESENT_32K 0x4
+#define MASK_AON_APB_RF_AP_SDIO1_BATTERY_DET 0x2
+#define MASK_AON_APB_RF_AP_SDIO1_CARD_DET 0x1
+#define MASK_AON_APB_RF_AP_SDIO2_IO_POWER_OFF_DELAY 0x2000000
+#define MASK_AON_APB_RF_AP_SDIO2_IO_POWER_OFF 0x1000000
+#define MASK_AON_APB_RF_AP_SDIO2_CARDDET_DBNC_THD_32K 0xff0000
+#define MASK_AON_APB_RF_AP_SDIO2_BATTERY_DBNC_THD_32K 0xff00
+#define MASK_AON_APB_RF_AP_SDIO2_CARDDET_DBNC_EN_32K 0x80
+#define MASK_AON_APB_RF_AP_SDIO2_BATTERY_DBNC_EN_32K 0x40
+#define MASK_AON_APB_RF_AP_SDIO2_BATTERY_DEB_EN_32K 0x20
+#define MASK_AON_APB_RF_AP_SDIO2_BATTERY_PRESENT_32K 0x10
+#define MASK_AON_APB_RF_AP_SDIO2_CARD_PROTECT_32K 0x8
+#define MASK_AON_APB_RF_AP_SDIO2_CARD_PRESENT_32K 0x4
+#define MASK_AON_APB_RF_AP_SDIO2_BATTERY_DET 0x2
+#define MASK_AON_APB_RF_AP_SDIO2_CARD_DET 0x1
+#define MASK_AON_APB_RF_PUBCP_SDIO0_IO_POWER_OFF_DELAY 0x2000000
+#define MASK_AON_APB_RF_PUBCP_SDIO0_IO_POWER_OFF 0x1000000
+#define MASK_AON_APB_RF_PUBCP_SDIO0_CARDDET_DBNC_THD_32K 0xff0000
+#define MASK_AON_APB_RF_PUBCP_SDIO0_BATTERY_DBNC_THD_32K 0xff00
+#define MASK_AON_APB_RF_PUBCP_SDIO0_CARDDET_DBNC_EN_32K 0x80
+#define MASK_AON_APB_RF_PUBCP_SDIO0_BATTERY_DBNC_EN_32K 0x40
+#define MASK_AON_APB_RF_PUBCP_SDIO0_BATTERY_DEB_EN_32K 0x20
+#define MASK_AON_APB_RF_PUBCP_SDIO0_BATTERY_PRESENT_32K 0x10
+#define MASK_AON_APB_RF_PUBCP_SDIO0_CARD_PROTECT_32K 0x8
+#define MASK_AON_APB_RF_PUBCP_SDIO0_CARD_PRESENT_32K 0x4
+#define MASK_AON_APB_RF_PUBCP_SDIO0_BATTERY_DET 0x2
+#define MASK_AON_APB_RF_PUBCP_SDIO0_CARD_DET 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_31 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_30 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_29 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_28 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_27 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_26 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_25 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_24 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_23 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_22 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_21 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_20 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_19 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_18 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_17 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_16 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_15 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_14 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_13 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_12 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_11 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_10 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_9 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_8 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_7 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_6 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_5 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_4 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_3 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_2 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_1 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_0 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_63 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_62 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_61 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_60 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_59 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_58 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_57 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_56 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_55 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_54 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_53 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_52 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_51 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_50 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_49 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_48 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_47 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_46 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_45 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_44 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_43 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_42 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_41 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_40 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_39 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_38 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_37 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_36 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_35 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_34 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_33 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_32 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_95 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_94 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_93 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_92 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_91 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_90 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_89 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_88 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_87 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_86 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_85 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_84 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_83 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_82 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_81 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_80 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_79 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_78 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_77 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_76 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_75 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_74 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_73 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_72 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_71 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_70 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_69 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_68 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_67 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_66 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_65 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_64 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_127 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_126 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_125 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_124 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_123 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_122 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_121 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_120 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_119 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_118 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_117 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_116 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_115 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_114 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_113 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_112 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_111 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_110 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_109 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_108 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_107 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_106 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_105 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_104 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_103 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_102 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_101 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_100 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_99 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_98 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_97 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_96 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_159 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_158 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_157 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_156 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_155 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_154 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_153 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_152 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_151 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_150 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_149 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_148 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_147 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_146 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_145 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_144 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_143 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_142 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_141 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_140 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_139 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_138 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_137 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_136 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_135 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_134 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_133 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_132 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_131 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_130 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_129 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_128 0x1
+#define MASK_AON_APB_RF_APCPU_INT_EN_191 0x80000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_190 0x40000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_189 0x20000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_188 0x10000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_187 0x8000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_186 0x4000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_185 0x2000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_184 0x1000000
+#define MASK_AON_APB_RF_APCPU_INT_EN_183 0x800000
+#define MASK_AON_APB_RF_APCPU_INT_EN_182 0x400000
+#define MASK_AON_APB_RF_APCPU_INT_EN_181 0x200000
+#define MASK_AON_APB_RF_APCPU_INT_EN_180 0x100000
+#define MASK_AON_APB_RF_APCPU_INT_EN_179 0x80000
+#define MASK_AON_APB_RF_APCPU_INT_EN_178 0x40000
+#define MASK_AON_APB_RF_APCPU_INT_EN_177 0x20000
+#define MASK_AON_APB_RF_APCPU_INT_EN_176 0x10000
+#define MASK_AON_APB_RF_APCPU_INT_EN_175 0x8000
+#define MASK_AON_APB_RF_APCPU_INT_EN_174 0x4000
+#define MASK_AON_APB_RF_APCPU_INT_EN_173 0x2000
+#define MASK_AON_APB_RF_APCPU_INT_EN_172 0x1000
+#define MASK_AON_APB_RF_APCPU_INT_EN_171 0x800
+#define MASK_AON_APB_RF_APCPU_INT_EN_170 0x400
+#define MASK_AON_APB_RF_APCPU_INT_EN_169 0x200
+#define MASK_AON_APB_RF_APCPU_INT_EN_168 0x100
+#define MASK_AON_APB_RF_APCPU_INT_EN_167 0x80
+#define MASK_AON_APB_RF_APCPU_INT_EN_166 0x40
+#define MASK_AON_APB_RF_APCPU_INT_EN_165 0x20
+#define MASK_AON_APB_RF_APCPU_INT_EN_164 0x10
+#define MASK_AON_APB_RF_APCPU_INT_EN_163 0x8
+#define MASK_AON_APB_RF_APCPU_INT_EN_162 0x4
+#define MASK_AON_APB_RF_APCPU_INT_EN_161 0x2
+#define MASK_AON_APB_RF_APCPU_INT_EN_160 0x1
+#define MASK_AON_APB_RF_AP_WDG_RST_FLAG 0x40
+#define MASK_AON_APB_RF_PCP_WDG_RST_FLAG 0x20
+#define MASK_AON_APB_RF_WTLCP_LTE_WDG_RST_FLAG 0x10
+#define MASK_AON_APB_RF_WTLCP_TG_WDG_RST_FLAG 0x8
+#define MASK_AON_APB_RF_AUDCP_WDG_RST_FLAG 0x4
+#define MASK_AON_APB_RF_APCPU_WDG_RST_FLAG 0x2
+#define MASK_AON_APB_RF_SEC_WDG_RST_FLAG 0x1
+#define MASK_AON_APB_RF_BOND_OPTION0 0xffffffff
+#define MASK_AON_APB_RF_BOND_OPTION1 0xffffffff
+#define MASK_AON_APB_RF_RES_REG0 0xffffffff
+#define MASK_AON_APB_RF_RES_REG1 0xffffffff
+#define MASK_AON_APB_RF_RES_REG2 0xffffffff
+#define MASK_AON_APB_RF_RES_REG3 0xffffffff
+#define MASK_AON_APB_RF_RES_REG4 0xffffffff
+#define MASK_AON_APB_RF_HPROT_DMAW 0xf0
+#define MASK_AON_APB_RF_HPROT_DMAR 0xf
+#define MASK_AON_APB_RF_REC_26MHZ_0_BUF_PD 0x100
+#define MASK_AON_APB_RF_SLEEP_PLLLOCK_SEL 0x80
+#define MASK_AON_APB_RF_PLL_LOCK_SEL 0x70
+#define MASK_AON_APB_RF_SLEEP_DBG_SEL 0xf
+#define MASK_AON_APB_RF_CPU2DDR_BRIDGE_DEBUG_SIGNAL_R 0xffffffff
+#define MASK_AON_APB_RF_AON2DDR_BRIDGE_DEBUG_SIGNAL_R 0xffffffff
+#define MASK_AON_APB_RF_AON2DDR_AXI_DETECTOR_OVERFLOW 0x4
+#define MASK_AON_APB_RF_AON2DDR_RST_SUBSYS 0x2
+#define MASK_AON_APB_RF_AON2DDR_BRIDGE_TRANS_IDLE 0x1
+#define MASK_AON_APB_RF_AUD2DDR_BRIDGE_DEBUG_SIGNAL_R 0xffffffff
+#define MASK_AON_APB_RF_WTL2DDR_BRIDGE_DEBUG_SIGNAL_R 0xffffffff
+#define MASK_AON_APB_RF_PUBCP2WTL_BRIDGE_DEBUG_SIGNAL_R 0xffffffff
+#define MASK_AON_APB_RF_LEAKAGE_MAGIC_WORD 0xffffffff
+#define MASK_AON_APB_RF_LEAKAGE_SWITCH 0x1
+#define MASK_AON_APB_RF_FUNC_TEST_BOOT_ADDR 0xffffffff
+#define MASK_AON_APB_RF_CGM_RESCUE 0xffffffff
+#define MASK_AON_APB_RF_SDIO2_SLICE_EN 0x8
+#define MASK_AON_APB_RF_CP_SDIO_ENABLE 0x4
+#define MASK_AON_APB_RF_AP_SDIO_ENABLE 0x2
+#define MASK_AON_APB_RF_SDIO_MODULE_SEL 0x1
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_PUBCP_WAKEUP_EN 0x80000000
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_AUDCP_WAKEUP_EN 0x40000000
+#define MASK_AON_APB_RF_SP_INT_REQ_ADI_WAKEUP_EN 0x20000000
+#define MASK_AON_APB_RF_SP_INT_REQ_PCP_WDG_WAKEUP_EN 0x10000000
+#define MASK_AON_APB_RF_SP_INT_REQ_PWR_DOWN_ALL_WAKEUP_EN 0x8000000
+#define MASK_AON_APB_RF_SP_INT_REQ_PWR_UP_ALL_WAKEUP_EN 0x4000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AP_WDG_RST_WAKEUP_EN 0x2000000
+#define MASK_AON_APB_RF_SP_INT_REQ_APCPU_WDG_RST_WAKEUP_EN 0x1000000
+#define MASK_AON_APB_RF_SP_INT_REQ_SEC_EIC_WAKEUP_EN 0x800000
+#define MASK_AON_APB_RF_SP_INT_REQ_SEC_TMR_WAKEUP_EN 0x400000
+#define MASK_AON_APB_RF_SP_INT_REQ_SEC_WDG_WAKEUP_EN 0x200000
+#define MASK_AON_APB_RF_SP_INT_REQ_SEC_RTC_WAKEUP_EN 0x100000
+#define MASK_AON_APB_RF_SP_INT_REQ_SEC_GPIO_WAKEUP_EN 0x80000
+#define MASK_AON_APB_RF_SP_INT_REQ_MBOX_SRC_SIPC_SP_CM4_WAKEUP_EN 0x40000
+#define MASK_AON_APB_RF_SP_INT_REQ_MBOX_SRC_CM4_WAKEUP_EN 0x20000
+#define MASK_AON_APB_RF_SP_INT_REQ_MBOX_TAR_CM4_WAKEUP_EN 0x10000
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_SOFT_WAKEUP_EN 0x8000
+#define MASK_AON_APB_RF_SP_INT_FPU_EXCEPTION_WAKEUP_EN 0x4000
+#define MASK_AON_APB_RF_SP_INT_REQ_EIC_GPIO_NON_LAT_WAKEUP_EN 0x2000
+#define MASK_AON_APB_RF_SP_INT_REQ_EIC_GPIO_LAT_WAKEUP_EN 0x1000
+#define MASK_AON_APB_RF_SP_INT_REQ_EIC_NON_LAT_WAKEUP_EN 0x800
+#define MASK_AON_APB_RF_SP_INT_REQ_EIC_LAT_WAKEUP_EN 0x400
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_DMA_WAKEUP_EN 0x200
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_GPIO_WAKEUP_EN 0x100
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_SYST_WAKEUP_EN 0x80
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_I2C0_SLV_WAKEUP_EN 0x40
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_WDG_WAKEUP_EN 0x20
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_SPI_WAKEUP_EN 0x10
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_UART1_WAKEUP_EN 0x8
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_UART0_WAKEUP_EN 0x4
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_I3C1_WAKEUP_EN 0x2
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_I3C0_WAKEUP_EN 0x1
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_VBC_AUDRCD_WAKEUP_EN 0x80000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_MCDT_WAKEUP_EN 0x40000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_DMA_WAKEUP_EN 0x20000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_CHN_START_CHN3_WAKEUP_EN 0x10000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_CHN_START_CHN2_WAKEUP_EN 0x8000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_CHN_START_CHN1_WAKEUP_EN 0x4000000
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_CHN_START_CHN0_WAKEUP_EN 0x2000000
+#define MASK_AON_APB_RF_SP_INT_REQ_ANA_WAKEUP_EN 0x1000000
+#define MASK_AON_APB_RF_SP_INT_REQ_WTLCP_LTE_WDG_RST_WAKEUP_EN 0x800000
+#define MASK_AON_APB_RF_SP_INT_REQ_WTLCP_TG_WDG_RST_WAKEUP_EN 0x400000
+#define MASK_AON_APB_RF_SP_INT_REQ_GSP_WAKEUP_EN 0x200000
+#define MASK_AON_APB_RF_SP_INT_REQ_SLV_FW_AP_WAKEUP_EN 0x100000
+#define MASK_AON_APB_RF_SP_INT_REQ_DISPC_WAKEUP_EN 0x80000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DFS_DENY_EN 0x40000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DMC_MPU_VIO_WAKEUP_EN 0x20000
+#define MASK_AON_APB_RF_SP_INT_REQ_MEM_FW_PUB_WAKEUP_EN 0x10000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DFI_BUSMON_WAKEUP_EN 0x8000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_PTM_WAKEUP_EN 0x4000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_HARDWARE_DFS_EXIT_WAKEUP_EN 0x2000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DFS_COMPLETE_WAKEUP_EN 0x1000
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DFS_ERROR_WAKEUP_EN 0x800
+#define MASK_AON_APB_RF_SP_INT_REQ_PUB_DFS_GIVEUP_EN 0x400
+#define MASK_AON_APB_RF_SP_INT_REQ_CLK_32K_DET_WAKEUP_EN 0x200
+#define MASK_AON_APB_RF_SP_INT_REQ_AON_I2C_WAKEUP_EN 0x100
+#define MASK_AON_APB_RF_SP_INT_REQ_THM0_WAKEUP_EN 0x80
+#define MASK_AON_APB_RF_SP_INT_REQ_PWR_UP_PUB_WAKEUP_EN 0x40
+#define MASK_AON_APB_RF_SP_INT_REQ_PWR_UP_AP_WAKEUP_EN 0x20
+#define MASK_AON_APB_RF_SP_INT_REQ_SLV_FW_AON_WAKEUP_EN 0x10
+#define MASK_AON_APB_RF_SP_INT_REQ_MEM_FW_AON_WAKEUP_EN 0x8
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_USB_WAKEUP_EN 0x4
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_AP_WAKEUP_EN 0x2
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_WTLCP_WAKEUP_EN 0x1
+#define MASK_AON_APB_RF_SP_INT_REQ_ICACHE_SP_WAKEUP_EN 0x1000
+#define MASK_AON_APB_RF_SP_INT_REQ_DCACHE_SP_WAKEUP_EN 0x800
+#define MASK_AON_APB_RF_SP_INT_REQ_BUSMON_CM4_SP_WAKEUP_EN 0x400
+#define MASK_AON_APB_RF_SP_INT_REQ_DFS_VOTE_DONE_WAKEUP_EN 0x200
+#define MASK_AON_APB_RF_SP_INT_REQ_THM2_WAKEUP_EN 0x100
+#define MASK_AON_APB_RF_SP_INT_REQ_THM1_WAKEUP_EN 0x80
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_TMR2_WAKEUP_EN 0x40
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_TMR1_WAKEUP_EN 0x20
+#define MASK_AON_APB_RF_SP_INT_REQ_CM4_TMR0_WAKEUP_EN 0x10
+#define MASK_AON_APB_RF_SP_INT_REQ_EXT_RSTB_SPCPU_WAKEUP_EN 0x8
+#define MASK_AON_APB_RF_SP_INT_REQ_DBG_AXI_MON_WAKEUP_EN 0x4
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_WDG_RST_WAKEUP_EN 0x2
+#define MASK_AON_APB_RF_SP_INT_REQ_AUDCP_VBC_AUDPLY_WAKEUP_EN 0x1
+#define MASK_AON_APB_RF_DBG_BUS_DATA_WTLCP 0xffffffff
+#define MASK_AON_APB_RF_DBG_BUS_DATA_PUBCP 0xffffffff
+#define MASK_AON_APB_RF_DBG_BUS_DATA_AUDCP 0xffffffff
+#define MASK_AON_APB_RF_SCC_DBG_BUS 0xffffffff
+#define MASK_AON_APB_RF_AON_FUNC_CTRL_0 0xffffffff
+#define MASK_AON_APB_RF_AON_FUNC_CTRL_1 0xffffffff
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C0_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C0_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C1_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C1_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C2_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C2_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C2_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_DCDC_PWR_ON_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_DCDC_PWR_OFF_DLY 0xff
+#define MASK_PMU_APB_RF_PD_AP_VSP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_AP_VSP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_AP_VSP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_AP_VSP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_AP_VSP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_AP_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_AP_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_AP_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_AP_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_AP_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_MM_TOP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_MM_TOP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_MM_TOP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_MM_TOP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_MM_TOP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_GPU_TOP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_GPU_TOP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_GPU_TOP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_GPU_TOP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_GPU_TOP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_PUBCP_DBG_SHUTDOWN_EN 0x4000000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PUBCP_FRC_STOP_REQ_FOR_WTL 0x1
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_MEM_RET_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_MEM_RET_REG 0x4000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_PUB_SYS_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_PUB_SYS_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_PUB_SYS_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_PUB_SYS_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_PUB_SYS_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_AP_WAKEUP_POR_N 0x1
+#define MASK_PMU_APB_RF_XTLBUF1_WAIT_CNT 0xff000000
+#define MASK_PMU_APB_RF_XTLBUF0_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_XTL1_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_XTL0_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_MPLL2_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_MPLL1_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_MPLL0_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_LTEPLL_WAIT_CNT 0xff000000
+#define MASK_PMU_APB_RF_TWPLL_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_DPLL1_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_DPLL0_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_ISPPLL_WAIT_CNT 0xff000000
+#define MASK_PMU_APB_RF_RPLL_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_GPLL_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_CPPLL_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_XTL0_CDMA_AUTO_SEL 0x800
+#define MASK_PMU_APB_RF_XTL0_CDMA_SEL 0x400
+#define MASK_PMU_APB_RF_XTL0_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_XTL0_FRC_ON 0x100
+#define MASK_PMU_APB_RF_XTL0_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_XTL0_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_XTL0_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_XTL0_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_XTL0_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_XTL0_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_XTL0_AP_SEL 0x1
+#define MASK_PMU_APB_RF_XTL1_CDMA_AUTO_SEL 0x800
+#define MASK_PMU_APB_RF_XTL1_CDMA_SEL 0x400
+#define MASK_PMU_APB_RF_XTL1_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_XTL1_FRC_ON 0x100
+#define MASK_PMU_APB_RF_XTL1_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_XTL1_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_XTL1_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_XTL1_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_XTL1_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_XTL1_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_XTL1_AP_SEL 0x1
+#define MASK_PMU_APB_RF_ISPPLL_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_ISPPLL_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_ISPPLL_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_ISPPLL_REF_SEL 0x400
+#define MASK_PMU_APB_RF_ISPPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_ISPPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_ISPPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_ISPPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_ISPPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_ISPPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_ISPPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_ISPPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_ISPPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_XTLBUF0_CDMA_AUTO_SEL 0x800
+#define MASK_PMU_APB_RF_XTLBUF0_CDMA_SEL 0x400
+#define MASK_PMU_APB_RF_XTLBUF0_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_XTLBUF0_FRC_ON 0x100
+#define MASK_PMU_APB_RF_XTLBUF0_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_XTLBUF0_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_XTLBUF0_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_XTLBUF0_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_XTLBUF0_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_XTLBUF0_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_XTLBUF0_AP_SEL 0x1
+#define MASK_PMU_APB_RF_XTLBUF1_CDMA_AUTO_SEL 0x800
+#define MASK_PMU_APB_RF_XTLBUF1_CDMA_SEL 0x400
+#define MASK_PMU_APB_RF_XTLBUF1_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_XTLBUF1_FRC_ON 0x100
+#define MASK_PMU_APB_RF_XTLBUF1_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_XTLBUF1_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_XTLBUF1_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_XTLBUF1_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_XTLBUF1_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_XTLBUF1_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_XTLBUF1_AP_SEL 0x1
+#define MASK_PMU_APB_RF_DPLL0_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_DPLL0_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_DPLL0_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_DPLL0_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_DPLL0_REF_SEL 0x200
+#define MASK_PMU_APB_RF_DPLL0_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_DPLL0_FRC_ON 0x80
+#define MASK_PMU_APB_RF_DPLL0_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_DPLL0_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_DPLL0_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_DPLL0_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_DPLL0_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_DPLL0_AP_SEL 0x1
+#define MASK_PMU_APB_RF_DPLL1_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_DPLL1_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_DPLL1_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_DPLL1_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_DPLL1_REF_SEL 0x200
+#define MASK_PMU_APB_RF_DPLL1_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_DPLL1_FRC_ON 0x80
+#define MASK_PMU_APB_RF_DPLL1_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_DPLL1_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_DPLL1_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_DPLL1_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_DPLL1_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_DPLL1_AP_SEL 0x1
+#define MASK_PMU_APB_RF_LTEPLL_CDMA2PMU_AUTO_SEL 0x4000
+#define MASK_PMU_APB_RF_LTEPLL_CDMA_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_LTEPLL_CDMA_SEL 0x1000
+#define MASK_PMU_APB_RF_LTEPLL_REF_SEL 0xc00
+#define MASK_PMU_APB_RF_LTEPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_LTEPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_LTEPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_LTEPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_LTEPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_LTEPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_LTEPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_LTEPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_LTEPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_TWPLL_CDMA2PMU_AUTO_SEL 0x4000
+#define MASK_PMU_APB_RF_TWPLL_CDMA_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_TWPLL_CDMA_SEL 0x1000
+#define MASK_PMU_APB_RF_TWPLL_REF_SEL 0xc00
+#define MASK_PMU_APB_RF_TWPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_TWPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_TWPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_TWPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_TWPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_TWPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_TWPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_TWPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_TWPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_GPLL_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_GPLL_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_GPLL_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_GPLL_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_GPLL_REF_SEL 0x200
+#define MASK_PMU_APB_RF_GPLL_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_GPLL_FRC_ON 0x80
+#define MASK_PMU_APB_RF_GPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_GPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_GPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_GPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_GPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_GPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_RPLL_CDMA2PMU_AUTO_SEL 0x4000
+#define MASK_PMU_APB_RF_RPLL_CDMA_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_RPLL_CDMA_SEL 0x1000
+#define MASK_PMU_APB_RF_RPLL_REF_SEL 0xc00
+#define MASK_PMU_APB_RF_RPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_RPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_RPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_RPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_RPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_RPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_RPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_RPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_RPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_MODE_ST_SOFT_RST 0x4000000
+#define MASK_PMU_APB_RF_APCPU_CORE7_MODE_ST_SOFT_RST 0x2000000
+#define MASK_PMU_APB_RF_APCPU_CORE6_MODE_ST_SOFT_RST 0x1000000
+#define MASK_PMU_APB_RF_APCPU_CORE5_MODE_ST_SOFT_RST 0x800000
+#define MASK_PMU_APB_RF_APCPU_CORE4_MODE_ST_SOFT_RST 0x400000
+#define MASK_PMU_APB_RF_APCPU_CORE3_MODE_ST_SOFT_RST 0x200000
+#define MASK_PMU_APB_RF_APCPU_CORE2_MODE_ST_SOFT_RST 0x100000
+#define MASK_PMU_APB_RF_APCPU_CORE1_MODE_ST_SOFT_RST 0x80000
+#define MASK_PMU_APB_RF_APCPU_CORE0_MODE_ST_SOFT_RST 0x40000
+#define MASK_PMU_APB_RF_AP_VDSP_SOFT_RST 0x20000
+#define MASK_PMU_APB_RF_AP_VSP_SOFT_RST 0x10000
+#define MASK_PMU_APB_RF_WTLCP_TGDSP_SOFT_RST 0x8000
+#define MASK_PMU_APB_RF_WTLCP_LDSP_SOFT_RST 0x4000
+#define MASK_PMU_APB_RF_WCDMA_AON_SOFT_RST 0x2000
+#define MASK_PMU_APB_RF_WTLCP_AON_SOFT_RST 0x1000
+#define MASK_PMU_APB_RF_CDMA_SOFT_RST 0x800
+#define MASK_PMU_APB_RF_AUDCP_AUDDSP_SOFT_RST 0x400
+#define MASK_PMU_APB_RF_AUDCP_SYS_SOFT_RST 0x200
+#define MASK_PMU_APB_RF_SP_SYS_SOFT_RST 0x100
+#define MASK_PMU_APB_RF_APCPU_SOFT_RST 0x80
+#define MASK_PMU_APB_RF_PUB_SOFT_RST 0x40
+#define MASK_PMU_APB_RF_AP_SOFT_RST 0x20
+#define MASK_PMU_APB_RF_GPU_SOFT_RST 0x10
+#define MASK_PMU_APB_RF_MM_SOFT_RST 0x8
+#define MASK_PMU_APB_RF_WTLCP_DSP_SYS_SRST 0x4
+#define MASK_PMU_APB_RF_PUBCP_SOFT_RST 0x2
+#define MASK_PMU_APB_RF_WTLCP_SOFT_RST 0x1
+#define MASK_PMU_APB_RF_PUBCP_DEEP_SLP_DBG 0xffff0000
+#define MASK_PMU_APB_RF_WTLCP_DEEP_SLP_DBG 0xffff
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_PUB_SYS_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_STATE 0xff
+#define MASK_PMU_APB_RF_PD_AP_VDSP_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_AP_VSP_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_AP_SYS_STATE 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_STATE 0xff
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_STATE 0xff
+#define MASK_PMU_APB_RF_PUB_SYS_AUTO_LIGHT_SLEEP_ENABLE 0xffffffff
+#define MASK_PMU_APB_RF_PUB_SYS_FORCE_SYSTEM_SLEEP 0x80000000
+#define MASK_PMU_APB_RF_PUB_SYS_FORCE_LIGHT_SLEEP 0x40000000
+#define MASK_PMU_APB_RF_PUB_SYS_FORCE_DEEP_SLEEP 0x20000000
+#define MASK_PMU_APB_RF_PUB_SYS_AUTO_DEEP_SLEEP_ENABLE 0x10000000
+#define MASK_PMU_APB_RF_AON_DMA_FORCE_LIGHT_SLEEP 0x8000000
+#define MASK_PMU_APB_RF_PUBCP_FORCE_LIGHT_SLEEP 0x4000000
+#define MASK_PMU_APB_RF_WTLCP_FORCE_LIGHT_SLEEP 0x2000000
+#define MASK_PMU_APB_RF_AUDCP_FORCE_LIGHT_SLEEP 0x1000000
+#define MASK_PMU_APB_RF_AP_FORCE_LIGHT_SLEEP 0x800000
+#define MASK_PMU_APB_RF_AON_SYS_FORCE_LIGHT_SLEEP 0x400000
+#define MASK_PMU_APB_RF_AUDCP_FORCE_PUB_DEEP_SLEEP 0x200000
+#define MASK_PMU_APB_RF_SP_SYS_FORCE_DEEP_SLEEP 0x100000
+#define MASK_PMU_APB_RF_AUDCP_FORCE_DEEP_SLEEP 0x80000
+#define MASK_PMU_APB_RF_PUBCP_FORCE_DEEP_SLEEP 0x40000
+#define MASK_PMU_APB_RF_WTLCP_FORCE_DEEP_SLEEP 0x20000
+#define MASK_PMU_APB_RF_AP_FORCE_DEEP_SLEEP 0x10000
+#define MASK_PMU_APB_RF_CDMA_FORCE_DEEP_SLEEP 0x8000
+#define MASK_PMU_APB_RF_AUDCP_FORCE_SYSTEM_SLEEP 0x4000
+#define MASK_PMU_APB_RF_GPU_TOP_FORCE_SYSTEM_SLEEP 0x2000
+#define MASK_PMU_APB_RF_PUBCP_FORCE_SYSTEM_SLEEP 0x800
+#define MASK_PMU_APB_RF_WTLCP_FORCE_SYSTEM_SLEEP 0x400
+#define MASK_PMU_APB_RF_AP_FORCE_SYSTEM_SLEEP 0x200
+#define MASK_PMU_APB_RF_APCPU_FORCE_SYSTEM_SLEEP 0x100
+#define MASK_PMU_APB_RF_AP_ALL_FORCE_SYSTEM_SLEEP 0x80
+#define MASK_PMU_APB_RF_SP_SYS_DEEP_SLEEP 0x40
+#define MASK_PMU_APB_RF_AUDCP_DEEP_SLEEP 0x20
+#define MASK_PMU_APB_RF_PUB_SYS_DEEP_SLEEP 0x10
+#define MASK_PMU_APB_RF_CDMA_DEEP_SLEEP 0x8
+#define MASK_PMU_APB_RF_PUBCP_DEEP_SLEEP 0x4
+#define MASK_PMU_APB_RF_WTLCP_DEEP_SLEEP 0x2
+#define MASK_PMU_APB_RF_AP_DEEP_SLEEP 0x1
+#define MASK_PMU_APB_RF_DDR_SLEEP_DISABLE_ACK 0x80000
+#define MASK_PMU_APB_RF_DDR_SLEEP_DISABLE_ACK_BYP 0x40000
+#define MASK_PMU_APB_RF_DDR_SLEEP_DISABLE 0x20000
+#define MASK_PMU_APB_RF_BUSY_TRANSFER_HWDATA_SEL 0x10000
+#define MASK_PMU_APB_RF_DDR_PUBL_APB_SOFT_RST 0x1000
+#define MASK_PMU_APB_RF_DDR_UMCTL_APB_SOFT_RST 0x800
+#define MASK_PMU_APB_RF_DDR_PUBL_SOFT_RST 0x400
+#define MASK_PMU_APB_RF_DDR_PHY_SOFT_RST 0x100
+#define MASK_PMU_APB_RF_DDR_PHY_AUTO_GATE_EN 0x40
+#define MASK_PMU_APB_RF_DDR_PUBL_AUTO_GATE_EN 0x20
+#define MASK_PMU_APB_RF_DDR_UMCTL_AUTO_GATE_EN 0x10
+#define MASK_PMU_APB_RF_DDR_PHY_EB 0x4
+#define MASK_PMU_APB_RF_DDR_UMCTL_EB 0x2
+#define MASK_PMU_APB_RF_DDR_PUBL_EB 0x1
+#define MASK_PMU_APB_RF_CDMA_AUTO_SLP_STATUS 0xf000000
+#define MASK_PMU_APB_RF_SP_SYS_SLP_STATUS 0xf00000
+#define MASK_PMU_APB_RF_CDMA_SLP_STATUS 0xf0000
+#define MASK_PMU_APB_RF_AUDCP_SLP_STATUS 0xf000
+#define MASK_PMU_APB_RF_PUBCP_SLP_STATUS 0xf00
+#define MASK_PMU_APB_RF_WTLCP_SLP_STATUS 0xf0
+#define MASK_PMU_APB_RF_AP_SLP_STATUS 0xf
+#define MASK_PMU_APB_RF_SP_PUB_DEEP_SLEEP_VOTE_EN 0x8
+#define MASK_PMU_APB_RF_PUB_SYS_SELF_REFRESH_FLAG_BYPASS 0x4
+#define MASK_PMU_APB_RF_PUB_SYS_PWR_PD_ACK_BYPASS 0x2
+#define MASK_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_LOCK_ACK_BYPASS 0x1
+#define MASK_PMU_APB_RF_SP_PUB_SYS_DEEP_SLEEP_POLL 0xff00
+#define MASK_PMU_APB_RF_AUDCP_PUB_SYS_DEEP_SLEEP_POLL 0xff
+#define MASK_PMU_APB_RF_AON_PUB_SYS_DEEP_SLEEP_POLL 0xff000000
+#define MASK_PMU_APB_RF_PUBCP_PUB_SYS_DEEP_SLEEP_POLL 0xff0000
+#define MASK_PMU_APB_RF_AP_PUB_SYS_DEEP_SLEEP_POLL 0xff00
+#define MASK_PMU_APB_RF_WTLCP_PUB_SYS_DEEP_SLEEP_POLL 0xff
+#define MASK_PMU_APB_RF_CPPLL_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_CPPLL_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_CPPLL_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_CPPLL_REF_SEL 0x400
+#define MASK_PMU_APB_RF_CPPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_CPPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_CPPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_CPPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_CPPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_CPPLL_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_CPPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_CPPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_CPPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_CPPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_CPPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_CPPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_CPPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_DDR_CTRL_AXI_LP_EN 0x80000000
+#define MASK_PMU_APB_RF_DDR_CTRL_CGM_SEL 0x40000000
+#define MASK_PMU_APB_RF_DDR_CHN9_AXI_LP_EN 0x2000000
+#define MASK_PMU_APB_RF_DDR_CHN8_AXI_LP_EN 0x1000000
+#define MASK_PMU_APB_RF_DDR_CHN7_AXI_LP_EN 0x800000
+#define MASK_PMU_APB_RF_DDR_CHN6_AXI_LP_EN 0x400000
+#define MASK_PMU_APB_RF_DDR_CHN5_AXI_LP_EN 0x200000
+#define MASK_PMU_APB_RF_DDR_CHN4_AXI_LP_EN 0x100000
+#define MASK_PMU_APB_RF_DDR_CHN3_AXI_LP_EN 0x80000
+#define MASK_PMU_APB_RF_DDR_CHN2_AXI_LP_EN 0x40000
+#define MASK_PMU_APB_RF_DDR_CHN1_AXI_LP_EN 0x20000
+#define MASK_PMU_APB_RF_DDR_CHN0_AXI_LP_EN 0x10000
+#define MASK_PMU_APB_RF_DDR_CHN9_CGM_SEL 0x200
+#define MASK_PMU_APB_RF_DDR_CHN8_CGM_SEL 0x100
+#define MASK_PMU_APB_RF_DDR_CHN7_CGM_SEL 0x80
+#define MASK_PMU_APB_RF_DDR_CHN6_CGM_SEL 0x40
+#define MASK_PMU_APB_RF_DDR_CHN5_CGM_SEL 0x20
+#define MASK_PMU_APB_RF_DDR_CHN4_CGM_SEL 0x10
+#define MASK_PMU_APB_RF_DDR_CHN3_CGM_SEL 0x8
+#define MASK_PMU_APB_RF_DDR_CHN2_CGM_SEL 0x4
+#define MASK_PMU_APB_RF_DDR_CHN1_CGM_SEL 0x2
+#define MASK_PMU_APB_RF_DDR_CHN0_CGM_SEL 0x1
+#define MASK_PMU_APB_RF_DDR_CHN9_AXI_STOP_SEL 0x200
+#define MASK_PMU_APB_RF_DDR_CHN8_AXI_STOP_SEL 0x100
+#define MASK_PMU_APB_RF_DDR_CHN7_AXI_STOP_SEL 0x80
+#define MASK_PMU_APB_RF_DDR_CHN6_AXI_STOP_SEL 0x40
+#define MASK_PMU_APB_RF_DDR_CHN5_AXI_STOP_SEL 0x20
+#define MASK_PMU_APB_RF_DDR_CHN4_AXI_STOP_SEL 0x10
+#define MASK_PMU_APB_RF_DDR_CHN3_AXI_STOP_SEL 0x8
+#define MASK_PMU_APB_RF_DDR_CHN2_AXI_STOP_SEL 0x4
+#define MASK_PMU_APB_RF_DDR_CHN1_AXI_STOP_SEL 0x2
+#define MASK_PMU_APB_RF_DDR_CHN0_AXI_STOP_SEL 0x1
+#define MASK_PMU_APB_RF_PD_MM_TOP_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_GPU_TOP_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_STATE 0xff
+#define MASK_PMU_APB_RF_DDR_PUB_RET_EN 0x8000000
+#define MASK_PMU_APB_RF_DDR_PHY_ISO_RST_EN 0x4000000
+#define MASK_PMU_APB_RF_DDR_UMCTL_RET_EN 0x2000000
+#define MASK_PMU_APB_RF_DDR_PHY_AUTO_RET_EN 0x1000000
+#define MASK_PMU_APB_RF_DDR_UMCTL_SOFT_RST 0x10000
+#define MASK_PMU_APB_RF_DDR_PHY_CKE_RET_EN 0x1
+#define MASK_PMU_APB_RF_AON_RC_4M_SEL 0x100
+#define MASK_PMU_APB_RF_GGE_26M_SEL 0x40
+#define MASK_PMU_APB_RF_PUB_26M_SEL 0x20
+#define MASK_PMU_APB_RF_AON_26M_SEL 0x10
+#define MASK_PMU_APB_RF_AUDCP_26M_SEL 0x8
+#define MASK_PMU_APB_RF_PUBCP_26M_SEL 0x4
+#define MASK_PMU_APB_RF_WTLCP_26M_SEL 0x2
+#define MASK_PMU_APB_RF_AP_26M_SEL 0x1
+#define MASK_PMU_APB_RF_PD_GPU_C1_BISR_DONE 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_BISR_DONE 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_BISR_DONE 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_BISR_DONE 0x4000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_BISR_DONE 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_BISR_DONE 0x1000000
+#define MASK_PMU_APB_RF_PD_GPU_C0_BISR_DONE 0x800000
+#define MASK_PMU_APB_RF_PD_AP_VSP_BISR_DONE 0x400000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_BISR_DONE 0x200000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_BISR_DONE 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_BISR_DONE 0x80000
+#define MASK_PMU_APB_RF_PD_AON_MEM_BISR_DONE 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_BISR_DONE 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_BISR_DONE 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_BISR_DONE 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_BISR_DONE 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_BISR_DONE 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_BISR_DONE 0x1000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_BISR_DONE 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_BISR_DONE 0x400
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_BISR_DONE 0x200
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_BISR_DONE 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_BISR_DONE 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_BISR_DONE 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_BISR_DONE 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_BISR_DONE 0x10
+#define MASK_PMU_APB_RF_PD_AP_VDSP_BISR_DONE 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_BISR_DONE 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_BISR_DONE 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_BISR_DONE 0x1
+#define MASK_PMU_APB_RF_PD_GPU_C1_BISR_BUSY 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_BISR_BUSY 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_BISR_BUSY 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_BISR_BUSY 0x4000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_BISR_BUSY 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_BISR_BUSY 0x1000000
+#define MASK_PMU_APB_RF_PD_GPU_C0_BISR_BUSY 0x800000
+#define MASK_PMU_APB_RF_PD_AP_VSP_BISR_BUSY 0x400000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_BISR_BUSY 0x200000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_BISR_BUSY 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_BISR_BUSY 0x80000
+#define MASK_PMU_APB_RF_PD_AON_MEM_BISR_BUSY 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_BISR_BUSY 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_BISR_BUSY 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_BISR_BUSY 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_BISR_BUSY 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_BISR_BUSY 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_BISR_BUSY 0x1000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_BISR_BUSY 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_BISR_BUSY 0x400
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_BISR_BUSY 0x200
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_BISR_BUSY 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_BISR_BUSY 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_BISR_BUSY 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_BISR_BUSY 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_BISR_BUSY 0x10
+#define MASK_PMU_APB_RF_PD_AP_VDSP_BISR_BUSY 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_BISR_BUSY 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_BISR_BUSY 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_BISR_BUSY 0x1
+#define MASK_PMU_APB_RF_PD_GPU_C1_BISR_FORCE_BYP 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_BISR_FORCE_BYP 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_BISR_FORCE_BYP 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_BISR_FORCE_BYP 0x4000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_BISR_FORCE_BYP 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_BISR_FORCE_BYP 0x1000000
+#define MASK_PMU_APB_RF_PD_GPU_C0_BISR_FORCE_BYP 0x800000
+#define MASK_PMU_APB_RF_PD_AP_VSP_BISR_FORCE_BYP 0x400000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_BISR_FORCE_BYP 0x200000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_BISR_FORCE_BYP 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_BISR_FORCE_BYP 0x80000
+#define MASK_PMU_APB_RF_PD_AON_MEM_BISR_FORCE_BYP 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_BISR_FORCE_BYP 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_BISR_FORCE_BYP 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_BISR_FORCE_BYP 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_BISR_FORCE_BYP 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_BISR_FORCE_BYP 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_BISR_FORCE_BYP 0x1000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_BISR_FORCE_BYP 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_BISR_FORCE_BYP 0x400
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_BISR_FORCE_BYP 0x200
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_BISR_FORCE_BYP 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_BISR_FORCE_BYP 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_BISR_FORCE_BYP 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_BISR_FORCE_BYP 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_BISR_FORCE_BYP 0x10
+#define MASK_PMU_APB_RF_PD_AP_VDSP_BISR_FORCE_BYP 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_BISR_FORCE_BYP 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_BISR_FORCE_BYP 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_BISR_FORCE_BYP 0x1
+#define MASK_PMU_APB_RF_PD_GPU_C1_BISR_FORCE_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_BISR_FORCE_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_BISR_FORCE_EN 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_BISR_FORCE_EN 0x4000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_BISR_FORCE_EN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_BISR_FORCE_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_GPU_C0_BISR_FORCE_EN 0x800000
+#define MASK_PMU_APB_RF_PD_AP_VSP_BISR_FORCE_EN 0x400000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_BISR_FORCE_EN 0x200000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_BISR_FORCE_EN 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_BISR_FORCE_EN 0x80000
+#define MASK_PMU_APB_RF_PD_AON_MEM_BISR_FORCE_EN 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_BISR_FORCE_EN 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_BISR_FORCE_EN 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_BISR_FORCE_EN 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_BISR_FORCE_EN 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_BISR_FORCE_EN 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_BISR_FORCE_EN 0x1000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_BISR_FORCE_EN 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_BISR_FORCE_EN 0x400
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_BISR_FORCE_EN 0x200
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_BISR_FORCE_EN 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_BISR_FORCE_EN 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_BISR_FORCE_EN 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_BISR_FORCE_EN 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_BISR_FORCE_EN 0x10
+#define MASK_PMU_APB_RF_PD_AP_VDSP_BISR_FORCE_EN 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_BISR_FORCE_EN 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_BISR_FORCE_EN 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_BISR_FORCE_EN 0x1
+#define MASK_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG0 0xffffffff
+#define MASK_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG1 0xffffffff
+#define MASK_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG2 0xffffffff
+#define MASK_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG3 0xffffffff
+#define MASK_PMU_APB_RF_CGM_FORCE_EN_CFG0 0xffffffff
+#define MASK_PMU_APB_RF_CGM_FORCE_EN_CFG1 0xffffffff
+#define MASK_PMU_APB_RF_CGM_FORCE_EN_CFG2 0xffffffff
+#define MASK_PMU_APB_RF_CGM_FORCE_EN_CFG3 0xffffffff
+#define MASK_PMU_APB_RF_SP_SYS_SLEEP_XTL_ON 0x20
+#define MASK_PMU_APB_RF_CDMA_SLEEP_XTL_ON 0x10
+#define MASK_PMU_APB_RF_AUDCP_SYS_SLEEP_XTL_ON 0x8
+#define MASK_PMU_APB_RF_PUBCP_SLEEP_XTL_ON 0x4
+#define MASK_PMU_APB_RF_WTLCP_SLEEP_XTL_ON 0x2
+#define MASK_PMU_APB_RF_AP_SLEEP_XTL_ON 0x1
+#define MASK_PMU_APB_RF_MEM_SLP_CFG 0xffffffff
+#define MASK_PMU_APB_RF_MEM_SD_CFG 0xffffffff
+#define MASK_PMU_APB_RF_APCPU_C7_WAKEUP_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_C6_WAKEUP_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_C5_WAKEUP_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_C4_WAKEUP_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_C3_WAKEUP_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_C2_WAKEUP_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_C1_WAKEUP_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_C0_WAKEUP_EN 0x1
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_CMG_HOLD_EN 0x100
+#define MASK_PMU_APB_RF_PD_APCPU_C7_CMG_HOLD_EN 0x80
+#define MASK_PMU_APB_RF_PD_APCPU_C6_CMG_HOLD_EN 0x40
+#define MASK_PMU_APB_RF_PD_APCPU_C5_CMG_HOLD_EN 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_C4_CMG_HOLD_EN 0x10
+#define MASK_PMU_APB_RF_PD_APCPU_C3_CMG_HOLD_EN 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_CMG_HOLD_EN 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_CMG_HOLD_EN 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_CMG_HOLD_EN 0x1
+#define MASK_PMU_APB_RF_AUDCP_PWR_WAIT_CNT 0xff000000
+#define MASK_PMU_APB_RF_PUBCP_PWR_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_WTLCP_PWR_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_AP_PWR_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_CDMA_PWR_WAIT_CNT 0xff0000
+#define MASK_PMU_APB_RF_SP_SYS_PWR_WAIT_CNT 0xff00
+#define MASK_PMU_APB_RF_RCO_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_RCO_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_RCO_CSYSPWRUPREQ_SEL 0x400
+#define MASK_PMU_APB_RF_RCO_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_RCO_FRC_ON 0x100
+#define MASK_PMU_APB_RF_RCO_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_RCO_PUB_SYS_SEL 0x40
+#define MASK_PMU_APB_RF_RCO_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_RCO_AUDCP_SEL 0x8
+#define MASK_PMU_APB_RF_RCO_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_RCO_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_RCO_AP_SEL 0x1
+#define MASK_PMU_APB_RF_RCO_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_MPLL0_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_MPLL0_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_MPLL0_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_MPLL0_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_MPLL0_REF_SEL 0x200
+#define MASK_PMU_APB_RF_MPLL0_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_MPLL0_FRC_ON 0x80
+#define MASK_PMU_APB_RF_MPLL0_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_MPLL0_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_MPLL0_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_MPLL0_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_MPLL0_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_MPLL0_AP_SEL 0x1
+#define MASK_PMU_APB_RF_MPLL1_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_MPLL1_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_MPLL1_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_MPLL1_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_MPLL1_REF_SEL 0x200
+#define MASK_PMU_APB_RF_MPLL1_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_MPLL1_FRC_ON 0x80
+#define MASK_PMU_APB_RF_MPLL1_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_MPLL1_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_MPLL1_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_MPLL1_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_MPLL1_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_MPLL1_AP_SEL 0x1
+#define MASK_PMU_APB_RF_MPLL2_CDMA2PMU_AUTO_SEL 0x2000
+#define MASK_PMU_APB_RF_MPLL2_CDMA_AUTO_SEL 0x1000
+#define MASK_PMU_APB_RF_MPLL2_CDMA_SEL 0x800
+#define MASK_PMU_APB_RF_MPLL2_TOP_DVFS_SEL 0x400
+#define MASK_PMU_APB_RF_MPLL2_REF_SEL 0x200
+#define MASK_PMU_APB_RF_MPLL2_FRC_OFF 0x100
+#define MASK_PMU_APB_RF_MPLL2_FRC_ON 0x80
+#define MASK_PMU_APB_RF_MPLL2_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_MPLL2_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_MPLL2_AUDCP_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_MPLL2_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_MPLL2_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_MPLL2_AP_SEL 0x1
+#define MASK_PMU_APB_RF_MEM_AUTO_SLP_EN 0xffffffff
+#define MASK_PMU_APB_RF_MEM_AUTO_SD_EN 0xffffffff
+#define MASK_PMU_APB_RF_PD_APCPU_C7_WAKEUP_LOCK_EN 0x80000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_WAKEUP_LOCK_EN 0x40000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_WAKEUP_LOCK_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_WAKEUP_LOCK_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_WAKEUP_LOCK_EN 0x8000000
+#define MASK_PMU_APB_RF_PUBCP_SYS_WAKEUP_LOCK_EN 0x1000000
+#define MASK_PMU_APB_RF_WTLCP_SYS_WAKEUP_LOCK_EN 0x800000
+#define MASK_PMU_APB_RF_AP_SYS_WAKEUP_LOCK_EN 0x400000
+#define MASK_PMU_APB_RF_PD_PUB_SYS_WAKEUP_LOCK_EN 0x200000
+#define MASK_PMU_APB_RF_PD_AP_VSP_WAKEUP_LOCK_EN 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_WAKEUP_LOCK_EN 0x80000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_WAKEUP_LOCK_EN 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_WAKEUP_LOCK_EN 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_WAKEUP_LOCK_EN 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_WAKEUP_LOCK_EN 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_WAKEUP_LOCK_EN 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_WAKEUP_LOCK_EN 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_WAKEUP_LOCK_EN 0x1000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_WAKEUP_LOCK_EN 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_WAKEUP_LOCK_EN 0x400
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_WAKEUP_LOCK_EN 0x200
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_WAKEUP_LOCK_EN 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_WAKEUP_LOCK_EN 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_WAKEUP_LOCK_EN 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_WAKEUP_LOCK_EN 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_WAKEUP_LOCK_EN 0x10
+#define MASK_PMU_APB_RF_PD_AP_VDSP_WAKEUP_LOCK_EN 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_WAKEUP_LOCK_EN 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_WAKEUP_LOCK_EN 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_WAKEUP_LOCK_EN 0x1
+#define MASK_PMU_APB_RF_AUDCP_SYS_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_WTLCP_TGDSP_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_WTLCP_LDSP_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_PUBCP_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C0_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C1_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C2_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C7_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C7_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_CDMA_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_WTLCP_TGDSP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_WTLCP_LDSP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_AP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_PUBCP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_WTLCP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_TOP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_SP_SYS_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_AUDCP_SYS_PUB_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_AUDCP_PUB_DSLP_WAKEUP_EN 0x1
+#define MASK_PMU_APB_RF_AUDCP_LSLP_WAKEUP_EN 0x8
+#define MASK_PMU_APB_RF_WTLCP_LSLP_WAKEUP_EN 0x4
+#define MASK_PMU_APB_RF_PUBCP_LSLP_WAKEUP_EN 0x2
+#define MASK_PMU_APB_RF_AP_LSLP_WAKEUP_EN 0x1
+#define MASK_PMU_APB_RF_AON_SMART_LSLP_ENA 0x100000
+#define MASK_PMU_APB_RF_AUDCP_SMART_LSLP_ENA 0x80000
+#define MASK_PMU_APB_RF_WTLCP_SMART_LSLP_ENA 0x40000
+#define MASK_PMU_APB_RF_PUBCP_SMART_LSLP_ENA 0x20000
+#define MASK_PMU_APB_RF_AP_SMART_LSLP_ENA 0x10000
+#define MASK_PMU_APB_RF_PUB_SYS_SMART_LSLP_ENA 0x400
+#define MASK_PMU_APB_RF_MM_LSLP_ENA 0x200
+#define MASK_PMU_APB_RF_GPU_LSLP_ENA 0x100
+#define MASK_PMU_APB_RF_AUDCP_SYS_LSLP_ENA 0x10
+#define MASK_PMU_APB_RF_AON_DMA_LSLP_ENA 0x8
+#define MASK_PMU_APB_RF_WTLCP_LSLP_ENA 0x4
+#define MASK_PMU_APB_RF_PUBCP_LSLP_ENA 0x2
+#define MASK_PMU_APB_RF_AP_LSLP_ENA 0x1
+#define MASK_PMU_APB_RF_PUB_SYS_LIGHT_SLEEP 0x20
+#define MASK_PMU_APB_RF_AP_LIGHT_SLEEP 0x10
+#define MASK_PMU_APB_RF_WTLCP_LIGHT_SLEEP 0x8
+#define MASK_PMU_APB_RF_PUBCP_LIGHT_SLEEP 0x4
+#define MASK_PMU_APB_RF_AUDCP_LIGHT_SLEEP 0x2
+#define MASK_PMU_APB_RF_AON_SYS_LIGHT_SLEEP 0x1
+#define MASK_PMU_APB_RF_PUB_DOZE_EN 0x20
+#define MASK_PMU_APB_RF_AUDCP_DOZE_ENA 0x10
+#define MASK_PMU_APB_RF_PUBCP_DOZE_ENA 0x8
+#define MASK_PMU_APB_RF_WTLCP_DOZE_ENA 0x4
+#define MASK_PMU_APB_RF_AP_DOZE_ENA 0x2
+#define MASK_PMU_APB_RF_DOZE_EN 0x1
+#define MASK_PMU_APB_RF_AUDCP_DOZE_SLEEP_ORG 0x80
+#define MASK_PMU_APB_RF_PUBCP_DOZE_SLEEP_ORG 0x40
+#define MASK_PMU_APB_RF_WTLCP_DOZE_SLEEP_ORG 0x20
+#define MASK_PMU_APB_RF_AP_DOZE_SLEEP_ORG 0x10
+#define MASK_PMU_APB_RF_AUDCP_DOZE_SLEEP 0x8
+#define MASK_PMU_APB_RF_PUBCP_DOZE_SLEEP 0x4
+#define MASK_PMU_APB_RF_WTLCP_DOZE_SLEEP 0x2
+#define MASK_PMU_APB_RF_AP_DOZE_SLEEP 0x1
+#define MASK_PMU_APB_RF_AUDCP_FORCE_DOZE_SLEEP 0x8
+#define MASK_PMU_APB_RF_PUBCP_FORCE_DOZE_SLEEP 0x4
+#define MASK_PMU_APB_RF_WTLCP_FORCE_DOZE_SLEEP 0x2
+#define MASK_PMU_APB_RF_AP_FORCE_DOZE_SLEEP 0x1
+#define MASK_PMU_APB_RF_AUDCP_SYS_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_AUDCP_AUDDSP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_PUB_ACC_RDY 0x1
+#define MASK_PMU_APB_RF_PUB_CLK_RDY 0x1
+#define MASK_PMU_APB_RF_EIC_LIGHT_SLEEP_SEL 0x2
+#define MASK_PMU_APB_RF_EIC_DEEP_SLEEP_SEL 0x1
+#define MASK_PMU_APB_RF_AXI_LP_CTRL_DISABLE 0x1
+#define MASK_PMU_APB_RF_PMU_DEBUG 0xffffffff
+#define MASK_PMU_APB_RF_AUDCP_SYS_DOZE_SLEEP_CNT_CLR 0x800000
+#define MASK_PMU_APB_RF_PUBCP_DOZE_SLEEP_CNT_CLR 0x400000
+#define MASK_PMU_APB_RF_WTLCP_DOZE_SLEEP_CNT_CLR 0x200000
+#define MASK_PMU_APB_RF_AP_DOZE_SLEEP_CNT_CLR 0x100000
+#define MASK_PMU_APB_RF_APCPU_TOP_SYS_SLEEP_CNT_CLR 0x20000
+#define MASK_PMU_APB_RF_PUBCP_SYS_SLEEP_CNT_CLR 0x10000
+#define MASK_PMU_APB_RF_WTLCP_SYS_SLEEP_CNT_CLR 0x8000
+#define MASK_PMU_APB_RF_AP_SYS_SLEEP_CNT_CLR 0x4000
+#define MASK_PMU_APB_RF_AUDCP_SYS_SLEEP_CNT_CLR 0x2000
+#define MASK_PMU_APB_RF_AON_SYS_LIGHT_SLEEP_CNT_CLR 0x1000
+#define MASK_PMU_APB_RF_PUBCP_LIGHT_SLEEP_CNT_CLR 0x800
+#define MASK_PMU_APB_RF_WTLCP_LIGHT_SLEEP_CNT_CLR 0x400
+#define MASK_PMU_APB_RF_AP_LIGHT_SLEEP_CNT_CLR 0x200
+#define MASK_PMU_APB_RF_PUB_SYS_LIGHT_SLEEP_CNT_CLR 0x100
+#define MASK_PMU_APB_RF_AUDCP_SYS_LIGHT_SLEEP_CNT_CLR 0x80
+#define MASK_PMU_APB_RF_CDMA_DEEP_SLEEP_CNT_CLR 0x40
+#define MASK_PMU_APB_RF_SP_SYS_DEEP_SLEEP_CNT_CLR 0x20
+#define MASK_PMU_APB_RF_PUBCP_DEEP_SLEEP_CNT_CLR 0x10
+#define MASK_PMU_APB_RF_WTLCP_DEEP_SLEEP_CNT_CLR 0x8
+#define MASK_PMU_APB_RF_AP_DEEP_SLEEP_CNT_CLR 0x4
+#define MASK_PMU_APB_RF_PUB_DEEP_SLEEP_CNT_CLR 0x2
+#define MASK_PMU_APB_RF_AUDCP_SYS_DEEP_SLEEP_CNT_CLR 0x1
+#define MASK_PMU_APB_RF_LVDSRFPLL_REF_SEL 0x300
+#define MASK_PMU_APB_RF_EXT_XTL3_COMB_EN 0x8
+#define MASK_PMU_APB_RF_EXT_XTL2_COMB_EN 0x4
+#define MASK_PMU_APB_RF_EXT_XTL1_COMB_EN 0x2
+#define MASK_PMU_APB_RF_EXT_XTL0_COMB_EN 0x1
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_CDMA_AUTO_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_CDMA_DEEP_SLEEP_MASK 0x2000
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_CDMA_AUTO_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_CDMA_DEEP_SLEEP_MASK 0x2000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN0_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_CDMA_AUTO_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_CDMA_DEEP_SLEEP_MASK 0x2000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_PAD_OUT_XTL_EN1_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_CDMA_AUTO_DEEP_SLEEP_MASK 0x8000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_CDMA_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_DCDC_ARM0_PD_EN 0x2000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_CDMA_AUTO_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_CDMA_DEEP_SLEEP_MASK 0x2000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_CDMA_AUTO_DEEP_SLEEP_MASK 0x4000
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_CDMA_DEEP_SLEEP_MASK 0x2000
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_POL_SEL 0x1000
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_TOP_DVFS_DEEP_SLEEP_MASK 0x800
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_PLL_PD_MASK 0x400
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_EXT_XTL_PD_MASK 0x200
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_SP_SYS_DEEP_SLEEP_MASK 0x100
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_AP_DEEP_SLEEP_MASK 0x80
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_PUB_SYS_DEEP_SLEEP_MASK 0x20
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_APCPU_C7_PD_MASK 0x10
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_APCPU_TOP_PD_MASK 0x8
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_WTLCP_DEEP_SLEEP_MASK 0x4
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_PUBCP_DEEP_SLEEP_MASK 0x2
+#define MASK_PMU_APB_RF_DCXO_LC_DEEP_SLEEP_AUDCP_DEEP_SLEEP_MASK 0x1
+#define MASK_PMU_APB_RF_PD_GPU_C1_BISR_FORCE_SEL 0x40000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_BISR_FORCE_SEL 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_BISR_FORCE_SEL 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_BISR_FORCE_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_BISR_FORCE_SEL 0x4000000
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_BISR_FORCE_SEL 0x2000000
+#define MASK_PMU_APB_RF_PD_GPU_C0_BISR_FORCE_SEL 0x1000000
+#define MASK_PMU_APB_RF_PD_AP_VSP_BISR_FORCE_SEL 0x800000
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_BISR_FORCE_SEL 0x400000
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_BISR_FORCE_SEL 0x200000
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_BISR_FORCE_SEL 0x100000
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_BISR_FORCE_SEL 0x80000
+#define MASK_PMU_APB_RF_PD_AON_MEM_BISR_FORCE_SEL 0x40000
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_BISR_FORCE_SEL 0x20000
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_BISR_FORCE_SEL 0x10000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_BISR_FORCE_SEL 0x8000
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_BISR_FORCE_SEL 0x4000
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_BISR_FORCE_SEL 0x2000
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_BISR_FORCE_SEL 0x1000
+#define MASK_PMU_APB_RF_PD_AP_VDSP_BISR_FORCE_SEL 0x800
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_BISR_FORCE_SEL 0x400
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_BISR_FORCE_SEL 0x200
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_BISR_FORCE_SEL 0x100
+#define MASK_PMU_APB_RF_PD_MM_TOP_BISR_FORCE_SEL 0x80
+#define MASK_PMU_APB_RF_PD_GPU_TOP_BISR_FORCE_SEL 0x40
+#define MASK_PMU_APB_RF_PD_AP_SYS_BISR_FORCE_SEL 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_BISR_FORCE_SEL 0x10
+#define MASK_PMU_APB_RF_PD_APCPU_C3_BISR_FORCE_SEL 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_BISR_FORCE_SEL 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_BISR_FORCE_SEL 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_BISR_FORCE_SEL 0x1
+#define MASK_PMU_APB_RF_SP_SYS_MEM_ALL_SEL 0x2
+#define MASK_PMU_APB_RF_AON_MEM_SP_SYS_SEL 0x1
+#define MASK_PMU_APB_RF_INT_REQ_PWR_DOWN_CLR 0x3ff0000
+#define MASK_PMU_APB_RF_INT_REQ_PWR_UP_CLR 0x3ff
+#define MASK_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_WAIT_CNT 0xffff0000
+#define MASK_PMU_APB_RF_PUB_SYS_SLEEP_WAIT_CNT 0xffff
+#define MASK_PMU_APB_RF_PWR_ST_CLK_DIV_CFG 0xffff0000
+#define MASK_PMU_APB_RF_SLP_CTRL_CLK_DIV_CFG 0xffff
+#define MASK_PMU_APB_RF_CGM_PMU_SEL_REG 0x3
+#define MASK_PMU_APB_RF_RAM_PWR_DLY 0xff000000
+#define MASK_PMU_APB_RF_ISO_OFF_DLY 0xff0000
+#define MASK_PMU_APB_RF_CGM_ON_DLY 0xff00
+#define MASK_PMU_APB_RF_RST_ASSERT_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_C0_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C1_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C2_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C7_GIC_RST_EN 0x100
+#define MASK_PMU_APB_RF_APCPU_C6_GIC_RST_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_C5_GIC_RST_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_C4_GIC_RST_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_C3_GIC_RST_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_C2_GIC_RST_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_C1_GIC_RST_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_C0_GIC_RST_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_TOP_GIC_RST_EN 0x1
+#define MASK_PMU_APB_RF_CSI_2P2LANE_PD_REG 0x1000
+#define MASK_PMU_APB_RF_PHY_PWR_DLY 0xff0
+#define MASK_PMU_APB_RF_DSI_PD_REG 0x8
+#define MASK_PMU_APB_RF_USB2PHY_PD_REG 0x4
+#define MASK_PMU_APB_RF_CSI_4LANE_PD_REG 0x2
+#define MASK_PMU_APB_RF_CSI_2LANE_PD_REG 0x1
+#define MASK_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_SEL 0x1
+#define MASK_PMU_APB_RF_PD_APCPU_C7_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C7_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_C7_RAM_PWR_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C7_DCDC_PWR_ON_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C7_DCDC_PWR_OFF_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C2_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_APCPU_C1_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C0_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_STATE 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C7_STATE 0xff
+#define MASK_PMU_APB_RF_APCPU_L2RSTDISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C0 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C1 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C2 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE_DSLP_ENA_SOFT_RST_MASK 0x1fe
+#define MASK_PMU_APB_RF_APCPU_TOP_DSLP_ENA_SOFT_RST_MASK 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C7 0x1
+#define MASK_PMU_APB_RF_GICDISABLE 0x1
+#define MASK_PMU_APB_RF_FW_WAKEUP_DDR_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_TOP_RAM_PWR_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_CORINTH_RAM_PWR_DLY 0xff000000
+#define MASK_PMU_APB_RF_APCPU_CORE_RAM_PWR_DLY 0xff0000
+#define MASK_PMU_APB_RF_APCPU_CORE_INITIAL_DLY 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORINTH_INITIAL_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_CORE0_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_CORE1_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_CORE2_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_TOP_FORCE_DEEP_STOP 0x100
+#define MASK_PMU_APB_RF_APCPU_CORE_FORCE_STOP 0xff
+#define MASK_PMU_APB_RF_APCPU_CORE2_LOW_POWER_STATE 0xff0000
+#define MASK_PMU_APB_RF_APCPU_CORE1_LOW_POWER_STATE 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORE0_LOW_POWER_STATE 0xff
+#define MASK_PMU_APB_RF_APCPU_CORINTH_LOW_POWER_STATE 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORE7_LOW_POWER_STATE 0xff
+#define MASK_PMU_APB_RF_PD_GPU_TOP_RST_ASSERT_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_GPU_TOP_ISO_OFF_DLY 0xff
+#define MASK_PMU_APB_RF_MPLL_WAIT_CLK_DIV_CFG 0xffff
+#define MASK_PMU_APB_RF_MPLL0_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_MPLL0_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_MPLL0_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_MPLL0_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_MPLL1_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_MPLL1_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_MPLL1_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_MPLL1_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_MPLL2_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_MPLL2_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_MPLL2_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_MPLL2_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_DPLL0_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_DPLL0_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_DPLL0_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_DPLL0_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_DPLL1_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_DPLL1_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_DPLL1_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_DPLL1_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_TWPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_TWPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_TWPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_TWPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_LTEPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_LTEPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_LTEPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_LTEPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_GPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_GPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_GPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_GPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_RPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_RPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_RPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_RPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_ISPPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_ISPPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_ISPPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_ISPPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_ST_RPLL_STATE 0x38000000
+#define MASK_PMU_APB_RF_ST_GPLL_STATE 0x7000000
+#define MASK_PMU_APB_RF_ST_LTEPLL_STATE 0xe00000
+#define MASK_PMU_APB_RF_ST_TWPLL_STATE 0x1c0000
+#define MASK_PMU_APB_RF_ST_DPLL1_STATE 0x38000
+#define MASK_PMU_APB_RF_ST_DPLL0_STATE 0x7000
+#define MASK_PMU_APB_RF_ST_MPLL2_STATE 0x1c0
+#define MASK_PMU_APB_RF_ST_MPLL1_STATE 0x38
+#define MASK_PMU_APB_RF_ST_MPLL0_STATE 0x7
+#define MASK_PMU_APB_RF_ST_ISPPLL_STATE 0x7
+#define MASK_PMU_APB_RF_APCPU_TOP_RAM_SHUTDOWN_EN 0x4
+#define MASK_PMU_APB_RF_WTLCP_TGDSP_TCM_RAM_SHUTDOWN_EN 0x2
+#define MASK_PMU_APB_RF_WTLCP_LDSP_TCM_RAM_SHUTDOWN_EN 0x1
+#define MASK_PMU_APB_RF_WTLCP_HU3GE_NEST_DOMAIN_EN 0x1
+#define MASK_PMU_APB_RF_DBG_RECOV_WAIT_BUS_IDLE_EN 0x80
+#define MASK_PMU_APB_RF_DBGRSTREQ_TRIG_DBG_RECOV_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_TOP_SOFT_RST_TRIG_DBG_RECOV_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_SOFT_RST_TRIG_DBG_RECOV_EN 0x10
+#define MASK_PMU_APB_RF_DEBUG_RECOV_FORCE_TRIG 0x4
+#define MASK_PMU_APB_RF_DEBUG_RECOV_AUTO_TRIG_EN 0x2
+#define MASK_PMU_APB_RF_DBG_RECOV_RST_TYPE_SEL 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE_RST_DEASSERT_DLY 0xff000000
+#define MASK_PMU_APB_RF_APCPU_CORE_RST_ASSERT_DLY 0xff0000
+#define MASK_PMU_APB_RF_APCPU_CORINTH_RST_DEASSERT_DLY 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORINTH_RST_ASSERT_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_CORE_CGM_OFF_DLY 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORE_CGM_ON_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_INITIAL_STATE 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE_DEBUG_RECOV_STATE_CLR 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORE7_WAKEUP_FROM_DEBUG_RECOV 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_WAKEUP_FROM_DEBUG_RECOV 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_WAKEUP_FROM_DEBUG_RECOV 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_WAKEUP_FROM_DEBUG_RECOV 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_WAKEUP_FROM_DEBUG_RECOV 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_WAKEUP_FROM_DEBUG_RECOV 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_WAKEUP_FROM_DEBUG_RECOV 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_WAKEUP_FROM_DEBUG_RECOV 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE5_RAM_DSLP_EN 0x400
+#define MASK_PMU_APB_RF_APCPU_CORE4_RAM_DSLP_EN 0x200
+#define MASK_PMU_APB_RF_APCPU_SNOOP_FILTER_RAM_DSLP_EN 0x100
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P3_RAM_DSLP_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P2_RAM_DSLP_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P1_RAM_DSLP_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P0_RAM_DSLP_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_RAM_DSLP_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_RAM_DSLP_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_RAM_DSLP_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_RAM_DSLP_EN 0x1
+#define MASK_PMU_APB_RF_PD_APCPU_C7_FRC_ON_EN 0x80
+#define MASK_PMU_APB_RF_PD_APCPU_C6_FRC_ON_EN 0x40
+#define MASK_PMU_APB_RF_PD_APCPU_C5_FRC_ON_EN 0x20
+#define MASK_PMU_APB_RF_PD_APCPU_C4_FRC_ON_EN 0x10
+#define MASK_PMU_APB_RF_PD_APCPU_C3_FRC_ON_EN 0x8
+#define MASK_PMU_APB_RF_PD_APCPU_C2_FRC_ON_EN 0x4
+#define MASK_PMU_APB_RF_PD_APCPU_C1_FRC_ON_EN 0x2
+#define MASK_PMU_APB_RF_PD_APCPU_C0_FRC_ON_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE_SOFT_RST_BYPASS 0x20
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_SOFT_RST_BYPASS 0x10
+#define MASK_PMU_APB_RF_APCPU_SRST_RST_BYPASS 0x8
+#define MASK_PMU_APB_RF_CLUSTER_DBGRSTREQ_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_SOFT_RST_TYPE_SEL 0x2
+#define MASK_PMU_APB_RF_DBGRSTREQ_RST_TYPE_SEL 0x1
+#define MASK_PMU_APB_RF_APCPU_CORINTH_FUNC_RET_GATE_CLK_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE5_PCHANNEL_STATE 0xf00000
+#define MASK_PMU_APB_RF_APCPU_CORE4_PCHANNEL_STATE 0xf0000
+#define MASK_PMU_APB_RF_APCPU_CORE3_PCHANNEL_STATE 0xf000
+#define MASK_PMU_APB_RF_APCPU_CORE2_PCHANNEL_STATE 0xf00
+#define MASK_PMU_APB_RF_APCPU_CORE1_PCHANNEL_STATE 0xf0
+#define MASK_PMU_APB_RF_APCPU_CORE0_PCHANNEL_STATE 0xf
+#define MASK_PMU_APB_RF_APCPU_CORINTH_PCHANNEL_STATE 0xf00
+#define MASK_PMU_APB_RF_APCPU_CORE7_PCHANNEL_STATE 0xf0
+#define MASK_PMU_APB_RF_APCPU_CORE6_PCHANNEL_STATE 0xf
+#define MASK_PMU_APB_RF_APCPU_CORE7_SOFT_INT 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_SOFT_INT 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_SOFT_INT 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_SOFT_INT 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_SOFT_INT 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_SOFT_INT 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_SOFT_INT 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_SOFT_INT 0x1
+#define MASK_PMU_APB_RF_RAM_PD_CDMA_SYS_FRC 0x80000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_SNOOP_FILTER_FRC 0x40000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P3_FRC 0x20000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P2_FRC 0x10000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P1_FRC 0x8000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P0_FRC 0x4000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE3_FRC 0x2000000
+#define MASK_PMU_APB_RF_RAM_PD_FLAG_WTLCP_TGDSP_TCM_FRC 0x1000000
+#define MASK_PMU_APB_RF_RAM_PD_FLAG_WTLCP_LDSP_TCM_FRC 0x800000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE2_FRC 0x400000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE1_FRC 0x200000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE0_FRC 0x100000
+#define MASK_PMU_APB_RF_RAM_PD_PUBCP_SYS_FRC 0x80000
+#define MASK_PMU_APB_RF_RAM_PD_AUDCP_SYS_FRC 0x40000
+#define MASK_PMU_APB_RF_RAM_PD_AUDCP_AUDDSP_FRC 0x20000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_SYS_FRC 0x10000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_LTE_DPFEC_FRC 0x8000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_LTE_CE_FRC 0x4000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_LTE_PROC_FRC 0x2000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_TD_PROC_FRC 0x1000
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_HU3GE_B_FRC 0x800
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_HU3GE_A_FRC 0x400
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_TGDSP_CACHE_FRC 0x200
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_TGDSP_TCM_FRC 0x100
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_LDSP_CACHE_FRC 0x80
+#define MASK_PMU_APB_RF_RAM_PD_WTLCP_LDSP_TCM_FRC 0x40
+#define MASK_PMU_APB_RF_RAM_PD_AP_SYS_FRC 0x20
+#define MASK_PMU_APB_RF_RAM_PD_AP_VSP_FRC 0x10
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_TOP_FRC 0x8
+#define MASK_PMU_APB_RF_RAM_PD_MM_TOP_FRC 0x4
+#define MASK_PMU_APB_RF_RAM_PD_GPU_TOP_FRC 0x2
+#define MASK_PMU_APB_RF_RAM_PD_AP_VDSP_FRC 0x4000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE5_FRC 0x2000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE4_FRC 0x1000000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE5_FRC 0x10000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE4_FRC 0x8000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_TOP_FRC 0x4000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_SNOOP_FILTER_FRC 0x2000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P3_FRC 0x1000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P2_FRC 0x800
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P1_FRC 0x400
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P0_FRC 0x200
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE3_FRC 0x100
+#define MASK_PMU_APB_RF_RAM_SLP_FLAG_WTLCP_TGDSP_TCM_FRC 0x40
+#define MASK_PMU_APB_RF_RAM_SLP_FLAG_WTLCP_LDSP_TCM_FRC 0x20
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE2_FRC 0x10
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE1_FRC 0x8
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE0_FRC 0x4
+#define MASK_PMU_APB_RF_RAM_SLP_WTLCP_TGDSP_TCM_FRC 0x2
+#define MASK_PMU_APB_RF_RAM_SLP_WTLCP_LDSP_TCM_FRC 0x1
+#define MASK_PMU_APB_RF_PUB_DFS_FRQ_SET_DATA 0x70
+#define MASK_PMU_APB_RF_PUB_DFS_FRQ_SEL_SET 0x8
+#define MASK_PMU_APB_RF_PUB_DFS_FREQ_SEL 0x7
+#define MASK_PMU_APB_RF_PACTIVE_CORE0_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE1_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE2_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE7_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CLUSTER_SW 0x7f
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_SW_PACTIVE_EN 0x100
+#define MASK_PMU_APB_RF_APCPU_CORE7_SW_PACTIVE_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_SW_PACTIVE_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_SW_PACTIVE_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_SW_PACTIVE_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_SW_PACTIVE_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_SW_PACTIVE_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_SW_PACTIVE_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_SW_PACTIVE_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_SW_PCHANNEL_EN 0x100
+#define MASK_PMU_APB_RF_APCPU_CORE7_SW_PCHANNEL_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_SW_PCHANNEL_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_SW_PCHANNEL_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_SW_PCHANNEL_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_SW_PCHANNEL_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_SW_PCHANNEL_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_SW_PCHANNEL_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_SW_PCHANNEL_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE0_PACTIVE 0xf000
+#define MASK_PMU_APB_RF_APCPU_CORE0_PDENY 0x800
+#define MASK_PMU_APB_RF_APCPU_CORE0_PACCEPT 0x400
+#define MASK_PMU_APB_RF_MODE_ST_CORE0_CGM_EN_SW 0x200
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE0_SW 0x100
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE0_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE0_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE0_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE0_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE0_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE1_PACTIVE 0xf000
+#define MASK_PMU_APB_RF_APCPU_CORE1_PDENY 0x800
+#define MASK_PMU_APB_RF_APCPU_CORE1_PACCEPT 0x400
+#define MASK_PMU_APB_RF_MODE_ST_CORE1_CGM_EN_SW 0x200
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE1_SW 0x100
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE1_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE1_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE1_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE1_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE1_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE2_PACTIVE 0xf000
+#define MASK_PMU_APB_RF_APCPU_CORE2_PDENY 0x800
+#define MASK_PMU_APB_RF_APCPU_CORE2_PACCEPT 0x400
+#define MASK_PMU_APB_RF_MODE_ST_CORE2_CGM_EN_SW 0x200
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE2_SW 0x100
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE2_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE2_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE2_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE2_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE2_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE7_PACTIVE 0x3c00
+#define MASK_PMU_APB_RF_APCPU_CORE7_PDENY 0x200
+#define MASK_PMU_APB_RF_APCPU_CORE7_PACCEPT 0x100
+#define MASK_PMU_APB_RF_MODE_ST_CORE7_CGM_EN_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE7_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE7_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE7_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE7_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_SNOOP_FILTER_SW 0x10000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_SNOOP_FILTER_SW 0x8000000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P3_SW 0x4000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P3_SW 0x2000000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P2_SW 0x1000000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P2_SW 0x800000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P1_SW 0x400000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P1_SW 0x200000
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_L3CACHE_TAG_P0_SW 0x100000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_L3CACHE_TAG_P0_SW 0x80000
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_PACTIVE 0x7f000
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_PDENY 0x800
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_PACCEPT 0x400
+#define MASK_PMU_APB_RF_RST_APCPU_CLUSTER_WARM_SW_N 0x200
+#define MASK_PMU_APB_RF_RST_APCPU_CLUSTER_COLD_SW_N 0x100
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_PSTATE_SW 0xfe
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_WTLCP_DPFEC_NEST_DOMAIN_EN 0x1
+#define MASK_PMU_APB_RF_GPLL_GPIO_FORCE_GATING_DISABLE 0x10
+#define MASK_PMU_APB_RF_MPLL2_GPIO_FORCE_GATING_DISABLE 0x4
+#define MASK_PMU_APB_RF_MPLL1_GPIO_FORCE_GATING_DISABLE 0x2
+#define MASK_PMU_APB_RF_MPLL0_GPIO_FORCE_GATING_DISABLE 0x1
+#define MASK_PMU_APB_RF_CSI_2P2LANE_PWRON_REG 0x10
+#define MASK_PMU_APB_RF_DSI_PWRON_REG 0x8
+#define MASK_PMU_APB_RF_USB2PHY_PWRON_REG 0x4
+#define MASK_PMU_APB_RF_CSI_4LANE_PWRON_REG 0x2
+#define MASK_PMU_APB_RF_CSI_2LANE_PWRON_REG 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE7_MODE_ST_CGM_EN_DISABLE 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_MODE_ST_CGM_EN_DISABLE 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_MODE_ST_CGM_EN_DISABLE 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_MODE_ST_CGM_EN_DISABLE 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_MODE_ST_CGM_EN_DISABLE 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_MODE_ST_CGM_EN_DISABLE 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_MODE_ST_CGM_EN_DISABLE 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_MODE_ST_CGM_EN_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_DENY_TIME_THRESHOLD 0xfc0
+#define MASK_PMU_APB_RF_APCPU_CORE_DENY_TIME_THRESHOLD 0x3f
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CLUSTER_EN 0x100
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE7_EN 0x80
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE6_EN 0x40
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE5_EN 0x20
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE4_EN 0x10
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE3_EN 0x8
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE2_EN 0x4
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE1_EN 0x2
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE0_EN 0x1
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CLUSTER_CLR 0x100
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE7_CLR 0x80
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE6_CLR 0x40
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE5_CLR 0x20
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE4_CLR 0x10
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE3_CLR 0x8
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE2_CLR 0x4
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE1_CLR 0x2
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE0_CLR 0x1
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CLUSTER 0x100
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE7 0x80
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE6 0x40
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE5 0x20
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE4 0x10
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE3 0x8
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE2 0x4
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE1 0x2
+#define MASK_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE0 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE0_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE0_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE1_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE1_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE2_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE2_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE7_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE7_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_DENY_TAR_STATE 0xfc0
+#define MASK_PMU_APB_RF_APCPU_CLUSTER_DENY_PRE_STATE 0x3f
+#define MASK_PMU_APB_RF_APCPU_CSYSPWRUP_WAKEUP_EN 0xff
+#define MASK_PMU_APB_RF_DCDC_CPU1_DVFS_BLOCK_SHUTDOWN_EN 0x2
+#define MASK_PMU_APB_RF_DCDC_CPU0_DVFS_BLOCK_SHUTDOWN_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE7_OFF_EMU_CLR_INT_DISABLE_EN 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_OFF_EMU_CLR_INT_DISABLE_EN 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_OFF_EMU_CLR_INT_DISABLE_EN 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_OFF_EMU_CLR_INT_DISABLE_EN 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_OFF_EMU_CLR_INT_DISABLE_EN 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_OFF_EMU_CLR_INT_DISABLE_EN 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_OFF_EMU_CLR_INT_DISABLE_EN 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_OFF_EMU_CLR_INT_DISABLE_EN 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE5_RAM_FRC_ON 0x400
+#define MASK_PMU_APB_RF_APCPU_CORE4_RAM_FRC_ON 0x200
+#define MASK_PMU_APB_RF_APCPU_CORE3_RAM_FRC_ON 0x100
+#define MASK_PMU_APB_RF_APCPU_SNOOP_FILTER_RAM_FRC_ON 0x80
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P3_RAM_FRC_ON 0x40
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P2_RAM_FRC_ON 0x20
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P1_RAM_FRC_ON 0x10
+#define MASK_PMU_APB_RF_APCPU_L3CACHE_TAG_P0_RAM_FRC_ON 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_RAM_FRC_ON 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_RAM_FRC_ON 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_RAM_FRC_ON 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE7_OFF_EMU_TO_OFF 0x80
+#define MASK_PMU_APB_RF_APCPU_CORE6_OFF_EMU_TO_OFF 0x40
+#define MASK_PMU_APB_RF_APCPU_CORE5_OFF_EMU_TO_OFF 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_OFF_EMU_TO_OFF 0x10
+#define MASK_PMU_APB_RF_APCPU_CORE3_OFF_EMU_TO_OFF 0x8
+#define MASK_PMU_APB_RF_APCPU_CORE2_OFF_EMU_TO_OFF 0x4
+#define MASK_PMU_APB_RF_APCPU_CORE1_OFF_EMU_TO_OFF 0x2
+#define MASK_PMU_APB_RF_APCPU_CORE0_OFF_EMU_TO_OFF 0x1
+#define MASK_PMU_APB_RF_ALL_PLL_PD_RCO_BYP 0x1
+#define MASK_PMU_APB_RF_SP_PWR_PD_AON_MEM_BYP 0x2
+#define MASK_PMU_APB_RF_SP_PWR_PD_SP_MEM_BYP 0x1
+#define MASK_PMU_APB_RF_LPDDR3_DPLL1_CNT_DONE_BYP 0x1
+#define MASK_PMU_APB_RF_SP_SRAM_RCO_SYS_SEL 0x8
+#define MASK_PMU_APB_RF_SP_SRAM_XTLBUF0_SYS_SEL 0x4
+#define MASK_PMU_APB_RF_AON_SRAM_RCO_SYS_SEL 0x2
+#define MASK_PMU_APB_RF_AON_SRAM_XTLBUF0_SYS_SEL 0x1
+#define MASK_PMU_APB_RF_WDG_RST_TRIG_DBG_RECOV_EN 0x1
+#define MASK_PMU_APB_RF_PD_CDMA_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_CDMA_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_CDMA_DEEP_STOP_BYP 0x1
+#define MASK_PMU_APB_RF_CDMA_CLP_CLK_TOP 0x4
+#define MASK_PMU_APB_RF_CDMA_DO_WAKE_REQ 0x2
+#define MASK_PMU_APB_RF_CDMA_1X_WAKE_REQ 0x1
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_PWR_CTRL_SEL 0x100
+#define MASK_PMU_APB_RF_CDMA_1X_SLP_O 0x80
+#define MASK_PMU_APB_RF_CDMA_DO_SLP_O 0x40
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_SHUTDOWN_M_B 0x20
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_ST_ISO_REG 0x10
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_ST_SHUTDOWN_D_B_REG 0x8
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_ST_SHUTDOWN_M_B_REG 0x4
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_ST_MEM_PD_REG 0x2
+#define MASK_PMU_APB_RF_PD_CDMA_PROC1_ST_MEM_RET_REG 0x1
+#define MASK_PMU_APB_RF_PD_APCPU_C0_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C1_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C2_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_TOP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_AP_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_GPU_TOP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_MM_TOP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_CE_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_AP_VSP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_LDSP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_TGDSP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_PUBCP_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_LTE_PROC_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_WTLCP_TD_PROC_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_AUDCP_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_PUB_SYS_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_AUDCP_AUDDSP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_APCPU_TOP_SYS_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AP_SYS_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_WTLCP_SYS_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUBCP_SYS_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AUDCP_SYS_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUB_SYS_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AP_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_SP_SYS_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_WTLCP_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUBCP_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AUDCP_SYS_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AP_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_WTLCP_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUBCP_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AUDCP_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AON_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AUDCP_SYS_SRST_BUSY 0x40
+#define MASK_PMU_APB_RF_AP_SYS_SRST_BUSY 0x20
+#define MASK_PMU_APB_RF_APCPU_SYS_SRST_BUSY 0x10
+#define MASK_PMU_APB_RF_GPU_SYS_SRST_BUSY 0x8
+#define MASK_PMU_APB_RF_MM_SYS_SRST_BUSY 0x4
+#define MASK_PMU_APB_RF_WTLCP_SYS_SRST_BUSY 0x2
+#define MASK_PMU_APB_RF_PUBCP_SYS_SRST_BUSY 0x1
+#define MASK_PMU_APB_RF_REG_AUDCP_SRST_FRC_LP_ACK 0x40
+#define MASK_PMU_APB_RF_REG_AP_SRST_FRC_LP_ACK 0x20
+#define MASK_PMU_APB_RF_REG_APCPU_SRST_FRC_LP_ACK 0x10
+#define MASK_PMU_APB_RF_REG_GPU_SRST_FRC_LP_ACK 0x8
+#define MASK_PMU_APB_RF_REG_MM_SRST_FRC_LP_ACK 0x4
+#define MASK_PMU_APB_RF_REG_WTLCP_SRST_FRC_LP_ACK 0x2
+#define MASK_PMU_APB_RF_REG_PUBCP_SRST_FRC_LP_ACK 0x1
+#define MASK_PMU_APB_RF_SOFT_RST_SEL 0xff
+#define MASK_PMU_APB_RF_REG_PUBCP_WTLCP_ASYNC_BRIDGE_W_FORCE_REQ 0x200
+#define MASK_PMU_APB_RF_REG_PUBCP_WTLCP_PWR_HS_ACK 0x100
+#define MASK_PMU_APB_RF_REG_AUDCP_SYS_DDR_PWR_HS_ACK 0x80
+#define MASK_PMU_APB_RF_REG_PUBCP_SYS_DDR_PWR_HS_ACK 0x40
+#define MASK_PMU_APB_RF_REG_WTLCP_SYS_DDR_PWR_HS_ACK 0x20
+#define MASK_PMU_APB_RF_REG_APCPU_TOP_DDR_PWR_HS_ACK 0x10
+#define MASK_PMU_APB_RF_REG_AP_SYS_DDR_PWR_HS_ACK 0x8
+#define MASK_PMU_APB_RF_REG_MM_SYS_DDR_PWR_HS_ACK 0x4
+#define MASK_PMU_APB_RF_REG_GPU_SYS_DDR_PWR_HS_ACK 0x2
+#define MASK_PMU_APB_RF_REG_AON_SYS_DDR_PWR_HS_ACK 0x1
+#define MASK_PMU_APB_RF_CSI_2P2LANE_PWR_CNT_DONE 0x8
+#define MASK_PMU_APB_RF_CSI_4LANE_PWR_CNT_DONE 0x4
+#define MASK_PMU_APB_RF_CSI_2LANE_PWR_CNT_DONE 0x2
+#define MASK_PMU_APB_RF_DSI_PWR_CNT_DONE 0x1
+#define MASK_PMU_APB_RF_PD_AP_SYS_DBG_SHUTDOWN_EN 0x1
+#define MASK_PMU_APB_RF_EIC_SYS_SEL 0x3
+#define MASK_PMU_APB_RF_DDR_SLP_CTRL_STATE 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C7_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_APCPU_TOP_DEEP_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_APCPU_TOP_LIGHT_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AP_DOZE_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_WTLCP_DOZE_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PUBCP_DOZE_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_AUDCP_DOZE_SLEEP_CNT 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C3_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C3_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C3_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C4_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C4_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_APCPU_C5_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C5_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_AP_VDSP_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_AP_VDSP_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_AP_VDSP_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_AP_VDSP_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_AP_VDSP_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_AP_VDSP_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_APCPU_C3_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C4_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C5_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_APCPU_C6_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_AP_VDSP_CORE_INT_DISABLE 0x1
+#define MASK_PMU_APB_RF_CORE_WFI_MARK_CLR 0xff00
+#define MASK_PMU_APB_RF_CORE_WFI_MARK 0xff
+#define MASK_PMU_APB_RF_APCPU_C6_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_AP_VDSP_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C3_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C4_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_APCPU_C5_DSLP_ENA 0x1
+#define MASK_PMU_APB_RF_PD_APCPU_C6_WFI_SHUTDOWN_EN 0x20000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_DBG_SHUTDOWN_EN 0x10000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_PD_SEL 0x8000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_FORCE_SHUTDOWN 0x2000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_AUTO_SHUTDOWN_EN 0x1000000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_PWR_ON_DLY 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C6_PWR_ON_SEQ_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C6_ISO_ON_DLY 0xff
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_ISO_ON_DLY 0xff000000
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_SHUTDOWN_WINDOW 0xff0000
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_PWR_ON_DLY 0xff00
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_PWR_OFF_DLY 0xff
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_STATE 0xf000
+#define MASK_PMU_APB_RF_PD_DCDC_CPU1_PWR_SEQ_DLY 0xff0
+#define MASK_PMU_APB_RF_DCDC_CPU1_FRC_ON 0x3
+#define MASK_PMU_APB_RF_PD_APCPU_C3_STATE 0xff000000
+#define MASK_PMU_APB_RF_PD_APCPU_C4_STATE 0xff0000
+#define MASK_PMU_APB_RF_PD_APCPU_C5_STATE 0xff00
+#define MASK_PMU_APB_RF_PD_APCPU_C6_STATE 0xff
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C3 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C4 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C5 0x1
+#define MASK_PMU_APB_RF_APCPU_VINITHI_C6 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE3_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_CORE4_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_CORE5_SIMD_RET_MODE 0x7
+#define MASK_PMU_APB_RF_APCPU_CORE6_LOW_POWER_STATE 0xff000000
+#define MASK_PMU_APB_RF_APCPU_CORE5_LOW_POWER_STATE 0xff0000
+#define MASK_PMU_APB_RF_APCPU_CORE4_LOW_POWER_STATE 0xff00
+#define MASK_PMU_APB_RF_APCPU_CORE3_LOW_POWER_STATE 0xff
+#define MASK_PMU_APB_RF_PACTIVE_CORE3_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE4_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE5_SW 0xf
+#define MASK_PMU_APB_RF_PACTIVE_CORE6_SW 0xf
+#define MASK_PMU_APB_RF_APCPU_CORE3_PACTIVE 0xf000
+#define MASK_PMU_APB_RF_APCPU_CORE3_PDENY 0x800
+#define MASK_PMU_APB_RF_APCPU_CORE3_PACCEPT 0x400
+#define MASK_PMU_APB_RF_MODE_ST_CORE3_CGM_EN_SW 0x200
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE3_SW 0x100
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE3_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE3_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE3_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE3_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE3_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE4_SW 0x8000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE4_SW 0x4000
+#define MASK_PMU_APB_RF_APCPU_CORE4_PACTIVE 0x3c00
+#define MASK_PMU_APB_RF_APCPU_CORE4_PDENY 0x200
+#define MASK_PMU_APB_RF_APCPU_CORE4_PACCEPT 0x100
+#define MASK_PMU_APB_RF_MODE_ST_CORE4_CGM_EN_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE4_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE4_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE4_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE4_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_RAM_RET_APCPU_CORE5_SW 0x8000
+#define MASK_PMU_APB_RF_RAM_PD_APCPU_CORE5_SW 0x4000
+#define MASK_PMU_APB_RF_APCPU_CORE5_PACTIVE 0x3c00
+#define MASK_PMU_APB_RF_APCPU_CORE5_PDENY 0x200
+#define MASK_PMU_APB_RF_APCPU_CORE5_PACCEPT 0x100
+#define MASK_PMU_APB_RF_MODE_ST_CORE5_CGM_EN_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE5_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE5_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE5_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE5_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE6_PACTIVE 0x3c00
+#define MASK_PMU_APB_RF_APCPU_CORE6_PDENY 0x200
+#define MASK_PMU_APB_RF_APCPU_CORE6_PACCEPT 0x100
+#define MASK_PMU_APB_RF_MODE_ST_CORE6_CGM_EN_SW 0x80
+#define MASK_PMU_APB_RF_RST_APCPU_CORE6_WARM_SW_N 0x40
+#define MASK_PMU_APB_RF_RST_APCPU_CORE6_COLD_SW_N 0x20
+#define MASK_PMU_APB_RF_APCPU_CORE6_PSTATE_SW 0x1e
+#define MASK_PMU_APB_RF_APCPU_CORE6_PREQ_SW 0x1
+#define MASK_PMU_APB_RF_APCPU_CORE3_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE3_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE4_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE4_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE5_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE5_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_APCPU_CORE6_DENY_TAR_STATE 0x3e0
+#define MASK_PMU_APB_RF_APCPU_CORE6_DENY_PRE_STATE 0x1f
+#define MASK_PMU_APB_RF_PD_APCPU_C3_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C4_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C5_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_AP_VDSP_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_PD_APCPU_C6_SHUTDOWN_MARK 0xf
+#define MASK_PMU_APB_RF_MEM_AUTO_SLP_EN1 0xffffffff
+#define MASK_PMU_APB_RF_MEM_AUTO_SD_EN1 0xffffffff
+#define MASK_PMU_APB_RF_MEM_SLP_CFG1 0xffffffff
+#define MASK_PMU_APB_RF_MEM_SD_CFG1 0xffffffff
+#define MASK_PMU_APB_RF_PD_GPU_C0_MEM_PD_REG 0x200
+#define MASK_PMU_APB_RF_PD_GPU_C0_ISO_REG 0x100
+#define MASK_PMU_APB_RF_PD_GPU_C0_PWR_CTRL_SEL 0x80
+#define MASK_PMU_APB_RF_PD_GPU_C0_PDCA_D_B_REG 0x40
+#define MASK_PMU_APB_RF_PD_GPU_C0_PDCA_M_B_REG 0x20
+#define MASK_PMU_APB_RF_PD_GPU_C1_MEM_PD_REG 0x10
+#define MASK_PMU_APB_RF_PD_GPU_C1_ISO_REG 0x8
+#define MASK_PMU_APB_RF_PD_GPU_C1_PWR_CTRL_SEL 0x4
+#define MASK_PMU_APB_RF_PD_GPU_C1_PDCA_D_B_REG 0x2
+#define MASK_PMU_APB_RF_PD_GPU_C1_PDCA_M_B_REG 0x1
+#define MASK_PMU_APB_RF_EPPLL_CDMA_SEL 0x80000
+#define MASK_PMU_APB_RF_EPPLL_CDMA_AUTO_SEL 0x40000
+#define MASK_PMU_APB_RF_EPPLL_CDMA2PMU_AUTO_SEL 0x20000
+#define MASK_PMU_APB_RF_XTL0_ETC_SEL 0x10000
+#define MASK_PMU_APB_RF_XTL1_ETC_SEL 0x8000
+#define MASK_PMU_APB_RF_RCO_ETC_SEL 0x4000
+#define MASK_PMU_APB_RF_XTLBUF0_ETC_SEL 0x2000
+#define MASK_PMU_APB_RF_XTLBUF1_ETC_SEL 0x1000
+#define MASK_PMU_APB_RF_ETC_SLEEP_XTL_ON 0x800
+#define MASK_PMU_APB_RF_EPPLL_REF_SEL 0x400
+#define MASK_PMU_APB_RF_EPPLL_FRC_OFF 0x200
+#define MASK_PMU_APB_RF_EPPLL_FRC_ON 0x100
+#define MASK_PMU_APB_RF_EPPLL_TOP_DVFS_SEL 0x80
+#define MASK_PMU_APB_RF_EPPLL_ETC_SEL 0x40
+#define MASK_PMU_APB_RF_EPPLL_SP_SYS_SEL 0x20
+#define MASK_PMU_APB_RF_EPPLL_PUB_SYS_SEL 0x10
+#define MASK_PMU_APB_RF_EPPLL_AUDCP_SEL 0x8
+#define MASK_PMU_APB_RF_EPPLL_PUBCP_SEL 0x4
+#define MASK_PMU_APB_RF_EPPLL_WTLCP_SEL 0x2
+#define MASK_PMU_APB_RF_EPPLL_AP_SEL 0x1
+#define MASK_PMU_APB_RF_EPPLL_RST_CTRL_BYPASS 0x1000000
+#define MASK_PMU_APB_RF_EPPLL_DELAY_PWR_ON 0xff0000
+#define MASK_PMU_APB_RF_EPPLL_DELAY_EN_OFF 0xff00
+#define MASK_PMU_APB_RF_EPPLL_DELAY_RST_ASSERT 0xff
+#define MASK_PMU_APB_RF_DORMANT 0x40000000
+#define MASK_PMU_APB_RF_ETC_DEEP_SLEEP_REG 0x20000000
+#define MASK_PMU_APB_RF_ETC_POWER_CTRL_SEL 0x10000000
+#define MASK_PMU_APB_RF_ETC_SLEEP_ENA 0x8000000
+#define MASK_PMU_APB_RF_PD_ETC_FORCE_SHUTDOWN 0x4000000
+#define MASK_PMU_APB_RF_PD_ETC_AUTO_SHUTDOWN_EN 0x2000000
+#define MASK_PMU_APB_RF_ETC_EN 0x1000000
+#define MASK_PMU_APB_RF_ETC_PWR_OFF_DLY 0xff0000
+#define MASK_PMU_APB_RF_ETC_RST_DLY 0xff00
+#define MASK_PMU_APB_RF_ETC_PWR_WAIT_CNT 0xff
+#define MASK_PMU_APB_RF_ETC_SLP_STATE 0x1e000000
+#define MASK_PMU_APB_RF_PD_ETC_DEEP_SLEEP 0x1000000
+#define MASK_PMU_APB_RF_ETC_DEEP_SLEEP 0x800000
+#define MASK_PMU_APB_RF_PD_ETC_STATE 0x7c0000
+#define MASK_PMU_APB_RF_ETC_READY 0x20000
+#define MASK_PMU_APB_RF_PD_ETC_CGM_EN 0x10000
+#define MASK_PMU_APB_RF_ETC_ISO_DLY 0xff00
+#define MASK_PMU_APB_RF_ETC_SHUTDOWN_WAIT_DLY 0xff
+#define MASK_PMU_APB_RF_ETC_STANDBY_DLY 0xff000000
+#define MASK_PMU_APB_RF_ETC_DORMANT_DLY 0xff0000
+#define MASK_PMU_APB_RF_ETC_PWR_ON_DLY 0xff00
+#define MASK_PMU_APB_RF_ETC_PWR_ON_SEQ_DLY 0xff
+#define MASK_PMU_APB_RF_ETC_CGM_EN_REG 0x10000000
+#define MASK_PMU_APB_RF_RESET_BAR_REG 0x8000000
+#define MASK_PMU_APB_RF_DORMANT_REG 0x4000000
+#define MASK_PMU_APB_RF_AVDD_ISOB_AON_REG 0x800000
+#define MASK_PMU_APB_RF_DVDD_ISOB_AON_REG 0x400000
+#define MASK_PMU_APB_RF_ETC_CGM_26M_EN_REG 0x200000
+#define MASK_PMU_APB_RF_DVDD_OFFB_AON_REG 0x100000
+#define MASK_PMU_APB_RF_PVDD_OFFB_AON_REG 0x80000
+#define MASK_PMU_APB_RF_AVDD_OFFB_AON_REG 0x40000
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_CGM_EN 0x20000
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_CGM_26M_EN 0x10000
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_DORMANT 0x8000
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_AVDDISOB 0x4000
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_AVDDOFFB 0x800
+#define MASK_PMU_APB_RF_ETC_PIN_SEL_PVDDOFFB 0x400
+#define MASK_PMU_APB_RF_ETC_READY_DLY 0x3ff
+#define MASK_PMU_APB_RF_EPLL_CLKOUT_26M_EN_SEL 0x8000000
+#define MASK_PMU_APB_RF_ETC_PWR_PD_EN 0x4000000
+#define MASK_PMU_APB_RF_EPLL_DIV32_CLKOUT_EN_SEL 0x2000000
+#define MASK_PMU_APB_RF_EPLL_DIV32_CLKOUT_EN_REG 0x1000000
+#define MASK_PMU_APB_RF_EPLL_CLKOUT_EN_SEL 0x800000
+#define MASK_PMU_APB_RF_EPLL_CLKOUT_EN_REG 0x400000
+#define MASK_PMU_APB_RF_EPLL_BG_PD_REG 0x200000
+#define MASK_PMU_APB_RF_EPLL_BG_PD_SEL 0x100000
+#define MASK_PMU_APB_RF_MPLL0_ETC_SEL 0x80000
+#define MASK_PMU_APB_RF_MPLL1_ETC_SEL 0x40000
+#define MASK_PMU_APB_RF_MPLL2_ETC_SEL 0x20000
+#define MASK_PMU_APB_RF_DPLL0_ETC_SEL 0x10000
+#define MASK_PMU_APB_RF_DPLL1_ETC_SEL 0x8000
+#define MASK_PMU_APB_RF_TWPLL_ETC_SEL 0x4000
+#define MASK_PMU_APB_RF_CPPLL_ETC_SEL 0x2000
+#define MASK_PMU_APB_RF_GPLL_ETC_SEL 0x1000
+#define MASK_PMU_APB_RF_EPLL_ETC_SEL 0x800
+#define MASK_PMU_APB_RF_RPLL_ETC_SEL 0x400
+#define MASK_PMU_APB_RF_ISPPLL_ETC_SEL 0x200
+#define MASK_PMU_APB_RF_LTEPLL_ETC_SEL 0x100
+#define MASK_PMU_APB_RF_EPPLL_WAIT_CNT 0xff
+#define MASK_DBG_APB_RF_BUS_BUSY_TIMER_EN 0x100
+#define MASK_DBG_APB_RF_BUS_BUSY_TIMER_DIVIDER 0xff
+#define MASK_DBG_APB_RF_APCPU_CSSYS_EN 0x8
+#define MASK_DBG_APB_RF_APCPU_APB_TRANS_CSYSREQ 0x4
+#define MASK_DBG_APB_RF_CPWRUPREQ_CDBGPWRUP 0x2
+#define MASK_DBG_APB_RF_DBGCONNECTED 0x1
+#define MASK_DBG_APB_RF_CSYSPWRUPREQ_RCO_EN 0x8
+#define MASK_DBG_APB_RF_CSYSPWRUPREQ_CR5_EN 0x4
+#define MASK_DBG_APB_RF_CSYSPWRUPREQ_AON_CM4_EN 0x2
+#define MASK_DBG_APB_RF_CSYSPWRUPREQ_APCPU_EN 0x1
+#define MASK_DBG_APB_RF_TPIU2SERDES_CGM_EN 0x20000
+#define MASK_DBG_APB_RF_CSSYS_EN_REG 0x10000
+#define MASK_DBG_APB_RF_APCPU_DAP_EN_REG 0x8000
+#define MASK_DBG_APB_RF_CROSS_TRIGGER_EN 0x4000
+#define MASK_DBG_APB_RF_APCPU_MTX_SOFT_RST 0x2000
+#define MASK_DBG_APB_RF_APCPU_AB_SOFT_RST 0x1000
+#define MASK_DBG_APB_RF_APCPU_APB_TRANS_BLKR_BYPASS 0x800
+#define MASK_DBG_APB_RF_APCPU_CORINTH_DEBUG_EN_FOR_LP 0x400
+#define MASK_DBG_APB_RF_AUTO_REG_SAVE_SEL 0x200
+#define MASK_DBG_APB_RF_AUTO_REG_SAVE_SOFT_TRIG 0x100
+#define MASK_DBG_APB_RF_AUTO_REG_SAVE_EN 0x80
+#define MASK_DBG_APB_RF_CSSYS_SOFT_RST_EN 0x40
+#define MASK_DBG_APB_RF_AON_MTX_SOFT_RST_EN 0x20
+#define MASK_DBG_APB_RF_DAP_SOFT_RST_EN 0x10
+#define MASK_DBG_APB_RF_APCPU_CSSYS_EN_REG 0x8
+#define MASK_DBG_APB_RF_APCPU_DBG_CONNECTED_SW 0x4
+#define MASK_DBG_APB_RF_APCPU_DBG_CONNECTED_CTRL 0x3
+#define MASK_DBG_APB_RF_STM_SOFT_RESET 0x1
+#define MASK_DBG_APB_RF_AON_APB_CLK_RCO_SEL 0xe00
+#define MASK_DBG_APB_RF_CSSYS_CLK_RCO_SEL 0x1c0
+#define MASK_DBG_APB_RF_DAP_CLK_RCO_SEL 0x38
+#define MASK_DBG_APB_RF_AON_APB_CLK_RCO_CTRL_EN 0x4
+#define MASK_DBG_APB_RF_CSSYS_CLK_RCO_CTRL_EN 0x2
+#define MASK_DBG_APB_RF_DAP_CLK_RCO_CTRL_EN 0x1
+#define MASK_DBG_APB_RF_REG_DBG_SYS_SEL_B 0xff00
+#define MASK_DBG_APB_RF_REG_DBG_SYS_SEL_A 0xff
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_GPU 0xff000000
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_MM 0xff0000
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_AP 0xff00
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_APCPU 0xff
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_AON 0xff0000
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_AON_LP 0xff00
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_PUB 0xff
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_MDAR 0xff000000
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_WTLCP 0xff0000
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_PUBCP 0xff00
+#define MASK_DBG_APB_RF_REG_DBG_BUS_SEL_AUDCP 0xff
+#define MASK_DBG_APB_RF_REG_DBG_MOD_SEL_LP 0xff000000
+#define MASK_DBG_APB_RF_REG_DBG_MOD_SEL_APCPU 0xff0000
+#define MASK_DBG_APB_RF_REG_DBG_MOD_SEL_WTLCP 0xff00
+#define MASK_DBG_APB_RF_REG_DBG_MOD_SEL_PUBCP 0xff
+#define MASK_DBG_APB_RF_DBG_BUS4_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS3_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS2_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS1_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS0_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS9_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS8_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS7_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS6_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS5_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS14_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS13_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS12_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS11_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS10_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS19_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS18_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS17_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS16_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS15_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS24_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS23_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS22_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS21_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS20_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS29_SEL 0x3f000000
+#define MASK_DBG_APB_RF_DBG_BUS28_SEL 0xfc0000
+#define MASK_DBG_APB_RF_DBG_BUS27_SEL 0x3f000
+#define MASK_DBG_APB_RF_DBG_BUS26_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS25_SEL 0x3f
+#define MASK_DBG_APB_RF_DBG_BUS31_SEL 0xfc0
+#define MASK_DBG_APB_RF_DBG_BUS30_SEL 0x3f
+#define MASK_DBG_APB_RF_PAD_DBG_BUS_DATA_A 0xffffffff
+#define MASK_DBG_APB_RF_PAD_DBG_BUS_DATA_B 0xffffffff
+#define MASK_DBG_APB_RF_PAD_DBG_BUS_DATA_OUT 0xffffffff
+#define MASK_DBG_APB_RF_AWADDR3_MATCH_INT_EN 0x8
+#define MASK_DBG_APB_RF_AWADDR2_MATCH_INT_EN 0x4
+#define MASK_DBG_APB_RF_AWADDR1_MATCH_INT_EN 0x2
+#define MASK_DBG_APB_RF_AWADDR0_MATCH_INT_EN 0x1
+#define MASK_DBG_APB_RF_AWADDR3_MATCH_INT_CLR 0x8
+#define MASK_DBG_APB_RF_AWADDR2_MATCH_INT_CLR 0x4
+#define MASK_DBG_APB_RF_AWADDR1_MATCH_INT_CLR 0x2
+#define MASK_DBG_APB_RF_AWADDR0_MATCH_INT_CLR 0x1
+#define MASK_DBG_APB_RF_AWADDR3_MATCH_INT_RAW 0x8
+#define MASK_DBG_APB_RF_AWADDR2_MATCH_INT_RAW 0x4
+#define MASK_DBG_APB_RF_AWADDR1_MATCH_INT_RAW 0x2
+#define MASK_DBG_APB_RF_AWADDR0_MATCH_INT_RAW 0x1
+#define MASK_DBG_APB_RF_AWADDR3_MATCH_INT_STAT 0x8
+#define MASK_DBG_APB_RF_AWADDR2_MATCH_INT_STAT 0x4
+#define MASK_DBG_APB_RF_AWADDR1_MATCH_INT_STAT 0x2
+#define MASK_DBG_APB_RF_AWADDR0_MATCH_INT_STAT 0x1
+#define MASK_DBG_APB_RF_ETR_AXI_MON_AWADDR0 0xfffffff
+#define MASK_DBG_APB_RF_ETR_AXI_MON_AWADDR1 0xfffffff
+#define MASK_DBG_APB_RF_ETR_AXI_MON_AWADDR2 0xfffffff
+#define MASK_DBG_APB_RF_ETR_AXI_MON_AWADDR3 0xfffffff
+#define MASK_REG_FW1_AON_XTL0_REL_CFG_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT2_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT1_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT0_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_XTL_WAIT_CNT_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_AP_WAKEUP_POR_CFG_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_PD_PUB_SYS_CFG_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_PD_CDMA_SYS_CFG_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_PUBCP_FRC_STOP_REQ_FOR_WTL_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_PD_AUDCP_SYS_CFG_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_PD_AUDCP_AUDDSP_CFG_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_PD_PUBCP_SYS_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_PD_WTLCP_SYS_CFG_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_WTLCP_TD_PROC_CFG_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_PROC_CFG_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_B_CFG_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_A_CFG_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_PD_WTLCP_TGDSP_CFG_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_PD_WTLCP_LDSP_CFG_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_DPFEC_CFG_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_CE_CFG_RD_SEC 0x800
+#define MASK_REG_FW1_AON_PD_GPU_TOP_CFG0_RD_SEC 0x400
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_CFG1_RD_SEC 0x200
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_CFG0_RD_SEC 0x100
+#define MASK_REG_FW1_AON_PD_MM_TOP_CFG_RD_SEC 0x80
+#define MASK_REG_FW1_AON_PD_AP_SYS_CFG_RD_SEC 0x40
+#define MASK_REG_FW1_AON_PD_AP_VSP_CFG_RD_SEC 0x20
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG2_RD_SEC 0x10
+#define MASK_REG_FW1_AON_PD_APCPU_C2_CFG_RD_SEC 0x8
+#define MASK_REG_FW1_AON_PD_APCPU_C1_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_PD_APCPU_C0_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG_RD_SEC 0x1
+#define MASK_REG_FW1_AON_BISR_DONE_STATUS_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_CLK26M_SEL_CFG_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_DDR_PHY_RET_CFG_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_DDR_OP_MODE_CFG_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_PWR_STATUS3_DBG_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_DDR_CHN_SLEEP_CTRL1_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_DDR_CHN_SLEEP_CTRL0_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_CPPLL_RST_CTRL_CFG_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_CPPLL_REL_CFG_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_POLL1_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_POLL0_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_PUB_SYS_SLEEP_BYPASS_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_SLEEP_STATUS_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_DDR_SLEEP_CTRL_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_SLEEP_CTRL_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PUB_SYS_AUTO_LIGHT_SLEEP_ENABLE_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_PWR_STATUS2_DBG_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_PWR_STATUS1_DBG_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_PWR_STATUS0_DBG_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PWR_STATUS4_DBG_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_CP_SLP_STATUS_DBG0_RD_SEC 0x800
+#define MASK_REG_FW1_AON_CP_SOFT_RST_RD_SEC 0x400
+#define MASK_REG_FW1_AON_RPLL_REL_CFG_RD_SEC 0x200
+#define MASK_REG_FW1_AON_GPLL_REL_CFG_RD_SEC 0x100
+#define MASK_REG_FW1_AON_TWPLL_REL_CFG_RD_SEC 0x80
+#define MASK_REG_FW1_AON_LTEPLL_REL_CFG_RD_SEC 0x40
+#define MASK_REG_FW1_AON_DPLL1_REL_CFG_RD_SEC 0x20
+#define MASK_REG_FW1_AON_DPLL0_REL_CFG_RD_SEC 0x10
+#define MASK_REG_FW1_AON_XTLBUF1_REL_CFG_RD_SEC 0x8
+#define MASK_REG_FW1_AON_XTLBUF0_REL_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_ISPPLL_REL_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_XTL1_REL_CFG_RD_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_C1_CORE_INT_DISABLE_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_C0_CORE_INT_DISABLE_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_PUBCP_CORE_INT_DISABLE_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_WTLCP_LDSP_CORE_INT_DISABLE_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_WTLCP_TGDSP_CORE_INT_DISABLE_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_AUDCP_SYS_CORE_INT_DISABLE_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_WAKEUP_LOCK_EN_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_MEM_AUTO_SD_CFG_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_MEM_AUTO_SLP_CFG_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_MPLL2_REL_CFG_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_MPLL1_REL_CFG_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_MPLL0_REL_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_RCO_CNT_WAIT_CFG_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_RCO_REL_CFG_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PWR_CNT_WAIT_CFG1_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PWR_CNT_WAIT_CFG0_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_SP_SYS_HOLD_CGM_EN_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_CORE_WAKEUP_EN_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_MEM_SD_CFG_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_MEM_SLP_CFG_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_SLEEP_XTLON_CTRL_RD_SEC 0x800
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG3_RD_SEC 0x400
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG2_RD_SEC 0x200
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG1_RD_SEC 0x100
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG0_RD_SEC 0x80
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG3_RD_SEC 0x40
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG2_RD_SEC 0x20
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG1_RD_SEC 0x10
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG0_RD_SEC 0x8
+#define MASK_REG_FW1_AON_BISR_EN_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_BISR_BYP_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_BISR_BUSY_STATUS_RD_SEC 0x1
+#define MASK_REG_FW1_AON_PAD_OUT_XTL_EN1_CFG_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_PAD_OUT_XTL_EN0_CFG_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_PAD_OUT_CHIP_SLEEP_CFG_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_EXT_XTL_EN_CTRL_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_LVDSRFPLL_REL_CFG_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_SLEEP_CNT_CLR_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_PMU_DEBUG_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_AXI_LP_CTRL_DISABLE_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_EIC_SEL_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_PUB_CLK_RDY_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_PUB_ACC_RDY_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_AUDCP_AUDDSP_DSLP_ENA_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_AUDCP_SYS_DSLP_ENA_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_DOZE_FORCE_SLEEP_CTRL_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_DOZE_SLEEP_MON_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_DOZE_SLEEP_ENABLE_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_MON_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_ENABLE_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_WAKEUP_EN_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PUB_DEEP_SLEEP_WAKEUP_EN_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_PUB_DEEP_SLEEP_ENA_RD_SEC 0x800
+#define MASK_REG_FW1_AON_SP_SYS_DSLP_ENA_RD_SEC 0x400
+#define MASK_REG_FW1_AON_APCPU_TOP_DSLP_ENA_RD_SEC 0x200
+#define MASK_REG_FW1_AON_WTLCP_DSLP_ENA_RD_SEC 0x100
+#define MASK_REG_FW1_AON_PUBCP_DSLP_ENA_RD_SEC 0x80
+#define MASK_REG_FW1_AON_AP_DSLP_ENA_RD_SEC 0x40
+#define MASK_REG_FW1_AON_WTLCP_LDSP_DSLP_ENA_RD_SEC 0x20
+#define MASK_REG_FW1_AON_WTLCP_TGDSP_DSLP_ENA_RD_SEC 0x10
+#define MASK_REG_FW1_AON_CDMA_DSLP_ENA_RD_SEC 0x8
+#define MASK_REG_FW1_AON_APCPU_C7_DSLP_ENA_RD_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_C7_CORE_INT_DISABLE_RD_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_C2_CORE_INT_DISABLE_RD_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_C1_SIMD_RET_MODE_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_C0_SIMD_RET_MODE_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_TOP_RMA_CTRL_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_FIREWALL_WAKEUP_PUB_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_GIC_CFG_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_APCPU_C7_CFG_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_APCPU_DSLP_ENA_SRST_MASK_CFG_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_C2_CFG_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_C1_CFG_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_C0_CFG_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_APCPU_TOP_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE1_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE0_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG3_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_APCPU_C7_CFG_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_SEL_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_ANALOG_PHY_PD_CFG_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_GIC_RST_EN_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_APCPU_C2_DSLP_ENA_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_C1_DSLP_ENA_RD_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_C0_DSLP_ENA_RD_SEC 0x400
+#define MASK_REG_FW1_AON_PWR_DGB_PARAMETER_RD_SEC 0x200
+#define MASK_REG_FW1_AON_CGM_PMU_SEL_RD_SEC 0x100
+#define MASK_REG_FW1_AON_PMU_CLK_DIV_CFG_RD_SEC 0x80
+#define MASK_REG_FW1_AON_DDR_SLP_WAIT_CNT_RD_SEC 0x40
+#define MASK_REG_FW1_AON_PWR_DOMAIN_INT_CLR_RD_SEC 0x20
+#define MASK_REG_FW1_AON_AON_MEM_CTRL_RD_SEC 0x10
+#define MASK_REG_FW1_AON_BISR_FORCE_SEL_RD_SEC 0x8
+#define MASK_REG_FW1_AON_DCXO_LP_DEEP_SLEEP_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_PAD_OUT_DCDC_ARM1_EN_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_PAD_OUT_DCDC_ARM0_EN_CFG_RD_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_SOFT_INT_GEN_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_PCHANNEL_STATE1_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_PCHANNEL_STATE0_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CORINTH_SCU_CLK_GATE_CFG_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCPU_SOFT_RST_TYPE_CFG_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_FRC_ON_CFG_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_ANANKELITE_MEM_POWER_CFG_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_DEBUG_STATE_MARK_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG3_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG2_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG1_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_DEBUG_RECOV_TYPE_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_WTLCP_HU3GE_NEST_DOMAIN_CTRL_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_DUAL_RAIL_MEM_POWER_CTRL_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PLL_RST_CTRL_STATE1_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PLL_RST_CTRL_STATE0_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_ISPPLL_RST_CTRL_CFG_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_RPLL_RST_CTRL_CFG_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_GPLL_RST_CTRL_CFG_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_LTEPLL_RST_CTRL_CFG_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_TWPLL_RST_CTRL_CFG_RD_SEC 0x800
+#define MASK_REG_FW1_AON_DPLL1_RST_CTRL_CFG_RD_SEC 0x400
+#define MASK_REG_FW1_AON_DPLL0_RST_CTRL_CFG_RD_SEC 0x200
+#define MASK_REG_FW1_AON_MPLL2_RST_CTRL_CFG_RD_SEC 0x100
+#define MASK_REG_FW1_AON_MPLL1_RST_CTRL_CFG_RD_SEC 0x80
+#define MASK_REG_FW1_AON_MPLL0_RST_CTRL_CFG_RD_SEC 0x40
+#define MASK_REG_FW1_AON_MPLL_WAIT_CLK_DIV_CFG_RD_SEC 0x20
+#define MASK_REG_FW1_AON_PD_GPU_TOP_CFG1_RD_SEC 0x10
+#define MASK_REG_FW1_AON_APCU_MODE_STATE1_RD_SEC 0x8
+#define MASK_REG_FW1_AON_APCU_MODE_STATE0_RD_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_CORE_FORCE_STOP_RD_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_C2_SIMD_RET_MODE_RD_SEC 0x1
+#define MASK_REG_FW1_AON_ANANKE_LITE_DUAL_RAIL_RAM_FORCE_ON_CFG_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_OFF_EMU_CLR_IN_DISABLE_CFG_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_DVFS_BLOCK_SHUTDOWN_CFG_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CSYSPWRUP_WAKEUP_EN_CFG_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CLUSTER_INF_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE7_INF_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE2_INF_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE1_INF_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE0_INF_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_RECORD_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_INT_REQ_APCPU_MODE_ST_CLR_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_INT_REQ_APCPU_MODE_ST_ENABLE_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_APCPU_DENY_TIME_THRESHOLD_CFG_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CGM_EN_CFG_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_ANALOG_PHY_PWRON_CFG_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_GPIO_FORCE_GATING_PLL_CFG_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_WTLCP_DPFEC_NEST_DOMAIN_CTRL_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_CLUSTER_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_CORE7_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_APCPU_CORE2_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_CORE1_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_CORE0_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x400
+#define MASK_REG_FW1_AON_SOFTWARE_APCPU_PCHANNEL_HANDSHAKE_ENABLE_RD_SEC 0x200
+#define MASK_REG_FW1_AON_SOFTWARE_APCPU_PACTIVE_ENABLE_RD_SEC 0x100
+#define MASK_REG_FW1_AON_APCPU_CLUSTER_SW_PACTIVE_RD_SEC 0x80
+#define MASK_REG_FW1_AON_APCPU_CORE7_SW_PACTIVE_RD_SEC 0x40
+#define MASK_REG_FW1_AON_APCPU_CORE2_SW_PACTIVE_RD_SEC 0x20
+#define MASK_REG_FW1_AON_APCPU_CORE1_SW_PACTIVE_RD_SEC 0x10
+#define MASK_REG_FW1_AON_APCPU_CORE0_SW_PACTIVE_RD_SEC 0x8
+#define MASK_REG_FW1_AON_PUB_DFS_FRQ_SEL_RD_SEC 0x4
+#define MASK_REG_FW1_AON_DUAL_RAIL_RAM_FORCE_SLP_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_DUAL_RAIL_RAM_FORCE_PD_CFG_RD_SEC 0x1
+#define MASK_REG_FW1_AON_PD_AUDCP_AUDDSP_SHUTDOWN_MARK_STATUS_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_PD_PUB_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_PD_AUDCP_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_PD_WTLCP_TD_PROC_SHUTDOWN_MARK_STATUS_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_PROC_SHUTDOWN_MARK_STATUS_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_PD_AP_VSP_SHUTDOWN_MARK_STATUS_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_DPFEC_SHUTDOWN_MARK_STATUS_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_CE_SHUTDOWN_MARK_STATUS_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_MM_TOP_SHUTDOWN_MARK_STATUS_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_GPU_TOP_SHUTDOWN_MARK_STATUS_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_PD_AP_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_PD_APCPU_C2_SHUTDOWN_MARK_STATUS_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_APCPU_C1_SHUTDOWN_MARK_STATUS_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_APCPU_C0_SHUTDOWN_MARK_STATUS_RD_SEC 0x800
+#define MASK_REG_FW1_AON_CDMA_PROC1_PWR_CFG_RD_SEC 0x400
+#define MASK_REG_FW1_AON_CDMA_WAKEUP_CFG_RD_SEC 0x200
+#define MASK_REG_FW1_AON_CDMA_DEEP_SLEEP_CFG_RD_SEC 0x100
+#define MASK_REG_FW1_AON_CDMA_DEEP_SLEEP_CNT_RD_SEC 0x80
+#define MASK_REG_FW1_AON_PD_CDMA_SYS_SHUTDOWN_MARK_STATUS_RD_SEC 0x40
+#define MASK_REG_FW1_AON_WDG_TRIG_DBG_RECOV_CFG_RD_SEC 0x20
+#define MASK_REG_FW1_AON_SRAM_DLY_CTRL_CFG_RD_SEC 0x10
+#define MASK_REG_FW1_AON_DPLL1_CNT_DONE_BYP_RD_SEC 0x8
+#define MASK_REG_FW1_AON_SP_CLK_GATE_BYP_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_ALL_PLL_PD_RCO_BYP_RD_SEC 0x2
+#define MASK_REG_FW1_AON_OFF_EMU_TO_OFF_CFG_RD_SEC 0x1
+#define MASK_REG_FW1_AON_PUBCP_DOZE_SLEEP_CNT_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_WTLCP_DOZE_SLEEP_CNT_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_AP_DOZE_SLEEP_CNT_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_TOP_LIGHT_SLEEP_CNT_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCPU_TOP_DEEP_SLEEP_CNT_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_PD_APCPU_C7_SHUTDOWN_MARK_STATUS_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_DDR_SLP_CTRL_STATE_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_EIC_SYS_SEL_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_PD_AP_SYS_DBG_SHUTDOWN_EN_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_CSI_DSI_PWR_CNT_DONE_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_REG_SYS_DDR_PWR_HS_ACK_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_SOFT_RST_SEL_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_REG_SYS_SRST_FRC_LP_ACK_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_SYS_SOFT_RST_BUSY_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_AON_SYS_LIGHT_SLEEP_CNT_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_AUDCP_SYS_LIGHT_SLEEP_CNT_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_PUBCP_LIGHT_SLEEP_CNT_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_WTLCP_LIGHT_SLEEP_CNT_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_AP_LIGHT_SLEEP_CNT_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_CNT_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_AUDCP_SYS_DEEP_SLEEP_CNT_RD_SEC 0x800
+#define MASK_REG_FW1_AON_PUBCP_DEEP_SLEEP_CNT_RD_SEC 0x400
+#define MASK_REG_FW1_AON_WTLCP_DEEP_SLEEP_CNT_RD_SEC 0x200
+#define MASK_REG_FW1_AON_SP_SYS_DEEP_SLEEP_CNT_RD_SEC 0x100
+#define MASK_REG_FW1_AON_AP_DEEP_SLEEP_CNT_RD_SEC 0x80
+#define MASK_REG_FW1_AON_PUB_SYS_LIGHT_SLEEP_CNT_RD_SEC 0x40
+#define MASK_REG_FW1_AON_AUDCP_SYS_SLEEP_CNT_RD_SEC 0x20
+#define MASK_REG_FW1_AON_PUBCP_SYS_SLEEP_CNT_RD_SEC 0x10
+#define MASK_REG_FW1_AON_WTLCP_SYS_SLEEP_CNT_RD_SEC 0x8
+#define MASK_REG_FW1_AON_AP_SYS_SLEEP_CNT_RD_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_TOP_SLEEP_CNT_RD_SEC 0x2
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_SHUTDOWN_MARK_STATUS_RD_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_CORE6_SW_PACTIVE_RD_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_CORE5_SW_PACTIVE_RD_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_CORE4_SW_PACTIVE_RD_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CORE3_SW_PACTIVE_RD_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCU_MODE_STATE_FIG_RD_SEC 0x8000000
+#define MASK_REG_FW1_AON_APCPU_C5_SIMD_RET_MODE_RD_SEC 0x4000000
+#define MASK_REG_FW1_AON_APCPU_C4_SIMD_RET_MODE_RD_SEC 0x2000000
+#define MASK_REG_FW1_AON_APCPU_C3_SIMD_RET_MODE_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_C6_CFG_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_C5_CFG_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_C4_CFG_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_APCPU_C3_CFG_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE_FIG_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_APCPU_CPU1_CFG2_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_APCPU_CPU1_CFG1_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_APCPU_C6_CFG_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_APCPU_C5_DSLP_ENA_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_C4_DSLP_ENA_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_C3_DSLP_ENA_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_AP_VDSP_DSLP_ENA_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_C6_DSLP_ENA_RD_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_WFI_MARK_RD_SEC 0x400
+#define MASK_REG_FW1_AON_AP_VDSP_CORE_INT_DISABLE_RD_SEC 0x200
+#define MASK_REG_FW1_AON_APCPU_C6_CORE_INT_DISABLE_RD_SEC 0x100
+#define MASK_REG_FW1_AON_APCPU_C5_CORE_INT_DISABLE_RD_SEC 0x80
+#define MASK_REG_FW1_AON_APCPU_C4_CORE_INT_DISABLE_RD_SEC 0x40
+#define MASK_REG_FW1_AON_APCPU_C3_CORE_INT_DISABLE_RD_SEC 0x20
+#define MASK_REG_FW1_AON_PD_AP_VDSP_CFG_RD_SEC 0x10
+#define MASK_REG_FW1_AON_PD_APCPU_C5_CFG_RD_SEC 0x8
+#define MASK_REG_FW1_AON_PD_APCPU_C4_CFG_RD_SEC 0x4
+#define MASK_REG_FW1_AON_PD_APCPU_C3_CFG_RD_SEC 0x2
+#define MASK_REG_FW1_AON_AUDCP_DOZE_SLEEP_CNT_RD_SEC 0x1
+#define MASK_REG_FW1_AON_EPPLL_PLL_SEL_CFG_RD_SEC 0x1000000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG3_RD_SEC 0x800000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG2_RD_SEC 0x400000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG1_RD_SEC 0x200000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG0_RD_SEC 0x100000
+#define MASK_REG_FW1_AON_EPPLL_RST_CTRL_CFG_RD_SEC 0x80000
+#define MASK_REG_FW1_AON_EPPLL_REL_CFG_RD_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_GPU_CORE_CFG0_RD_SEC 0x20000
+#define MASK_REG_FW1_AON_MEM_SD_CFG_FIG_RD_SEC 0x10000
+#define MASK_REG_FW1_AON_MEM_SLP_CFG_FIG_RD_SEC 0x8000
+#define MASK_REG_FW1_AON_MEM_AUTO_SD_CFG_FIG_RD_SEC 0x4000
+#define MASK_REG_FW1_AON_MEM_AUTO_SLP_CFG_FIG_RD_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_APCPU_C6_SHUTDOWN_MARK_STATUS_RD_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_AP_VDSP_SHUTDOWN_MARK_STATUS_RD_SEC 0x800
+#define MASK_REG_FW1_AON_PD_APCPU_C5_SHUTDOWN_MARK_STATUS_RD_SEC 0x400
+#define MASK_REG_FW1_AON_PD_APCPU_C4_SHUTDOWN_MARK_STATUS_RD_SEC 0x200
+#define MASK_REG_FW1_AON_PD_APCPU_C3_SHUTDOWN_MARK_STATUS_RD_SEC 0x100
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE6_INF_RD_SEC 0x80
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE5_INF_RD_SEC 0x40
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE4_INF_RD_SEC 0x20
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE3_INF_RD_SEC 0x10
+#define MASK_REG_FW1_AON_APCPU_CORE6_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x8
+#define MASK_REG_FW1_AON_APCPU_CORE5_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_CORE4_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_CORE3_SW_PCHANNEL_HANDSHAKE_RD_SEC 0x1
+#define MASK_REG_FW1_AON_XTL0_REL_CFG_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT2_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT1_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_PLL_WAIT_CNT0_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_XTL_WAIT_CNT_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_AP_WAKEUP_POR_CFG_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_PD_PUB_SYS_CFG_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_PD_CDMA_SYS_CFG_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_PUBCP_FRC_STOP_REQ_FOR_WTL_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_PD_AUDCP_SYS_CFG_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_PD_AUDCP_AUDDSP_CFG_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_PD_PUBCP_SYS_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_PD_WTLCP_SYS_CFG_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_WTLCP_TD_PROC_CFG_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_PROC_CFG_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_B_CFG_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_A_CFG_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_PD_WTLCP_TGDSP_CFG_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_PD_WTLCP_LDSP_CFG_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_DPFEC_CFG_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_CE_CFG_WR_SEC 0x800
+#define MASK_REG_FW1_AON_PD_GPU_TOP_CFG0_WR_SEC 0x400
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_CFG1_WR_SEC 0x200
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_CFG0_WR_SEC 0x100
+#define MASK_REG_FW1_AON_PD_MM_TOP_CFG_WR_SEC 0x80
+#define MASK_REG_FW1_AON_PD_AP_SYS_CFG_WR_SEC 0x40
+#define MASK_REG_FW1_AON_PD_AP_VSP_CFG_WR_SEC 0x20
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG2_WR_SEC 0x10
+#define MASK_REG_FW1_AON_PD_APCPU_C2_CFG_WR_SEC 0x8
+#define MASK_REG_FW1_AON_PD_APCPU_C1_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_PD_APCPU_C0_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG_WR_SEC 0x1
+#define MASK_REG_FW1_AON_BISR_DONE_STATUS_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_CLK26M_SEL_CFG_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_DDR_PHY_RET_CFG_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_DDR_OP_MODE_CFG_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_PWR_STATUS3_DBG_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_DDR_CHN_SLEEP_CTRL1_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_DDR_CHN_SLEEP_CTRL0_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_CPPLL_RST_CTRL_CFG_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_CPPLL_REL_CFG_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_POLL1_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_POLL0_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_PUB_SYS_SLEEP_BYPASS_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_SLEEP_STATUS_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_DDR_SLEEP_CTRL_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_SLEEP_CTRL_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PUB_SYS_AUTO_LIGHT_SLEEP_ENABLE_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_PWR_STATUS2_DBG_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_PWR_STATUS1_DBG_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_PWR_STATUS0_DBG_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PWR_STATUS4_DBG_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_CP_SLP_STATUS_DBG0_WR_SEC 0x800
+#define MASK_REG_FW1_AON_CP_SOFT_RST_WR_SEC 0x400
+#define MASK_REG_FW1_AON_RPLL_REL_CFG_WR_SEC 0x200
+#define MASK_REG_FW1_AON_GPLL_REL_CFG_WR_SEC 0x100
+#define MASK_REG_FW1_AON_TWPLL_REL_CFG_WR_SEC 0x80
+#define MASK_REG_FW1_AON_LTEPLL_REL_CFG_WR_SEC 0x40
+#define MASK_REG_FW1_AON_DPLL1_REL_CFG_WR_SEC 0x20
+#define MASK_REG_FW1_AON_DPLL0_REL_CFG_WR_SEC 0x10
+#define MASK_REG_FW1_AON_XTLBUF1_REL_CFG_WR_SEC 0x8
+#define MASK_REG_FW1_AON_XTLBUF0_REL_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_ISPPLL_REL_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_XTL1_REL_CFG_WR_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_C1_CORE_INT_DISABLE_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_C0_CORE_INT_DISABLE_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_PUBCP_CORE_INT_DISABLE_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_WTLCP_LDSP_CORE_INT_DISABLE_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_WTLCP_TGDSP_CORE_INT_DISABLE_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_AUDCP_SYS_CORE_INT_DISABLE_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_WAKEUP_LOCK_EN_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_MEM_AUTO_SD_CFG_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_MEM_AUTO_SLP_CFG_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_MPLL2_REL_CFG_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_MPLL1_REL_CFG_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_MPLL0_REL_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_RCO_CNT_WAIT_CFG_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_RCO_REL_CFG_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PWR_CNT_WAIT_CFG1_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PWR_CNT_WAIT_CFG0_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_SP_SYS_HOLD_CGM_EN_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_CORE_WAKEUP_EN_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_MEM_SD_CFG_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_MEM_SLP_CFG_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_SLEEP_XTLON_CTRL_WR_SEC 0x800
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG3_WR_SEC 0x400
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG2_WR_SEC 0x200
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG1_WR_SEC 0x100
+#define MASK_REG_FW1_AON_CGM_FORCE_EN_CFG0_WR_SEC 0x80
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG3_WR_SEC 0x40
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG2_WR_SEC 0x20
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG1_WR_SEC 0x10
+#define MASK_REG_FW1_AON_CGM_AUTO_GATE_SEL_CFG0_WR_SEC 0x8
+#define MASK_REG_FW1_AON_BISR_EN_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_BISR_BYP_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_BISR_BUSY_STATUS_WR_SEC 0x1
+#define MASK_REG_FW1_AON_PAD_OUT_XTL_EN1_CFG_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_PAD_OUT_XTL_EN0_CFG_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_PAD_OUT_CHIP_SLEEP_CFG_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_EXT_XTL_EN_CTRL_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_LVDSRFPLL_REL_CFG_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_SLEEP_CNT_CLR_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_PMU_DEBUG_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_AXI_LP_CTRL_DISABLE_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_EIC_SEL_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_PUB_CLK_RDY_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_PUB_ACC_RDY_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_AUDCP_AUDDSP_DSLP_ENA_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_AUDCP_SYS_DSLP_ENA_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_DOZE_FORCE_SLEEP_CTRL_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_DOZE_SLEEP_MON_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_DOZE_SLEEP_ENABLE_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_MON_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_ENABLE_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_LIGHT_SLEEP_WAKEUP_EN_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PUB_DEEP_SLEEP_WAKEUP_EN_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_PUB_DEEP_SLEEP_ENA_WR_SEC 0x800
+#define MASK_REG_FW1_AON_SP_SYS_DSLP_ENA_WR_SEC 0x400
+#define MASK_REG_FW1_AON_APCPU_TOP_DSLP_ENA_WR_SEC 0x200
+#define MASK_REG_FW1_AON_WTLCP_DSLP_ENA_WR_SEC 0x100
+#define MASK_REG_FW1_AON_PUBCP_DSLP_ENA_WR_SEC 0x80
+#define MASK_REG_FW1_AON_AP_DSLP_ENA_WR_SEC 0x40
+#define MASK_REG_FW1_AON_WTLCP_LDSP_DSLP_ENA_WR_SEC 0x20
+#define MASK_REG_FW1_AON_WTLCP_TGDSP_DSLP_ENA_WR_SEC 0x10
+#define MASK_REG_FW1_AON_CDMA_DSLP_ENA_WR_SEC 0x8
+#define MASK_REG_FW1_AON_APCPU_C7_DSLP_ENA_WR_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_C7_CORE_INT_DISABLE_WR_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_C2_CORE_INT_DISABLE_WR_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_C1_SIMD_RET_MODE_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_C0_SIMD_RET_MODE_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_TOP_RMA_CTRL_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_FIREWALL_WAKEUP_PUB_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_GIC_CFG_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_APCPU_C7_CFG_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_APCPU_DSLP_ENA_SRST_MASK_CFG_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_C2_CFG_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_C1_CFG_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_C0_CFG_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_APCPU_TOP_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE1_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE0_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_CFG3_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_APCPU_C7_CFG_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_SEL_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_ANALOG_PHY_PD_CFG_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_GIC_RST_EN_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_APCPU_C2_DSLP_ENA_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_C1_DSLP_ENA_WR_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_C0_DSLP_ENA_WR_SEC 0x400
+#define MASK_REG_FW1_AON_PWR_DGB_PARAMETER_WR_SEC 0x200
+#define MASK_REG_FW1_AON_CGM_PMU_SEL_WR_SEC 0x100
+#define MASK_REG_FW1_AON_PMU_CLK_DIV_CFG_WR_SEC 0x80
+#define MASK_REG_FW1_AON_DDR_SLP_WAIT_CNT_WR_SEC 0x40
+#define MASK_REG_FW1_AON_PWR_DOMAIN_INT_CLR_WR_SEC 0x20
+#define MASK_REG_FW1_AON_AON_MEM_CTRL_WR_SEC 0x10
+#define MASK_REG_FW1_AON_BISR_FORCE_SEL_WR_SEC 0x8
+#define MASK_REG_FW1_AON_DCXO_LP_DEEP_SLEEP_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_PAD_OUT_DCDC_ARM1_EN_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_PAD_OUT_DCDC_ARM0_EN_CFG_WR_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_SOFT_INT_GEN_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_PCHANNEL_STATE1_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_PCHANNEL_STATE0_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CORINTH_SCU_CLK_GATE_CFG_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCPU_SOFT_RST_TYPE_CFG_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_FRC_ON_CFG_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_ANANKELITE_MEM_POWER_CFG_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_DEBUG_STATE_MARK_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG3_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG2_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CFG1_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_DEBUG_RECOV_TYPE_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_WTLCP_HU3GE_NEST_DOMAIN_CTRL_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_DUAL_RAIL_MEM_POWER_CTRL_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PLL_RST_CTRL_STATE1_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PLL_RST_CTRL_STATE0_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_ISPPLL_RST_CTRL_CFG_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_RPLL_RST_CTRL_CFG_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_GPLL_RST_CTRL_CFG_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_LTEPLL_RST_CTRL_CFG_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_TWPLL_RST_CTRL_CFG_WR_SEC 0x800
+#define MASK_REG_FW1_AON_DPLL1_RST_CTRL_CFG_WR_SEC 0x400
+#define MASK_REG_FW1_AON_DPLL0_RST_CTRL_CFG_WR_SEC 0x200
+#define MASK_REG_FW1_AON_MPLL2_RST_CTRL_CFG_WR_SEC 0x100
+#define MASK_REG_FW1_AON_MPLL1_RST_CTRL_CFG_WR_SEC 0x80
+#define MASK_REG_FW1_AON_MPLL0_RST_CTRL_CFG_WR_SEC 0x40
+#define MASK_REG_FW1_AON_MPLL_WAIT_CLK_DIV_CFG_WR_SEC 0x20
+#define MASK_REG_FW1_AON_PD_GPU_TOP_CFG1_WR_SEC 0x10
+#define MASK_REG_FW1_AON_APCU_MODE_STATE1_WR_SEC 0x8
+#define MASK_REG_FW1_AON_APCU_MODE_STATE0_WR_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_CORE_FORCE_STOP_WR_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_C2_SIMD_RET_MODE_WR_SEC 0x1
+#define MASK_REG_FW1_AON_ANANKE_LITE_DUAL_RAIL_RAM_FORCE_ON_CFG_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_OFF_EMU_CLR_IN_DISABLE_CFG_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_DVFS_BLOCK_SHUTDOWN_CFG_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CSYSPWRUP_WAKEUP_EN_CFG_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CLUSTER_INF_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE7_INF_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE2_INF_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE1_INF_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE0_INF_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_RECORD_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_INT_REQ_APCPU_MODE_ST_CLR_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_INT_REQ_APCPU_MODE_ST_ENABLE_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_APCPU_DENY_TIME_THRESHOLD_CFG_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_APCPU_MODE_ST_CGM_EN_CFG_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_ANALOG_PHY_PWRON_CFG_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_GPIO_FORCE_GATING_PLL_CFG_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_WTLCP_DPFEC_NEST_DOMAIN_CTRL_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_CLUSTER_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_CORE7_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_APCPU_CORE2_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_CORE1_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_CORE0_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x400
+#define MASK_REG_FW1_AON_SOFTWARE_APCPU_PCHANNEL_HANDSHAKE_ENABLE_WR_SEC 0x200
+#define MASK_REG_FW1_AON_SOFTWARE_APCPU_PACTIVE_ENABLE_WR_SEC 0x100
+#define MASK_REG_FW1_AON_APCPU_CLUSTER_SW_PACTIVE_WR_SEC 0x80
+#define MASK_REG_FW1_AON_APCPU_CORE7_SW_PACTIVE_WR_SEC 0x40
+#define MASK_REG_FW1_AON_APCPU_CORE2_SW_PACTIVE_WR_SEC 0x20
+#define MASK_REG_FW1_AON_APCPU_CORE1_SW_PACTIVE_WR_SEC 0x10
+#define MASK_REG_FW1_AON_APCPU_CORE0_SW_PACTIVE_WR_SEC 0x8
+#define MASK_REG_FW1_AON_PUB_DFS_FRQ_SEL_WR_SEC 0x4
+#define MASK_REG_FW1_AON_DUAL_RAIL_RAM_FORCE_SLP_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_DUAL_RAIL_RAM_FORCE_PD_CFG_WR_SEC 0x1
+#define MASK_REG_FW1_AON_PD_AUDCP_AUDDSP_SHUTDOWN_MARK_STATUS_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_PD_PUB_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_PD_AUDCP_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_PD_WTLCP_TD_PROC_SHUTDOWN_MARK_STATUS_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_PROC_SHUTDOWN_MARK_STATUS_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_PD_AP_VSP_SHUTDOWN_MARK_STATUS_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_DPFEC_SHUTDOWN_MARK_STATUS_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_WTLCP_LTE_CE_SHUTDOWN_MARK_STATUS_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_MM_TOP_SHUTDOWN_MARK_STATUS_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_GPU_TOP_SHUTDOWN_MARK_STATUS_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_PD_AP_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_PD_APCPU_C2_SHUTDOWN_MARK_STATUS_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_APCPU_C1_SHUTDOWN_MARK_STATUS_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_APCPU_C0_SHUTDOWN_MARK_STATUS_WR_SEC 0x800
+#define MASK_REG_FW1_AON_CDMA_PROC1_PWR_CFG_WR_SEC 0x400
+#define MASK_REG_FW1_AON_CDMA_WAKEUP_CFG_WR_SEC 0x200
+#define MASK_REG_FW1_AON_CDMA_DEEP_SLEEP_CFG_WR_SEC 0x100
+#define MASK_REG_FW1_AON_CDMA_DEEP_SLEEP_CNT_WR_SEC 0x80
+#define MASK_REG_FW1_AON_PD_CDMA_SYS_SHUTDOWN_MARK_STATUS_WR_SEC 0x40
+#define MASK_REG_FW1_AON_WDG_TRIG_DBG_RECOV_CFG_WR_SEC 0x20
+#define MASK_REG_FW1_AON_SRAM_DLY_CTRL_CFG_WR_SEC 0x10
+#define MASK_REG_FW1_AON_DPLL1_CNT_DONE_BYP_WR_SEC 0x8
+#define MASK_REG_FW1_AON_SP_CLK_GATE_BYP_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_ALL_PLL_PD_RCO_BYP_WR_SEC 0x2
+#define MASK_REG_FW1_AON_OFF_EMU_TO_OFF_CFG_WR_SEC 0x1
+#define MASK_REG_FW1_AON_PUBCP_DOZE_SLEEP_CNT_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_WTLCP_DOZE_SLEEP_CNT_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_AP_DOZE_SLEEP_CNT_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_TOP_LIGHT_SLEEP_CNT_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCPU_TOP_DEEP_SLEEP_CNT_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_PD_APCPU_C7_SHUTDOWN_MARK_STATUS_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_DDR_SLP_CTRL_STATE_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_EIC_SYS_SEL_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_PD_AP_SYS_DBG_SHUTDOWN_EN_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_CSI_DSI_PWR_CNT_DONE_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_REG_SYS_DDR_PWR_HS_ACK_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_SOFT_RST_SEL_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_REG_SYS_SRST_FRC_LP_ACK_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_SYS_SOFT_RST_BUSY_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_AON_SYS_LIGHT_SLEEP_CNT_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_AUDCP_SYS_LIGHT_SLEEP_CNT_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_PUBCP_LIGHT_SLEEP_CNT_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_WTLCP_LIGHT_SLEEP_CNT_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_AP_LIGHT_SLEEP_CNT_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PUB_SYS_DEEP_SLEEP_CNT_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_AUDCP_SYS_DEEP_SLEEP_CNT_WR_SEC 0x800
+#define MASK_REG_FW1_AON_PUBCP_DEEP_SLEEP_CNT_WR_SEC 0x400
+#define MASK_REG_FW1_AON_WTLCP_DEEP_SLEEP_CNT_WR_SEC 0x200
+#define MASK_REG_FW1_AON_SP_SYS_DEEP_SLEEP_CNT_WR_SEC 0x100
+#define MASK_REG_FW1_AON_AP_DEEP_SLEEP_CNT_WR_SEC 0x80
+#define MASK_REG_FW1_AON_PUB_SYS_LIGHT_SLEEP_CNT_WR_SEC 0x40
+#define MASK_REG_FW1_AON_AUDCP_SYS_SLEEP_CNT_WR_SEC 0x20
+#define MASK_REG_FW1_AON_PUBCP_SYS_SLEEP_CNT_WR_SEC 0x10
+#define MASK_REG_FW1_AON_WTLCP_SYS_SLEEP_CNT_WR_SEC 0x8
+#define MASK_REG_FW1_AON_AP_SYS_SLEEP_CNT_WR_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_TOP_SLEEP_CNT_WR_SEC 0x2
+#define MASK_REG_FW1_AON_PD_GPU_RGX_DUST_SHUTDOWN_MARK_STATUS_WR_SEC 0x1
+#define MASK_REG_FW1_AON_APCPU_CORE6_SW_PACTIVE_WR_SEC 0x80000000
+#define MASK_REG_FW1_AON_APCPU_CORE5_SW_PACTIVE_WR_SEC 0x40000000
+#define MASK_REG_FW1_AON_APCPU_CORE4_SW_PACTIVE_WR_SEC 0x20000000
+#define MASK_REG_FW1_AON_APCPU_CORE3_SW_PACTIVE_WR_SEC 0x10000000
+#define MASK_REG_FW1_AON_APCU_MODE_STATE_FIG_WR_SEC 0x8000000
+#define MASK_REG_FW1_AON_APCPU_C5_SIMD_RET_MODE_WR_SEC 0x4000000
+#define MASK_REG_FW1_AON_APCPU_C4_SIMD_RET_MODE_WR_SEC 0x2000000
+#define MASK_REG_FW1_AON_APCPU_C3_SIMD_RET_MODE_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_APCPU_C6_CFG_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_APCPU_C5_CFG_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_APCPU_C4_CFG_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_APCPU_C3_CFG_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_APCU_PWR_STATE_FIG_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_PD_APCPU_CPU1_CFG2_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_APCPU_CPU1_CFG1_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_PD_APCPU_C6_CFG_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_APCPU_C5_DSLP_ENA_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_APCPU_C4_DSLP_ENA_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_APCPU_C3_DSLP_ENA_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_AP_VDSP_DSLP_ENA_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_APCPU_C6_DSLP_ENA_WR_SEC 0x800
+#define MASK_REG_FW1_AON_APCPU_WFI_MARK_WR_SEC 0x400
+#define MASK_REG_FW1_AON_AP_VDSP_CORE_INT_DISABLE_WR_SEC 0x200
+#define MASK_REG_FW1_AON_APCPU_C6_CORE_INT_DISABLE_WR_SEC 0x100
+#define MASK_REG_FW1_AON_APCPU_C5_CORE_INT_DISABLE_WR_SEC 0x80
+#define MASK_REG_FW1_AON_APCPU_C4_CORE_INT_DISABLE_WR_SEC 0x40
+#define MASK_REG_FW1_AON_APCPU_C3_CORE_INT_DISABLE_WR_SEC 0x20
+#define MASK_REG_FW1_AON_PD_AP_VDSP_CFG_WR_SEC 0x10
+#define MASK_REG_FW1_AON_PD_APCPU_C5_CFG_WR_SEC 0x8
+#define MASK_REG_FW1_AON_PD_APCPU_C4_CFG_WR_SEC 0x4
+#define MASK_REG_FW1_AON_PD_APCPU_C3_CFG_WR_SEC 0x2
+#define MASK_REG_FW1_AON_AUDCP_DOZE_SLEEP_CNT_WR_SEC 0x1
+#define MASK_REG_FW1_AON_EPPLL_PLL_SEL_CFG_WR_SEC 0x1000000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG3_WR_SEC 0x800000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG2_WR_SEC 0x400000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG1_WR_SEC 0x200000
+#define MASK_REG_FW1_AON_EPPLL_DELAY_CTRL_CFG0_WR_SEC 0x100000
+#define MASK_REG_FW1_AON_EPPLL_RST_CTRL_CFG_WR_SEC 0x80000
+#define MASK_REG_FW1_AON_EPPLL_REL_CFG_WR_SEC 0x40000
+#define MASK_REG_FW1_AON_PD_GPU_CORE_CFG0_WR_SEC 0x20000
+#define MASK_REG_FW1_AON_MEM_SD_CFG_FIG_WR_SEC 0x10000
+#define MASK_REG_FW1_AON_MEM_SLP_CFG_FIG_WR_SEC 0x8000
+#define MASK_REG_FW1_AON_MEM_AUTO_SD_CFG_FIG_WR_SEC 0x4000
+#define MASK_REG_FW1_AON_MEM_AUTO_SLP_CFG_FIG_WR_SEC 0x2000
+#define MASK_REG_FW1_AON_PD_APCPU_C6_SHUTDOWN_MARK_STATUS_WR_SEC 0x1000
+#define MASK_REG_FW1_AON_PD_AP_VDSP_SHUTDOWN_MARK_STATUS_WR_SEC 0x800
+#define MASK_REG_FW1_AON_PD_APCPU_C5_SHUTDOWN_MARK_STATUS_WR_SEC 0x400
+#define MASK_REG_FW1_AON_PD_APCPU_C4_SHUTDOWN_MARK_STATUS_WR_SEC 0x200
+#define MASK_REG_FW1_AON_PD_APCPU_C3_SHUTDOWN_MARK_STATUS_WR_SEC 0x100
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE6_INF_WR_SEC 0x80
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE5_INF_WR_SEC 0x40
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE4_INF_WR_SEC 0x20
+#define MASK_REG_FW1_AON_INT_REQ_MODE_ST_APCPU_CORE3_INF_WR_SEC 0x10
+#define MASK_REG_FW1_AON_APCPU_CORE6_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x8
+#define MASK_REG_FW1_AON_APCPU_CORE5_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x4
+#define MASK_REG_FW1_AON_APCPU_CORE4_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x2
+#define MASK_REG_FW1_AON_APCPU_CORE3_SW_PCHANNEL_HANDSHAKE_WR_SEC 0x1
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY0 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY1 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY2 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY3 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY4 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY5 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY6 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY7 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY8 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY9 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY10 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY11 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY12 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY13 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY14 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY15 0xffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY0 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY1 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY2 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY3 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY4 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY5 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY6 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY7 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY8 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY9 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY10 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY11 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY12 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY13 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY14 0xffffffff
+#define MASK_REG_FW1_AON_BIT_CTRL_ARRAY15 0xffffffff
+#define MASK_MM_CLK_CORE_CGM_MM_AHB_CFG_CGM_MM_AHB_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_MM_MTX_CFG_CGM_MM_MTX_SEL 0x7
+#define MASK_MM_CLK_CORE_CGM_SENSOR0_CFG_CGM_SENSOR0_DIV 0x700
+#define MASK_MM_CLK_CORE_CGM_SENSOR0_CFG_CGM_SENSOR0_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_SENSOR1_CFG_CGM_SENSOR1_DIV 0x700
+#define MASK_MM_CLK_CORE_CGM_SENSOR1_CFG_CGM_SENSOR1_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_SENSOR2_CFG_CGM_SENSOR2_DIV 0x700
+#define MASK_MM_CLK_CORE_CGM_SENSOR2_CFG_CGM_SENSOR2_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_CPP_CFG_CGM_CPP_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_JPG_CFG_CGM_JPG_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_FD_CFG_CGM_FD_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_DCAM_IF_CFG_CGM_DCAM_IF_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_DCAM_AXI_CFG_CGM_DCAM_AXI_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_ISP_CFG_CGM_ISP_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI0_CFG_CGM_MIPI_CSI0_PAD_SEL 0x10000
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI0_CFG_CGM_MIPI_CSI0_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI1_CFG_CGM_MIPI_CSI1_PAD_SEL 0x10000
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI1_CFG_CGM_MIPI_CSI1_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI2_CFG_CGM_MIPI_CSI2_PAD_SEL 0x10000
+#define MASK_MM_CLK_CORE_CGM_MIPI_CSI2_CFG_CGM_MIPI_CSI2_SEL 0x3
+#define MASK_MM_CLK_CORE_CGM_CPHY_CFG_CFG_CGM_CPHY_CFG_SEL 0x1
+#define MASK_MM_CLK_CORE_CGM_CSI_PHY_SCAN_ONLY_CFG_CGM_CSI_PHY_SCAN_ONLY_SEL 0x1
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_ANALOG_DPLL_DUMY_IN 0xffff0000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_ANALOG_DPLL_DUMY_OUT 0xffff
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_LOCK_DONE 0x40000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_N 0x3ff80
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_ICP 0x70
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_ICP_FS 0xc
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_SDM_EN 0x2
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_DIV_S 0x1
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_NINT 0x3f800000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_KINT 0x7fffff
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_DIV_SEL 0x3c000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_CLKDIV_EN 0x2000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_IL_DIV 0x1000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_CCS_CTRL 0xff0
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_MOD_EN 0x8
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_RST 0x2
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_PD 0x1
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_CP_OFFSET 0x60
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_CP_EN 0x10
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_R3_SEL 0xc
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_R2_SEL 0x3
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_RESERVED 0xff
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_BIST_EN 0x10000
+#define MASK_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL0_BIST_CNT 0xffff
+#define MASK_ANLG_PHY_G0_RF_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_DIV_SEL 0x10
+#define MASK_ANLG_PHY_G0_RF_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_CLKDIV_EN 0x8
+#define MASK_ANLG_PHY_G0_RF_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN 0x4
+#define MASK_ANLG_PHY_G0_RF_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_RST 0x2
+#define MASK_ANLG_PHY_G0_RF_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_PD 0x1
+#define MASK_AUD_CP_APB_RF_TMR1_EB 0x40
+#define MASK_AUD_CP_APB_RF_TMR0_EB 0x20
+#define MASK_AUD_CP_APB_RF_RTC_WDG_EB 0x4
+#define MASK_AUD_CP_APB_RF_WDG_EB 0x2
+#define MASK_AUD_CP_APB_RF_TMR1_SOFT_RST 0x8
+#define MASK_AUD_CP_APB_RF_TMR0_SOFT_RST 0x4
+#define MASK_AUD_CP_APB_RF_WDG_SOFT_RST 0x2
+#define MASK_AUD_CP_APB_RF_AXI_LP_CTRL_DISABLE 0x10000
+#define MASK_AUD_CP_APB_RF_OCEM_RST_MASK 0x2
+#define MASK_AUD_CP_APB_RF_DSP_STATUS 0x1ff80000
+#define MASK_AUD_CP_APB_RF_WAKE_INT_MSK 0xffff
+#define MASK_AUD_CP_APB_RF_HIGH_RESERVED 0xffff0000
+#define MASK_AUD_CP_APB_RF_LOW_RESERVED 0xffff
+#define MASK_AUD_CP_APB_RF_IRAM_ENDIAN_SEL 0x1
+#define MASK_PUB_AHB_RF_SOFT_CMD_NUM 0x700
+#define MASK_PUB_AHB_RF_SOFT_CMD_FC_SEL 0x70
+#define MASK_PUB_AHB_RF_SOFT_CMD_RESP 0x8
+#define MASK_PUB_AHB_RF_SOFT_CMD_DONE 0x4
+#define MASK_PUB_AHB_RF_SOFT_CMD_START 0x1
+#define MASK_PUB_AHB_RF_SOFT_CMD_SEQL 0xffffffff
+#define MASK_PUB_AHB_RF_SOFT_CMD_SEQH 0xffffffff
+#define MASK_PUB_AHB_RF_SOFT_CMD_STEP 0xffffffff
+#define MASK_PUB_AHB_RF_MPU_DUMP_ADDR 0xffffffff
+#define MASK_PUB_AHB_RF_DMC_MPU_VIO_ADDR 0xffffffff
+#define MASK_PUB_AHB_RF_DMC_MPU_VIO_CMD 0xffffffff
+#define MASK_PUB_AHB_RF_DMC_MPU_VIO_INT_REQ 0x2
+#define MASK_PUB_AHB_RF_RF_MPU_EN 0x1
+#define MASK_PUB_AHB_RF_RF_MPU_CFG0 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG0_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG0_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG0_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG1 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG1_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG1_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG1_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG2 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG2_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG2_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG2_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG3 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG3_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG3_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG3_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG4 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG4_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG4_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG4_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG5 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG5_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG5_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG5_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG6 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG6_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG6_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG6_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG7 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG7_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG7_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG7_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG8 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG8_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG8_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG8_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG9 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG9_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG9_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG9_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG10 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG10_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG10_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG10_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG11 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG11_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG11_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG11_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG12 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG12_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG12_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG12_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG13 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG13_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG13_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG13_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG14 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG14_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG14_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG14_HIGH_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG15 0x1ff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG15_ID_MASK_VAL 0xffffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG15_LOW_RANGE 0x7ffffff
+#define MASK_PUB_AHB_RF_RF_MPU_CFG15_HIGH_RANGE 0x7ffffff
diff --git a/include/dt-bindings/soc/sprd,ums512-regs.h b/include/dt-bindings/soc/sprd,ums512-regs.h
new file mode 100644
index 000000000000..5e14d7886ed6
--- /dev/null
+++ b/include/dt-bindings/soc/sprd,ums512-regs.h
@@ -0,0 +1,2134 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Spreadtrum UMS512 SOC system global register file
+ *
+ * Copyright C 2022, Spreadtrum Communications Inc.
+ */
+
+#define REG_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM1_CTL 0x0000
+#define REG_ANLG_PHY_G4_RF_ANALOG_THM1_1_THM1_RESERVED_CTL 0x0004
+#define REG_ANLG_PHY_G4_RF_ANALOG_THM1_1_REG_SEL_CFG_0 0x0008
+#define REG_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_EFUSE_PIN_PW_CTL 0x000c
+#define REG_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_REG_SEL_CFG_0 0x0010
+#define REG_ANLG_PHY_G4_RF_ANALOG_EFUSE4K_CSI_PHY_POWER_CONTROL 0x0014
+#define REG_AP_CLK_CORE_CGM_AP_APB_CFG 0x0020
+#define REG_AP_CLK_CORE_CGM_IPI_CFG 0x0024
+#define REG_AP_CLK_CORE_CGM_UART0_CFG 0x0028
+#define REG_AP_CLK_CORE_CGM_UART1_CFG 0x002c
+#define REG_AP_CLK_CORE_CGM_UART2_CFG 0x0030
+#define REG_AP_CLK_CORE_CGM_I2C0_CFG 0x0034
+#define REG_AP_CLK_CORE_CGM_I2C1_CFG 0x0038
+#define REG_AP_CLK_CORE_CGM_I2C2_CFG 0x003c
+#define REG_AP_CLK_CORE_CGM_I2C3_CFG 0x0040
+#define REG_AP_CLK_CORE_CGM_I2C4_CFG 0x0044
+#define REG_AP_CLK_CORE_CGM_SPI0_CFG 0x0048
+#define REG_AP_CLK_CORE_CGM_SPI1_CFG 0x004c
+#define REG_AP_CLK_CORE_CGM_SPI2_CFG 0x0050
+#define REG_AP_CLK_CORE_CGM_SPI3_CFG 0x0054
+#define REG_AP_CLK_CORE_CGM_IIS0_CFG 0x0058
+#define REG_AP_CLK_CORE_CGM_IIS1_CFG 0x005c
+#define REG_AP_CLK_CORE_CGM_IIS2_CFG 0x0060
+#define REG_AP_CLK_CORE_CGM_SIM_CFG 0x0064
+#define REG_AP_CLK_CORE_CGM_CE_CFG 0x0068
+#define REG_AP_CLK_CORE_CGM_AP_EMMC_32K_CFG 0x006c
+#define REG_AP_CLK_CORE_CGM_AP_SDIO0_32K_CFG 0x0070
+#define REG_AP_CLK_CORE_CGM_AP_SDIO1_32K_CFG 0x0074
+#define REG_AP_CLK_CORE_CGM_AP_SDIO2_32K_CFG 0x0078
+#define REG_AP_CLK_CORE_CGM_AP_SIM_32K_CFG 0x007c
+#define REG_AP_CLK_CORE_CGM_SDIO0_2X_CFG 0x0080
+#define REG_AP_CLK_CORE_CGM_SDIO0_1X_CFG 0x0084
+#define REG_AP_CLK_CORE_CGM_SDIO1_2X_CFG 0x0088
+#define REG_AP_CLK_CORE_CGM_SDIO1_1X_CFG 0x008c
+#define REG_AP_CLK_CORE_CGM_EMMC_2X_CFG 0x0090
+#define REG_AP_CLK_CORE_CGM_EMMC_1X_CFG 0x0094
+#define REG_AP_CLK_CORE_CGM_VSP_CFG 0x0098
+#define REG_AP_CLK_CORE_CGM_DISPC0_CFG 0x009c
+#define REG_AP_CLK_CORE_CGM_DISPC0_DPI_CFG 0x00a0
+#define REG_AP_CLK_CORE_CGM_DSI_APB_CFG 0x00a4
+#define REG_AP_CLK_CORE_CGM_DSI_RXESC_CFG 0x00a8
+#define REG_AP_CLK_CORE_CGM_DSI_LANEBYTE_CFG 0x00ac
+#define REG_AP_CLK_CORE_CGM_VDSP_CFG 0x00b0
+#define REG_AP_CLK_CORE_CGM_VDSP_M_CFG 0x00b4
+#define REG_AP_CLK_CORE_CGM_DPHY_REF_CFG 0x00b8
+#define REG_AP_CLK_CORE_CGM_DPHY_CFG_CFG 0x00bc
+#define REG_AP_CLK_CORE_CGM_DSI_PHY_SCAN_ONLY_CFG 0x00c0
+#define REG_AP_AHB_RF_AHB_EB 0x0000
+#define REG_AP_AHB_RF_AHB_RST 0x0004
+#define REG_AP_AHB_RF_AP_SYS_FORCE_SLEEP_CFG 0x000c
+#define REG_AP_AHB_RF_AP_SYS_AUTO_SLEEP_CFG 0x0010
+#define REG_AP_AHB_RF_HOLDING_PEN 0x0014
+#define REG_AP_AHB_RF_CLOCK_FREQUENCY_DOWN 0x0018
+#define REG_AP_AHB_RF_AP_SYS_CLK_EN_FRC_OFF_0 0x0020
+#define REG_AP_AHB_RF_AP_SYS_CLK_EN_FRC_OFF_1 0x0024
+#define REG_AP_AHB_RF_AP_SYS_CLK_EN_FRC_ON_0 0x0028
+#define REG_AP_AHB_RF_AP_SYS_CLK_EN_FRC_ON_1 0x002c
+#define REG_AP_AHB_RF_MISC_CKG_EN 0x0040
+#define REG_AP_AHB_RF_VDSP_ASYNC_BRG 0x004c
+#define REG_AP_AHB_RF_DISP_ASYNC_BRG 0x0050
+#define REG_AP_AHB_RF_S6_LPC 0x0054
+#define REG_AP_AHB_RF_S5_LPC 0x0058
+#define REG_AP_AHB_RF_AP_ASYNC_BRG 0x005c
+#define REG_AP_AHB_RF_M0_LPC 0x0060
+#define REG_AP_AHB_RF_M1_LPC 0x0064
+#define REG_AP_AHB_RF_M2_LPC 0x0068
+#define REG_AP_AHB_RF_M3_LPC 0x006c
+#define REG_AP_AHB_RF_M4_LPC 0x0070
+#define REG_AP_AHB_RF_M5_LPC 0x0074
+#define REG_AP_AHB_RF_M6_LPC 0x0078
+#define REG_AP_AHB_RF_M7_LPC 0x007c
+#define REG_AP_AHB_RF_MAIN_LPC 0x0088
+#define REG_AP_AHB_RF_S0_LPC 0x008c
+#define REG_AP_AHB_RF_S1_LPC 0x0090
+#define REG_AP_AHB_RF_S2_LPC 0x0094
+#define REG_AP_AHB_RF_S3_LPC 0x0098
+#define REG_AP_AHB_RF_S4_LPC 0x009c
+#define REG_AP_AHB_RF_MERGE_M0_LPC 0x00a0
+#define REG_AP_AHB_RF_MERGE_M1_LPC 0x00a4
+#define REG_AP_AHB_RF_S7_LPC 0x00a8
+#define REG_AP_AHB_RF_MERGE_S0_LPC 0x00ac
+#define REG_AP_AHB_RF_AP_QOS0 0x00b0
+#define REG_AP_AHB_RF_AP_QOS1 0x00b8
+#define REG_AP_AHB_RF_AP_QOS2 0x00bc
+#define REG_AP_AHB_RF_ASYNC_BRIDGE_IDLE_OVERFLOW 0x00c0
+#define REG_AP_AHB_RF_ASYNC_BRIDGE_DEBUG_SIGNAL_W_DISP 0x00c8
+#define REG_AP_AHB_RF_ASYNC_BRIDGE_DEBUG_SIGNAL_W_AP 0x00cc
+#define REG_AP_AHB_RF_ASYNC_BRIDGE_DEBUG_SIGNAL_W_VDSP 0x00d0
+#define REG_AP_AHB_RF_AP_QOS3 0x00d4
+#define REG_AP_AHB_RF_AP_QOS3_SEL 0x00d8
+#define REG_AP_AHB_RF_MERGE_VDSP_M0_LPC 0x0100
+#define REG_AP_AHB_RF_MERGE_VDSP_M1_LPC 0x0104
+#define REG_AP_AHB_RF_MERGE_VDSP_M2_LPC 0x0108
+#define REG_AP_AHB_RF_MERGE_VDSP_M3_LPC 0x010c
+#define REG_AP_AHB_RF_MERGE_VDSP_MAIN_LPC 0x0110
+#define REG_AP_AHB_RF_MERGE_VDSP_S0_LPC 0x0114
+#define REG_AP_AHB_RF_MERGE_VDSP_S1_LPC 0x0118
+#define REG_AP_AHB_RF_MERGE_VDMA_M0_LPC 0x011c
+#define REG_AP_AHB_RF_MERGE_VDMA_M1_LPC 0x0120
+#define REG_AP_AHB_RF_MERGE_VDMA_S0_LPC 0x0124
+#define REG_AP_AHB_RF_SYS_RST 0x3010
+#define REG_AP_AHB_RF_CACHE_EMMC_SDIO 0x3014
+#define REG_AP_AHB_RF_AP_QOS_CFG 0x301c
+#define REG_AP_AHB_RF_DSI_PHY 0x3034
+#define REG_AP_AHB_RF_VDSP_FUNC_CTRL 0x3084
+#define REG_AP_AHB_RF_VDSP_FATAL_INFO_LOW 0x3088
+#define REG_AP_AHB_RF_VDSP_FATAL_INFO_HIGH 0x308c
+#define REG_AP_AHB_RF_VDSP_LP_CTRL 0x3090
+#define REG_AP_AHB_RF_VDSP_INT_CTRL 0x3094
+#define REG_AP_AHB_RF_CHIP_ID 0x30fc
+#define REG_AP_DVFS_APB_RF_AP_DVFS_HOLD_CTRL 0x0000
+#define REG_AP_DVFS_APB_RF_AP_DVFS_WAIT_WINDOW_CFG 0x0004
+#define REG_AP_DVFS_APB_RF_AP_DFS_EN_CTRL 0x0008
+#define REG_AP_DVFS_APB_RF_AP_SW_TRIG_CTRL 0x000c
+#define REG_AP_DVFS_APB_RF_AP_MIN_VOLTAGE_CFG 0x0010
+#define REG_AP_DVFS_APB_RF_AP_SW_DVFS_CTRL 0x0034
+#define REG_AP_DVFS_APB_RF_AP_FREQ_UPDATE_BYPASS 0x0038
+#define REG_AP_DVFS_APB_RF_CGM_AP_DVFS_CLK_GATE_CTRL 0x003c
+#define REG_AP_DVFS_APB_RF_AP_DVFS_VOLTAGE_DBG 0x0040
+#define REG_AP_DVFS_APB_RF_AP_DVFS_CGM_CFG_DBG 0x004c
+#define REG_AP_DVFS_APB_RF_AP_DVFS_STATE_DBG 0x0050
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX0_MAP 0x0054
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX1_MAP 0x0058
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX2_MAP 0x005c
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX3_MAP 0x0060
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX4_MAP 0x0064
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX5_MAP 0x0068
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX6_MAP 0x006c
+#define REG_AP_DVFS_APB_RF_VDSP_INDEX7_MAP 0x0070
+#define REG_AP_DVFS_APB_RF_VSP_INDEX0_MAP 0x0074
+#define REG_AP_DVFS_APB_RF_VSP_INDEX1_MAP 0x0078
+#define REG_AP_DVFS_APB_RF_VSP_INDEX2_MAP 0x007c
+#define REG_AP_DVFS_APB_RF_VSP_INDEX3_MAP 0x0080
+#define REG_AP_DVFS_APB_RF_VSP_INDEX4_MAP 0x0084
+#define REG_AP_DVFS_APB_RF_VSP_INDEX5_MAP 0x0088
+#define REG_AP_DVFS_APB_RF_VSP_INDEX6_MAP 0x008c
+#define REG_AP_DVFS_APB_RF_VSP_INDEX7_MAP 0x0090
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX0_MAP 0x0094
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX1_MAP 0x0098
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX2_MAP 0x009c
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX3_MAP 0x0100
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX4_MAP 0x0104
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX5_MAP 0x0108
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX6_MAP 0x010c
+#define REG_AP_DVFS_APB_RF_DISPC_INDEX7_MAP 0x0110
+#define REG_AP_DVFS_APB_RF_VDSP_DVFS_INDEX_CFG 0x0114
+#define REG_AP_DVFS_APB_RF_VDSP_DVFS_INDEX_IDLE_CFG 0x0118
+#define REG_AP_DVFS_APB_RF_VSP_DVFS_INDEX_CFG 0x011c
+#define REG_AP_DVFS_APB_RF_VSP_DVFS_INDEX_IDLE_CFG 0x0120
+#define REG_AP_DVFS_APB_RF_DISPC_DVFS_INDEX_CFG 0x0124
+#define REG_AP_DVFS_APB_RF_DISPC_DVFS_INDEX_IDLE_CFG 0x0128
+#define REG_AP_DVFS_APB_RF_AP_FREQ_UPD_STATE 0x012c
+#define REG_AP_DVFS_APB_RF_AP_GFREE_WAIT_DELAY_CFG 0x0130
+#define REG_AP_DVFS_APB_RF_AP_FREQ_UPD_TYPE_CFG 0x0134
+#define REG_AP_DVFS_APB_RF_AP_DFS_IDLE_DISABLE_CFG 0x0140
+#define REG_AP_DVFS_APB_RF_AP_DVFS_RESERVED_REG_CFG0 0x0150
+#define REG_AP_DVFS_APB_RF_AP_DVFS_RESERVED_REG_CFG1 0x0154
+#define REG_AP_DVFS_APB_RF_AP_DVFS_RESERVED_REG_CFG2 0x0158
+#define REG_AP_DVFS_APB_RF_AP_DVFS_RESERVED_REG_CFG3 0x015c
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_HOLD_CTRL 0x0000
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_WAIT_WINDOW_CFG1 0x0008
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_WAIT_WINDOW_CFG2 0x000c
+#define REG_APCPU_DVFS_APB_RF_APCPU_CPU1_MIN_VOLTAGE_CFG0 0x0010
+#define REG_APCPU_DVFS_APB_RF_APCPU_CPU0_MIN_VOLTAGE_CFG0 0x0014
+#define REG_APCPU_DVFS_APB_RF_AUTO_TUNE_CFG 0x0018
+#define REG_APCPU_DVFS_APB_RF_DFS_IDLE_DISABLE_CFG 0x001c
+#define REG_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU0_SW_DVFS_CTRL 0x0020
+#define REG_APCPU_DVFS_APB_RF_APCPU_DCDC_CPU1_SW_DVFS_CTRL 0x0024
+#define REG_APCPU_DVFS_APB_RF_APCPU_FREQ_UPDATE_BYPASS 0x0028
+#define REG_APCPU_DVFS_APB_RF_CGM_APCPU_DVFS_CLK_GATE_CTRL 0x002c
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_VOLTAGE_DBG 0x0030
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_VOLTAGE_DBG0 0x0034
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_CGM_CFG_DBG0 0x0038
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_CGM_CFG_DBG1 0x003c
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_CGM_CFG_DBG2 0x0040
+#define REG_APCPU_DVFS_APB_RF_APCPU_CPU0_DVFS_STATE_DBG 0x0044
+#define REG_APCPU_DVFS_APB_RF_APCPU_CPU1_DVFS_STATE_DBG 0x004c
+#define REG_APCPU_DVFS_APB_RF_ANANKE_LITE_PROMETHEUS_VOTE_DCDC_CPU0_CFG 0x0050
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX0 0x0060
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX1 0x0064
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX2 0x0068
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX3 0x006c
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX4 0x0070
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX5 0x0074
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX6 0x0078
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX7 0x007c
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX8 0x0080
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX9 0x0084
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX10 0x0088
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX11 0x008c
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX12 0x0090
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX13 0x0094
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX14 0x0098
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX15 0x009c
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX0 0x00a0
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX1 0x00a4
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX2 0x00a8
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX3 0x00ac
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX4 0x00b0
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX5 0x00b4
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX6 0x00b8
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX7 0x00bc
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX8 0x00c0
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX9 0x00c4
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX10 0x00c8
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX11 0x00cc
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX12 0x00d0
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX13 0x00d4
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX14 0x00d8
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX15 0x00dc
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX0 0x0180
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX1 0x0184
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX2 0x0188
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX3 0x018c
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX4 0x0190
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX5 0x0194
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX6 0x0198
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX7 0x019c
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX8 0x01a0
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX9 0x01a4
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX10 0x01a8
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX11 0x01ac
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX12 0x01b0
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX13 0x01b4
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX14 0x01b8
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX15 0x01bc
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX0 0x01d4
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX1 0x01d8
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX2 0x01dc
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX3 0x01e0
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX4 0x01e4
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX5 0x01e8
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX6 0x01ec
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX7 0x01f0
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX0 0x01f4
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX1 0x01f8
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX2 0x01fc
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX3 0x0200
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX4 0x0204
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX5 0x0208
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX6 0x020c
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX7 0x0210
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX_CFG 0x0214
+#define REG_APCPU_DVFS_APB_RF_ANANKE_DVFS_INDEX_IDLE_CFG 0x0218
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX_CFG 0x0224
+#define REG_APCPU_DVFS_APB_RF_PROMETHEUS_DVFS_INDEX_IDLE_CFG 0x0228
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX_CFG 0x022c
+#define REG_APCPU_DVFS_APB_RF_APCPU_SCU_DVFS_INDEX_IDLE_CFG 0x0230
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX_CFG 0x0234
+#define REG_APCPU_DVFS_APB_RF_APCPU_ATB_DVFS_INDEX_IDLE_CFG 0x0238
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX_CFG 0x023c
+#define REG_APCPU_DVFS_APB_RF_APCPU_PERIPH_DVFS_INDEX_IDLE_CFG 0x0240
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_CTRL_CFG 0x0244
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_DELAY_CFG0 0x0248
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_DELAY_CFG1 0x024c
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_DELAY_CFG2 0x0250
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_DELAY_CFG3 0x0254
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_CTRL_CFG 0x0258
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_DELAY_CFG0 0x025c
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_DELAY_CFG1 0x0260
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_DELAY_CFG2 0x0264
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_DELAY_CFG3 0x0268
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_CTRL_CFG 0x026c
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_DELAY_CFG0 0x0270
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_DELAY_CFG1 0x0274
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_DELAY_CFG2 0x0278
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_DELAY_CFG3 0x027c
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX0 0x0280
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX1 0x0284
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX2 0x0288
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX3 0x028c
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX4 0x0290
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX5 0x0294
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX6 0x0298
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX7 0x029c
+#define REG_APCPU_DVFS_APB_RF_MPLL_DVFS_STATE_DEBUG 0x02a0
+#define REG_APCPU_DVFS_APB_RF_APCPU_FREQ_UPDATE_STATE0 0x02a4
+#define REG_APCPU_DVFS_APB_RF_CGM_RELOCK_BYP_CFG0 0x02a8
+#define REG_APCPU_DVFS_APB_RF_APCPU_GFREE_WAIT_DELAY_CFG0 0x02ac
+#define REG_APCPU_DVFS_APB_RF_APCPU_GFREE_WAIT_DELAY_CFG1 0x02b0
+#define REG_APCPU_DVFS_APB_RF_APCPU_GFREE_WAIT_DELAY_CFG2 0x02b4
+#define REG_APCPU_DVFS_APB_RF_APCPU_GFREE_WAIT_DELAY_CFG3 0x02b8
+#define REG_APCPU_DVFS_APB_RF_MPLL0_DVFS_DELAY_CFG4 0x02bc
+#define REG_APCPU_DVFS_APB_RF_MPLL1_DVFS_DELAY_CFG4 0x02c0
+#define REG_APCPU_DVFS_APB_RF_MPLL2_DVFS_DELAY_CFG4 0x02c4
+#define REG_APCPU_DVFS_APB_RF_CGM_RELOCK_BYP_CFG1 0x02c8
+#define REG_APCPU_DVFS_APB_RF_APCPU_FREQ_UPD_TYPE_CFG 0x02cc
+#define REG_APCPU_DVFS_APB_RF_MPLL_INDEX_READ 0x02d0
+#define REG_APCPU_DVFS_APB_RF_APCPU_FREQ_UPDATE_STATE1 0x02d4
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX_CFG 0x02e0
+#define REG_APCPU_DVFS_APB_RF_APCPU_GIC_DVFS_INDEX_IDLE_CFG 0x02e4
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_RESERVED_REG_CFG0 0x02f0
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_RESERVED_REG_CFG1 0x02f4
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_RESERVED_REG_CFG2 0x02f8
+#define REG_APCPU_DVFS_APB_RF_APCPU_DVFS_RESERVED_REG_CFG3 0x02fc
+#define REG_REG_FW0_AP_REG_RD_CTRL_0 0x0000
+#define REG_REG_FW0_AP_REG_WR_CTRL_0 0x0004
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY0 0x0008
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY1 0x000c
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY2 0x0010
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY3 0x0014
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY4 0x0018
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY5 0x001c
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY6 0x0020
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY7 0x0024
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY8 0x0028
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY9 0x002c
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY10 0x0030
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY11 0x0034
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY12 0x0038
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY13 0x003c
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY14 0x0040
+#define REG_REG_FW0_AP_BIT_CTRL_ADDR_ARRAY15 0x0044
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY0 0x0048
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY1 0x004c
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY2 0x0050
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY3 0x0054
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY4 0x0058
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY5 0x005c
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY6 0x0060
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY7 0x0064
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY8 0x0068
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY9 0x006c
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY10 0x0070
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY11 0x0074
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY12 0x0078
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY13 0x007c
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY14 0x0080
+#define REG_REG_FW0_AP_BIT_CTRL_ARRAY15 0x0084
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_HOLD_CTRL 0x0000
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_WAIT_WINDOW_CFG 0x0004
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_SW_DVFS_CTRL 0x001c
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_FREQ_UPDATE_BYPASS 0x0020
+#define REG_AUDCP_DVFS_AHB_RF_CGM_AUDCP_DVFS_CLK_GATE_CTRL 0x0024
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_VOLTAGE_DBG 0x0028
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_CGM_CFG_DBG 0x0030
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_STATE_DBG 0x0034
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX0_MAP 0x0038
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX1_MAP 0x003c
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX2_MAP 0x0040
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX3_MAP 0x0044
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX4_MAP 0x0048
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX5_MAP 0x004c
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX6_MAP 0x0050
+#define REG_AUDCP_DVFS_AHB_RF_AUDDSP_INDEX7_MAP 0x0054
+#define REG_AUDCP_DVFS_AHB_RF_DSP_DVFS_INDEX_CFG 0x0058
+#define REG_AUDCP_DVFS_AHB_RF_DSP_DVFS_INDEX_IDLE_CFG 0x005c
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_FREQ_UPD_STATE 0x0060
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_GFREE_WAIT_DELAY_CFG 0x0064
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_FREQ_UPD_TYPE_CFG 0x0068
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DFS_IDLE_DISABLE_CFG 0x0070
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_RESERVED_REG_CFG0 0x0080
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_RESERVED_REG_CFG1 0x0084
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_RESERVED_REG_CFG2 0x0088
+#define REG_AUDCP_DVFS_AHB_RF_AUDCP_DVFS_RESERVED_REG_CFG3 0x008c
+#define REG_AUD_CP_CLK_CORE_CGM_DSP_CORE_CFG 0x0020
+#define REG_AUD_CP_CLK_CORE_CGM_DSP_AXI_CFG 0x0024
+#define REG_AUD_CP_CLK_CORE_CGM_DSP_AHB_CFG 0x0028
+#define REG_AUD_CP_CLK_CORE_CGM_DSP_APB_CFG 0x002c
+#define REG_AUD_CP_CLK_CORE_CGM_IIS0_CFG 0x0030
+#define REG_AUD_CP_CLK_CORE_CGM_IIS1_CFG 0x0034
+#define REG_AUD_CP_CLK_CORE_CGM_IIS2_CFG 0x0038
+#define REG_AUD_CP_CLK_CORE_CGM_UART_CFG 0x003c
+#define REG_AUD_CP_CLK_CORE_CGM_TMR_26M_CFG 0x0040
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_CFG 0x0044
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_24M_CFG 0x0048
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_IFD_CFG 0x004c
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_IIS0_CFG 0x0050
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_IIS1_CFG 0x0054
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_IIS2_CFG 0x0058
+#define REG_AUD_CP_CLK_CORE_CGM_VBC_IIS3_CFG 0x005c
+#define REG_AUD_CP_CLK_CORE_CGM_TDM_SLV_CFG 0x0060
+#define REG_AUD_CP_CLK_CORE_CGM_SRC48K_CFG 0x0064
+#define REG_AUD_CP_CLK_CORE_CGM_AUD_CFG 0x0068
+#define REG_AUD_CP_CLK_CORE_CGM_AUDIF_CFG 0x006c
+#define REG_AUD_CP_CLK_CORE_CGM_AUDCP_DVFS_CFG 0x0070
+#define REG_PUB_APB_RF_DDR_EB 0x0000
+#define REG_PUB_APB_RF_DDR_SOFT_RST 0x0004
+#define REG_PUB_APB_RF_DMC_EXT_LPCTRL_CFG 0x31a0
+#define REG_PUB_APB_RF_DMC_EXT_LPCTRL_SEQL 0x31a4
+#define REG_PUB_APB_RF_DMC_EXT_LPCTRL_SEQH 0x31a8
+#define REG_PUB_APB_RF_DMC_EXT_LPCTRL_STEP 0x31ac
+#define REG_PUB_APB_RF_QOS_SELECT 0x31b0
+#define REG_PUB_APB_RF_DPLL_PRE_DIV_STATUS 0x31c0
+#define REG_PUB_APB_RF_DFI_BWMON_TIMER 0x31c4
+#define REG_PUB_APB_RF_QOS_SWITCH 0x31c8
+#define REG_PUB_APB_RF_PUB_BUS_CK_EB 0x31cc
+#define REG_PUB_APB_RF_AXI_LPC_CTRL_3 0x31d0
+#define REG_PUB_APB_RF_PUB_INT_CG_EN 0x31d4
+#define REG_PUB_APB_RF_TIMER_ENABLE 0x31d8
+#define REG_PUB_APB_RF_VOTE_CTRL 0x31e0
+#define REG_PUB_APB_RF_VOTE_STATUS 0x31e4
+#define REG_PUB_APB_RF_DFS_HW_CTRL3 0x31f0
+#define REG_PUB_APB_RF_QOS_FIXED_CTRL0 0x31f4
+#define REG_PUB_APB_RF_QOS_FIXED_CTRL1 0x31f8
+#define REG_PUB_APB_RF_QOS_FIXED_CTRL2 0x31fc
+#define REG_PUB_APB_RF_PUB_AXI_QOS_URGENT_REG_0 0x3200
+#define REG_PUB_APB_RF_PUB_AXI_QOS_URGENT_REG_1 0x3204
+#define REG_PUB_APB_RF_PUB_INT_CTRL 0x32f0
+#define REG_PUB_APB_RF_DFS_STATUS 0x32f4
+#define REG_PUB_APB_RF_DFS_STATUS1 0x32f8
+#define REG_PUB_APB_RF_DFS_FC_REQ_DELAY 0x32fc
+#define REG_PUB_APB_RF_PUB_LP_GEN_CTRL 0x333c
+#define REG_PUB_APB_RF_AXI_LPC_CTRL_0 0x334c
+#define REG_PUB_APB_RF_AXI_LPC_CTRL_1 0x3350
+#define REG_PUB_APB_RF_AXI_LPC_CTRL_2 0x3354
+#define REG_PUB_APB_RF_FENCING_CTRL 0x3358
+#define REG_PUB_APB_RF_CP_BASE_ADDR 0x3360
+#define REG_PUB_APB_RF_CLK_PUB_DFS_CTRL 0x3364
+#define REG_PUB_APB_RF_BIST_CTRL 0x3400
+#define REG_PUB_APB_RF_DMC_SOFT_RST_CTRL 0x3404
+#define REG_PUB_APB_RF_MC_IDLE_WAIT_CTRL 0x3414
+#define REG_PUB_APB_RF_QOS_THRESHOLD_0 0x3418
+#define REG_PUB_APB_RF_QOS_THRESHOLD_1 0x341c
+#define REG_PUB_APB_RF_DMC_DDR_CLK_CTRL 0x4000
+#define REG_PUB_APB_RF_DMC_CLK_INIT_SW_START 0x4004
+#define REG_PUB_APB_RF_DMC_CLK_STATE 0x4008
+#define REG_PUB_APB_RF_DMC_CLK_INIT_CFG 0x400c
+#define REG_PUB_APB_RF_DMC_DESKEW_WAIT_CFG 0x4010
+#define REG_PUB_APB_RF_DMC_DESKEW_WAIT_CNT0 0x4014
+#define REG_PUB_APB_RF_DMC_DESKEW_WAIT_CNT1 0x4018
+#define REG_PUB_APB_RF_DMC_DESKEW_WAIT_CNT2 0x401c
+#define REG_PUB_APB_RF_DMC_DESKEW_WAIT_CNT3 0x4020
+#define REG_PUB_APB_RF_DMC_DDL_CTRL 0x402c
+#define REG_PUB_APB_RF_DFS_PURE_SW_CTRL 0x4100
+#define REG_PUB_APB_RF_DFS_SW_CTRL 0x4104
+#define REG_PUB_APB_RF_DFS_SW_CTRL1 0x4108
+#define REG_PUB_APB_RF_DFS_SW_CTRL2 0x410c
+#define REG_PUB_APB_RF_DFS_SW_CTRL3 0x4110
+#define REG_PUB_APB_RF_DFS_HW_CTRL 0x4114
+#define REG_PUB_APB_RF_DFS_HW_CTRL1 0x4118
+#define REG_PUB_APB_RF_DFS_HW_CTRL2 0x411c
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET0 0x4120
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET1 0x4124
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET2 0x4128
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET3 0x412c
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET4 0x4130
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET5 0x4134
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET6 0x4138
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET7 0x413c
+#define REG_PUB_APB_RF_DFS_HW_RATIO_SET8 0x4140
+#define REG_PUB_APB_RF_HW_DESKEWPLL_PD_CTRL0 0x4144
+#define REG_PUB_APB_RF_HW_DESKEWPLL_PD_CTRL1 0x4148
+#define REG_PUB_APB_RF_DVS_CTRL_0 0x4150
+#define REG_PUB_APB_RF_DVS_CTRL_1 0x4154
+#define REG_PUB_APB_RF_DVS_CTRL_2 0x4158
+#define REG_PUB_APB_RF_DVS_DEC_BLOCK_TIME 0x415c
+#define REG_PUB_APB_RF_VOTE_MASTER_EN 0x4310
+#define REG_PUB_APB_RF_VOTE_FSM_CNT 0x4314
+#define REG_PUB_APB_RF_THRESHOLD_INC_FREQ_0 0x4318
+#define REG_PUB_APB_RF_THRESHOLD_INC_FREQ_1 0x431c
+#define REG_PUB_APB_RF_THRESHOLD_INC_FREQ_2 0x4320
+#define REG_PUB_APB_RF_THRESHOLD_INC_FREQ_3 0x4324
+#define REG_PUB_APB_RF_TEST_DSKPLL_BIST_CNT 0x4328
+#define REG_PUB_APB_RF_PUB_STATUS_MON_CTRL 0x6200
+#define REG_PUB_APB_RF_PUB_ST_IDLE_CYC_CNT 0x6204
+#define REG_PUB_APB_RF_PUB_ST_WR_CYC_CNT 0x6208
+#define REG_PUB_APB_RF_PUB_ST_RD_CYC_CNT 0x620c
+#define REG_PUB_APB_RF_PUB_ST_SR_CYC_CNT 0x6210
+#define REG_PUB_APB_RF_PUB_ST_LS_CYC_CNT 0x6214
+#define REG_PUB_APB_RF_PUB_ST_LS_TIME_CNT 0x6218
+#define REG_PUB_APB_RF_PUB_DFS_F0_CYC_CNT 0x621c
+#define REG_PUB_APB_RF_PUB_DFS_F1_CYC_CNT 0x6220
+#define REG_PUB_APB_RF_PUB_DFS_F2_CYC_CNT 0x6224
+#define REG_PUB_APB_RF_PUB_DFS_F3_CYC_CNT 0x6228
+#define REG_PUB_APB_RF_PUB_DFS_F4_CYC_CNT 0x622c
+#define REG_PUB_APB_RF_PUB_DFS_F5_CYC_CNT 0x6230
+#define REG_PUB_APB_RF_PUB_DFS_F6_CYC_CNT 0x6234
+#define REG_PUB_APB_RF_PUB_DFS_F7_CYC_CNT 0x6238
+#define REG_PUB_APB_RF_PUB_DFS_CNT 0x623c
+#define REG_PUB_APB_RF_VOTE_CTRL_DPU 0x6400
+#define REG_PUB_APB_RF_VOTE_CTRL_DCAM 0x6404
+#define REG_PUB_APB_RF_VOTE_CTRL_PUBCP 0x6408
+#define REG_PUB_APB_RF_VOTE_CTRL_WTLCP 0x640c
+#define REG_PUB_APB_RF_VOTE_CTRL_WTLCP1 0x6410
+#define REG_PUB_APB_RF_VOTE_CTRL_AGCP 0x6414
+#define REG_PUB_APB_RF_VOTE_CTRL_SW 0x6418
+#define REG_PUB_APB_RF_VOTE_CTRL_VDSP 0x641c
+#define REG_PUB_APB_RF_DFS_GFREE_CTRL 0x6500
+#define REG_PUB_APB_RF_DFS_SW_CTRL_APPEND 0x6600
+#define REG_PUB_APB_RF_AWURGENT_DBG_CTRL 0x6800
+#define REG_PUB_APB_RF_ARURGENT_DBG_CTRL 0x6804
+#define REG_PUB_APB_RF_LSLP_SRE_SIM 0x6808
+#define REG_PUB_APB_RF_PUB0_DUMMY_REG0 0x8000
+#define REG_PUB_APB_RF_PUB0_DUMMY_REG1 0x8004
+#define REG_REG_FW1_AP_REG_RD_CTRL_0 0x0000
+#define REG_REG_FW1_AP_REG_RD_CTRL_1 0x0004
+#define REG_REG_FW1_AP_REG_WR_CTRL_0 0x0008
+#define REG_REG_FW1_AP_REG_WR_CTRL_1 0x000c
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY0 0x0010
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY1 0x0014
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY2 0x0018
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY3 0x001c
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY4 0x0020
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY5 0x0024
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY6 0x0028
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY7 0x002c
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY8 0x0030
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY9 0x0034
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY10 0x0038
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY11 0x003c
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY12 0x0040
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY13 0x0044
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY14 0x0048
+#define REG_REG_FW1_AP_BIT_CTRL_ADDR_ARRAY15 0x004c
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY0 0x0050
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY1 0x0054
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY2 0x0058
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY3 0x005c
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY4 0x0060
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY5 0x0064
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY6 0x0068
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY7 0x006c
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY8 0x0070
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY9 0x0074
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY10 0x0078
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY11 0x007c
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY12 0x0080
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY13 0x0084
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY14 0x0088
+#define REG_REG_FW1_AP_BIT_CTRL_ARRAY15 0x008c
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXCLKLANE 0x0000
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_0 0x0004
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_1 0x0008
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_2 0x000c
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATA_3 0x0010
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TXDATAESC 0x0014
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_STATE_RX 0x0018
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_ERR 0x001c
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_CTRL 0x0020
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_RSVD 0x0024
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_TEST 0x0028
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_4L_DATALANE_CTRL 0x002c
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_MIPI_CTRL7 0x0030
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_DSI_ISO_SW 0x0034
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_0 0x0038
+#define REG_ANLG_PHY_G1_RF_ANALOG_MIPI_DSI_4LANE_REG_SEL_CFG_1 0x003c
+#define REG_AON_SEC_APB_RF_CHIP_KPRTL_0 0x0000
+#define REG_AON_SEC_APB_RF_CHIP_KPRTL_1 0x0004
+#define REG_AON_SEC_APB_RF_CHIP_KPRTL_2 0x0008
+#define REG_AON_SEC_APB_RF_CHIP_KPRTL_3 0x000c
+#define REG_AON_SEC_APB_RF_SEC_EB 0x0010
+#define REG_AON_SEC_APB_RF_SEC_SOFT_RST 0x0014
+#define REG_AON_SEC_APB_RF_FUNC_DMA_EN 0x0018
+#define REG_AON_SEC_APB_RF_AON_SEC_EB 0x001c
+#define REG_AON_SEC_APB_RF_SECURE_EFUSE_BOUNDRY 0x0020
+#define REG_AON_SEC_APB_RF_APCPU_APB_EB 0x0024
+#define REG_AON_SEC_APB_RF_APCPU_SOFT_RST 0x0028
+#define REG_AON_SEC_APB_RF_APCPU_CORE0_3_CLK_CFG 0x002c
+#define REG_AON_SEC_APB_RF_APCPU_CORE4_7_CLK_CFG 0x0030
+#define REG_AON_SEC_APB_RF_APCPU_BUS_CLK_CFG 0x0038
+#define REG_AON_SEC_APB_RF_APCPU_TOP_MISC_CLK_CFG 0x003c
+#define REG_AON_SEC_APB_RF_RVBARADDR0 0x0040
+#define REG_AON_SEC_APB_RF_RVBARADDR1 0x0044
+#define REG_AON_SEC_APB_RF_RVBARADDR2 0x0048
+#define REG_AON_SEC_APB_RF_RVBARADDR3 0x004c
+#define REG_AON_SEC_APB_RF_RVBARADDR4 0x0050
+#define REG_AON_SEC_APB_RF_RVBARADDR5 0x0054
+#define REG_AON_SEC_APB_RF_RVBARADDR6 0x0058
+#define REG_AON_SEC_APB_RF_RVBARADDR7 0x005c
+#define REG_AON_SEC_APB_RF_APCPU_CFG_CTRL 0x0060
+#define REG_AON_SEC_APB_RF_AON_SEC_APB_RSV_0 0x0070
+#define REG_AON_SEC_APB_RF_AON_SEC_APB_RSV_1 0x0074
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CTRL0 0x0000
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CTRL1 0x0004
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CTRL2 0x0008
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_PERFOR 0x000c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_CTRL3 0x0010
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TWPLL_BIST_CTRL 0x0014
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CTRL0 0x0018
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CTRL1 0x001c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CTRL2 0x0020
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_PERFOR 0x0024
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_CTRL3 0x0028
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_LPLL_BIST_CTRL 0x002c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CTRL0 0x0030
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CTRL1 0x0034
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CTRL2 0x0038
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_PERFOR 0x003c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CTRL3 0x0040
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_ISPPLL_CTRL4 0x0044
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CTRL0 0x0048
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CTRL1 0x004c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CTRL2 0x0050
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_PERFOR 0x0054
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CTRL3 0x0058
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_BIST_CTRL 0x005c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CTRL0 0x0060
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CTRL1 0x0064
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CTRL2 0x0068
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_PERFOR 0x006c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_CTRL3 0x0070
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_CPLL_BIST_CTRL 0x0074
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_TEST_CLK_CTRL 0x0078
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_GPLL_CTRL4 0x007c
+#define REG_ANLG_PHY_GC_RF_ANALOG_PLL_TOP_REG_SEL_CFG_0 0x0080
+#define REG_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM1_CTL 0x0084
+#define REG_ANLG_PHY_GC_RF_ANALOG_THM1_0_THM1_RESERVED_CTL 0x0088
+#define REG_ANLG_PHY_GC_RF_ANALOG_THM1_0_REG_SEL_CFG_0 0x008c
+#define REG_ANLG_PHY_G2_ANALOG_USB20_REG_SEL_CFG_0 0x0074
+#define REG_ANLG_PHY_G2_ANALOG_USB20_USB20_BATTER_PLL 0x005c
+#define REG_ANLG_PHY_G2_ANALOG_USB20_USB20_ISO_SW 0x0070
+#define REG_ANLG_PHY_G2_ANALOG_USB20_USB20_TRIMMING 0x0064
+#define REG_ANLG_PHY_G2_ANALOG_USB20_USB20_UTMI_CTL1 0x0058
+#define REG_ANLG_PHY_G2_ANALOG_USB20_USB20_UTMI_CTL2 0x0060
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL0 0x0000
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL1 0x0004
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL2 0x0008
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL3 0x000c
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL4 0x0010
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL5 0x0014
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL6 0x0018
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL7 0x001c
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_MPLL1_CTRL8 0x0020
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX0 0x0024
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX1 0x0028
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX2 0x002c
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX3 0x0030
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX4 0x0034
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX5 0x0038
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX6 0x003c
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_PROMETHEUS_DVFS_INDEX7 0x0040
+#define REG_ANLG_PHY_G2_RF_ANALOG_MPLL1_REG_SEL_CFG_0 0x0044
+#define REG_ANLG_PHY_G2_RF_ANALOG_THM2_THM2_CTL 0x0048
+#define REG_ANLG_PHY_G2_RF_ANALOG_THM2_THM2_RESERVED_CTL 0x004c
+#define REG_ANLG_PHY_G2_RF_ANALOG_THM2_REG_SEL_CFG_0 0x0050
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TEST_PIN 0x0054
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_UTMI_CTL1 0x0058
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_BATTER_PLL 0x005c
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_UTMI_CTL2 0x0060
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_TRIMMING 0x0064
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PHY_TUNE_CTL 0x0068
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_PHY_BIST_TEST 0x006c
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_USB20_ISO_SW 0x0070
+#define REG_ANLG_PHY_G2_RF_ANALOG_USB20_REG_SEL_CFG_0 0x0074
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CTRL0 0x0078
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CTRL1 0x007c
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CTRL2 0x0080
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CTRL3 0x0084
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_RG_EPLL_CTRL4 0x0088
+#define REG_ANLG_PHY_G2_RF_ANALOG_EPLL_TOP_REG_SEL_CFG_0 0x008c
+#define REG_AON_DBG_APB_RF_APCPU_COMM_CTRL 0x0000
+#define REG_AON_DBG_APB_RF_APCPU_PROT_CTRL 0x0004
+#define REG_AON_DBG_APB_RF_CSSYS_CFG 0x0008
+#define REG_AON_DBG_APB_RF_CR5_PROT_CTRL 0x000c
+#define REG_AON_DBG_APB_RF_APCPU_PROT_CTRL_NON_SEC 0x0010
+#define REG_AON_DBG_APB_RF_CSSYS_CFG_NON_SEC 0x0014
+#define REG_AON_DBG_APB_RF_CR5_PROT_CTRL_NON_SEC 0x0018
+#define REG_AON_DBG_APB_RF_DEBUG_BOND_OPTION 0x001c
+#define REG_SCC_APB_RF_SCC_TUNE_LMT_CFG 0x0000
+#define REG_SCC_APB_RF_SCC_TUNE_STATUS 0x0004
+#define REG_SCC_APB_RF_SCC_CFG 0x0008
+#define REG_SCC_APB_RF_SCC_TUNE_STEP_CFG 0x000c
+#define REG_SCC_APB_RF_SCC_WAIT_CFG 0x0010
+#define REG_SCC_APB_RF_SCC_INT_CFG 0x0014
+#define REG_SCC_APB_RF_SCC_TUNE_MARK 0x0024
+#define REG_SCC_APB_RF_SCC_FSM_STS 0x0028
+#define REG_SCC_APB_RF_SCC_ROSC_MODE 0x0100
+#define REG_SCC_APB_RF_SCC_ROSC_CFG 0x0104
+#define REG_SCC_APB_RF_SCC_ROSC_CTRL 0x0108
+#define REG_SCC_APB_RF_SCC_ROSC_RPT 0x010c
+#define REG_SCC_APB_RF_SCC_ROSC_SW_RST 0x0110
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CTRL0 0x0000
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CTRL1 0x0004
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_PLL_CLK_CTRL 0x0008
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_PERFOR 0x000c
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_CTRL2 0x0010
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_RESERVED 0x0014
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RPLL_BIST_CTRL 0x0018
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANA_BB_PWR_CTRL 0x001c
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANA_BB_26M_BUF 0x0020
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANA_BB_EN_CTRL 0x0024
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANALOG_TEST 0x0028
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_CTRL1 0x002c
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_AAPC_CTRL2 0x0030
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ANA_BB_RSVD 0x0034
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_RTC100M_CTRL 0x0038
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_TEST_CLK_CTRL 0x003c
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_BB_TOP_TEST_0 0x0040
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_BB_TOP_TEST_1 0x0044
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_ISPPLL_CTRL0 0x0048
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_REG_SEL_CFG_0 0x004c
+#define REG_ANLG_PHY_G3_RF_ANALOG_BB_TOP_REG_SEL_CFG_1 0x0050
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL0 0x0054
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL1 0x0058
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL2 0x005c
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL3 0x0060
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL4 0x0064
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL5 0x0068
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL6 0x006c
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL7 0x0070
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_MPLL0_CTRL8 0x0074
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX0 0x0078
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX1 0x007c
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX2 0x0080
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX3 0x0084
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX4 0x0088
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX5 0x008c
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX6 0x0090
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_ANANKE_BIG_DVFS_INDEX7 0x0094
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL0_REG_SEL_CFG_0 0x0098
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL0 0x009c
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL1 0x00a0
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL2 0x00a4
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL3 0x00a8
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL4 0x00ac
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL5 0x00b0
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL6 0x00b4
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_MPLL2_CTRL7 0x00b8
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX0 0x00bc
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX1 0x00c0
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX2 0x00c4
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX3 0x00c8
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX4 0x00cc
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX5 0x00d0
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX6 0x00d4
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_SCU_DVFS_INDEX7 0x00d8
+#define REG_ANLG_PHY_G3_RF_ANALOG_MPLL2_REG_SEL_CFG_0 0x00dc
+#define REG_PRE_DIV_CLK_GEN_SOFT_CNT_DONE0_CFG 0x0020
+#define REG_PRE_DIV_CLK_GEN_PLL_WAIT_SEL0_CFG 0x0024
+#define REG_PRE_DIV_CLK_GEN_PLL_WAIT_SW_CTL0_CFG 0x0028
+#define REG_PRE_DIV_CLK_GEN_DIV_EN_SEL0_CFG 0x002c
+#define REG_PRE_DIV_CLK_GEN_DIV_EN_SEL1_CFG 0x0030
+#define REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL0_CFG 0x0034
+#define REG_PRE_DIV_CLK_GEN_DIV_EN_SW_CTL1_CFG 0x0038
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL0_CFG 0x003c
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL1_CFG 0x0040
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL2_CFG 0x0044
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL3_CFG 0x0048
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SEL4_CFG 0x004c
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL0_CFG 0x0050
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL1_CFG 0x0054
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL2_CFG 0x0058
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL3_CFG 0x005c
+#define REG_PRE_DIV_CLK_GEN_GATE_EN_SW_CTL4_CFG 0x0060
+#define REG_PRE_DIV_CLK_GEN_OUTPUT_CLOCK_MUX_SEL0_CFG 0x0064
+#define REG_PRE_DIV_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG 0x0068
+#define REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS00_CFG 0x006c
+#define REG_PRE_DIV_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS10_CFG 0x0070
+#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS00_CFG 0x0074
+#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG 0x0078
+#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS20_CFG 0x007c
+#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS30_CFG 0x0080
+#define REG_PRE_DIV_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS40_CFG 0x0084
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_FIX_VOLTAGE_CTRL 0x0000
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_WAIT_WINDOW_CFG 0x0004
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY_CFG0 0x0008
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_UP_DELAY_CFG1 0x000c
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG0 0x0010
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG1 0x0014
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_CTRL 0x0018
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOLTAGE_JUDGE_BYPASS 0x001c
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_STATE_DBG 0x0020
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_FIX_VOLTAGE_CTRL 0x0024
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_WAIT_WINDOW_CFG 0x0028
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG0 0x002c
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG1 0x0030
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG0 0x0034
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG1 0x0038
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_CTRL 0x003c
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOLTAGE_JUDGE_BYPASS 0x0040
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_STATE_DBG 0x0044
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_FIX_VOLTAGE_CTRL 0x0048
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_WAIT_WINDOW_CFG 0x004c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG2 0x0050
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG1 0x0054
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG0 0x0058
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG2 0x005c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG1 0x0060
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG0 0x0064
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_CTRL 0x0068
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_JUDGE_BYPASS 0x006c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_STATE_DBG 0x0070
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_FIX_VOLTAGE_CTRL 0x0074
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_WAIT_WINDOW_CFG 0x0078
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG2 0x007c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG1 0x0080
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG0 0x0084
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG2 0x0088
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG1 0x008c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG0 0x0090
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_SW_DVFS_CTRL 0x0094
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_JUDGE_BYPASS 0x0098
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_STATE_DBG 0x009c
+#define REG_TOP_DVFS_APB_RF_DCDC_STEP_TUNE_CFG 0x00a0
+#define REG_TOP_DVFS_APB_RF_TOP_DVFS_CLK_CTRL 0x00a4
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_SW_DVFS_POLL 0x00a8
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_SW_DVFS_POLL 0x00ac
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_SW_DVFS_POLL 0x00b0
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOL_TUNE_UP_CFG 0x00b4
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_VOL_TUNE_DOWN_CFG 0x00b8
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOL_TUNE_UP_CFG 0x00bc
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_VOL_TUNE_DOWN_CFG 0x00c0
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOL_TUNE_UP_CFG0 0x00c4
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOL_TUNE_UP_CFG1 0x00c8
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOL_TUNE_DOWN_CFG0 0x00cc
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOL_TUNE_DOWN_CFG1 0x00d0
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOL_TUNE_UP_CFG0 0x00d4
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOL_TUNE_UP_CFG1 0x00d8
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOL_TUNE_DOWN_CFG0 0x00dc
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOL_TUNE_DOWN_CFG1 0x00e0
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_VOLTAGE_VALUE0 0x00e4
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_VOLTAGE_VALUE1 0x00e8
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_VOLTAGE_VALUE0 0x00ec
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_VOLTAGE_VALUE1 0x00f0
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_VOLTAGE_VALUE0 0x00f4
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_VOLTAGE_VALUE1 0x00f8
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_VOLTAGE_VALUE2 0x00fc
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_VOLTAGE_VALUE0 0x0100
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_VOLTAGE_VALUE1 0x0104
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_VOLTAGE_VALUE2 0x0108
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU_STEP_TUNE_VOL 0x010c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG3 0x0110
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG3 0x0114
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG3 0x0118
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG3 0x011c
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_TYPE_SEL_CFG 0x0120
+#define REG_TOP_DVFS_APB_RF_DIALOG_DCDC_CPU1_VOL_TUNE_UP_CFG 0x0124
+#define REG_TOP_DVFS_APB_RF_DIALOG_DCDC_CPU1_VOL_TUNE_DOWN_CFG 0x0128
+#define REG_TOP_DVFS_APB_RF_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE0 0x012c
+#define REG_TOP_DVFS_APB_RF_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE1 0x0130
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_SW_DVFS_CTRL_ADI 0x0134
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_SW_DVFS_CTRL_I2C 0x0138
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_STATE_DBG1 0x013c
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_STATE_DBG1 0x0140
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_STATE_DBG1 0x0144
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_STATE_DBG1 0x0148
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_STATE_DBG2 0x014c
+#define REG_TOP_DVFS_APB_RF_SUBSYS_SW_DVFS_EN_CFG 0x0150
+#define REG_TOP_DVFS_APB_RF_WTLCP_DVFS_URGENCY_CFG 0x0154
+#define REG_TOP_DVFS_APB_RF_DCDC_DVFS_CNT_CFG 0x0158
+#define REG_TOP_DVFS_APB_RF_DCDC_MM_DVFS_CNT 0x015c
+#define REG_TOP_DVFS_APB_RF_DCDC_MODEM_DVFS_CNT 0x0160
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU0_DVFS_CNT 0x0164
+#define REG_TOP_DVFS_APB_RF_DCDC_CPU1_DVFS_CNT 0x0168
+#define REG_TOP_DVFS_APB_RF_DVFS_IDLE_VOL_CFG 0x016c
+#define REG_TOP_DVFS_APB_RF_SHARE_DCDC_CFG 0x0170
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_FIX_VOLTAGE_CTRL 0x0174
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_WAIT_WINDOW_CFG 0x0178
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY_CFG0 0x017c
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_UP_DELAY_CFG1 0x0180
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG0 0x0184
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG1 0x0188
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_CTRL 0x018c
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOLTAGE_JUDGE_BYPASS 0x0190
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_STATE_DBG 0x0194
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_SW_DVFS_POLL 0x0198
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOL_TUNE_UP_CFG 0x019c
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_VOL_TUNE_DOWN_CFG 0x01a0
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_VOLTAGE_VALUE0 0x01a4
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_VOLTAGE_VALUE1 0x01a8
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_STATE_DBG1 0x01ac
+#define REG_TOP_DVFS_APB_RF_DCDC_TOP_DVFS_CNT 0x01b0
+#define REG_TOP_DVFS_APB_RF_TOP_DVFS_RESERVED_REG_CFG0 0x01c0
+#define REG_TOP_DVFS_APB_RF_TOP_DVFS_RESERVED_REG_CFG1 0x01c4
+#define REG_TOP_DVFS_APB_RF_TOP_DVFS_RESERVED_REG_CFG2 0x01c8
+#define REG_TOP_DVFS_APB_RF_TOP_DVFS_RESERVED_REG_CFG3 0x01cc
+#define REG_MM_AHB_RF_AHB_EB 0x0000
+#define REG_MM_AHB_RF_AHB_RST 0x0004
+#define REG_MM_AHB_RF_GEN_CLK_CFG 0x0008
+#define REG_MM_AHB_RF_MM_QOS 0x000c
+#define REG_MM_AHB_RF_MM_LP_DISABLE 0x0010
+#define REG_MM_AHB_RF_MM_LPC_CTRL_ISP 0x0014
+#define REG_MM_AHB_RF_MM_LPC_CTRL_JPG 0x0018
+#define REG_MM_AHB_RF_MM_LPC_CTRL_CPP 0x001c
+#define REG_MM_AHB_RF_MM_LPC_CTRL_MM_MAIN_MTX_S0 0x0020
+#define REG_MM_AHB_RF_MM_LPC_CTRL_AXI2AHB_M0 0x0024
+#define REG_MM_AHB_RF_MM_LPC_CTRL_DCAM_ASYNC_BDG 0x0028
+#define REG_MM_AHB_RF_MM_LPC_CTRL_MTX_ASYNC_BDG 0x002c
+#define REG_MM_AHB_RF_MIPI_CSI_SEL_CTRL 0x0030
+#define REG_MM_AHB_RF_MM_0P5_APPEND 0x0034
+#define REG_MM_AHB_RF_MM_IP_BUSY 0x0038
+#define REG_MM_AHB_RF_MM_AS_BDG_STATE 0x003c
+#define REG_MM_AHB_RF_MM_LPC_CTRL_FD 0x0040
+#define REG_MM_AHB_RF_MM_LPC_CTRL_SLICE_ISP 0x0044
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_HOLD_CTRL 0x0000
+#define REG_GPU_DVFS_APB_RF_GPU_MIN_VOLTAGE_CFG 0x0010
+#define REG_GPU_DVFS_APB_RF_GPU_SW_DVFS_CTRL 0x0020
+#define REG_GPU_DVFS_APB_RF_GPU_FREQ_UPDATE_BYPASS 0x0024
+#define REG_GPU_DVFS_APB_RF_CGM_GPU_DVFS_CLK_GATE_CTRL 0x0028
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_VOLTAGE_DBG 0x002c
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_CGM_CFG_DBG 0x0034
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_STATE_DBG 0x0038
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX0_MAP 0x0048
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX1_MAP 0x004c
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX2_MAP 0x0050
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX3_MAP 0x0054
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX4_MAP 0x0058
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX5_MAP 0x005c
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX6_MAP 0x0060
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_INDEX7_MAP 0x0064
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_INDEX_CFG 0x008c
+#define REG_GPU_DVFS_APB_RF_GPU_CORE_DVFS_INDEX_IDLE_CFG 0x0090
+#define REG_GPU_DVFS_APB_RF_GPU_FREQ_UPD_STATE 0x0098
+#define REG_GPU_DVFS_APB_RF_GPU_GFREE_WAIT_DELAY_CFG 0x009c
+#define REG_GPU_DVFS_APB_RF_GPU_FREQ_UPD_TYPE_CFG 0x00a4
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_RESERVED_REG_CFG0 0x00a8
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_RESERVED_REG_CFG1 0x00ac
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_RESERVED_REG_CFG2 0x00b0
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_RESERVED_REG_CFG3 0x00b4
+#define REG_GPU_DVFS_APB_RF_GPU_DVFS_WAIT_WINDOW_CFG2 0x00c0
+#define REG_GPU_DVFS_APB_RF_GPU_DFS_IDLE_DISABLE_CFG 0x00d0
+#define REG_AP_APB_RF_APB_EB 0x0000
+#define REG_AP_APB_RF_APB_RST 0x0004
+#define REG_AP_APB_RF_APB_MISC_CTRL 0x0008
+#define REG_PUB_QOSC_AHB_RF_QOS_CTRL_EB 0x0000
+#define REG_PUB_QOSC_AHB_RF_QOS_CTRL_RESET 0x0004
+#define REG_PUB_QOSC_AHB_RF_QOSC_CLK_CTRL 0x0008
+#define REG_PUB_QOSC_AHB_RF_QOSC_PORT_ENABLE 0x000c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNTER_EN 0x0010
+#define REG_PUB_QOSC_AHB_RF_QOSC_AXURGENT_EN 0x0014
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_EN 0x0018
+#define REG_PUB_QOSC_AHB_RF_QOSC_CFG 0x001c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x0020
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x0024
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH2 0x0028
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH3 0x002c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH4 0x0030
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH5 0x0034
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH6 0x0038
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_WR_CH7 0x003c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x0050
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x0054
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH2 0x0058
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH3 0x005c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH4 0x0060
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH5 0x0064
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH6 0x0068
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_THRESHOLD_HIGH_RD_CH7 0x006c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH0 0x0080
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH1 0x0084
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH2 0x0088
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH3 0x008c
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH4 0x0090
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH5 0x0094
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH6 0x0098
+#define REG_PUB_QOSC_AHB_RF_QOSC_SV_COUNT_OFFSET_CH7 0x009c
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW0 0x00b0
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_TIMING_WINDOW1 0x00b4
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH0 0x00c0
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH1 0x00c4
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH2 0x00c8
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH3 0x00cc
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH4 0x00d0
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH5 0x00d4
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH6 0x00d8
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH7 0x00dc
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH8 0x00e0
+#define REG_PUB_QOSC_AHB_RF_QOSC_BW_LIMITER_MAX_CH9 0x00e4
+#define REG_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_HIGH_EN 0x00f0
+#define REG_PUB_QOSC_AHB_RF_QOSC_FORCE_URGENT_ULTRA_EN 0x00f4
+#define REG_PUB_QOSC_AHB_RF_QOSC_LATMON_AXURGENT_EN 0x00f8
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH0 0x0100
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH1 0x0104
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH2 0x0108
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH3 0x010c
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH4 0x0110
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH5 0x0114
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH6 0x0118
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH7 0x011c
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH8 0x0120
+#define REG_PUB_QOSC_AHB_RF_QOSC_QOS_VALUE_CH9 0x0124
+#define REG_PUB_QOSC_AHB_RF_QOSC_STATUS0 0x0200
+#define REG_PUB_QOSC_AHB_RF_QOSC_STATUS1 0x0204
+#define REG_PUB_QOSC_AHB_RF_QOSC_STATUS2 0x0208
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH0 0x0210
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH1 0x0214
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH2 0x0218
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH3 0x021c
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH4 0x0220
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH5 0x0224
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH6 0x0228
+#define REG_PUB_QOSC_AHB_RF_QOSC_URGENT_COUNT_CH7 0x022c
+#define REG_PUB_QOSC_AHB_RF_QOSC_DBG_MON 0x0280
+#define REG_PUB_QOSC_AHB_RF_QOSC_MON_STATUS 0x0284
+#define REG_PUB_QOSC_AHB_RF_QOSC_MON_STATUS_1 0x0288
+#define REG_PUB_QOSC_AHB_RF_M1_QOS_CTRL_EB 0x0400
+#define REG_PUB_QOSC_AHB_RF_M1_QOS_CTRL_RESET 0x0404
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_CLK_CTRL 0x0408
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_PORT_ENABLE 0x040c
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNTER_EN 0x0410
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_AXURGENT_EN 0x0414
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_EN 0x0418
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_CFG 0x041c
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x0420
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x0424
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x0430
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x0434
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNT_OFFSET_CH0 0x0440
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_SV_COUNT_OFFSET_CH1 0x0444
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_BW_TIMING_WINDOW0 0x0450
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_CH0 0x0460
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_BW_LIMITER_MAX_CH1 0x0464
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_HIGH_EN 0x0470
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_FORCE_URGENT_ULTRA_EN 0x0474
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_LATMON_AXURGENT_EN 0x0478
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_CH0 0x0480
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_QOS_VALUE_CH1 0x0484
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_STATUS0 0x0500
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_STATUS1 0x0504
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_STATUS2 0x0508
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_URGENT_COUNT_CH0 0x0510
+#define REG_PUB_QOSC_AHB_RF_M1_QOSC_URGENT_COUNT_CH1 0x0514
+#define REG_PUB_QOSC_AHB_RF_M2_QOS_CTRL_EB 0x0600
+#define REG_PUB_QOSC_AHB_RF_M2_QOS_CTRL_RESET 0x0604
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_CLK_CTRL 0x0608
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_PORT_ENABLE 0x060c
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNTER_EN 0x0610
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_AXURGENT_EN 0x0614
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_EN 0x0618
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_CFG 0x061c
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x0620
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x0624
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x0630
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x0634
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNT_OFFSET_CH0 0x0640
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_SV_COUNT_OFFSET_CH1 0x0644
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_BW_TIMING_WINDOW0 0x0650
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_CH0 0x0660
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_BW_LIMITER_MAX_CH1 0x0664
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_HIGH_EN 0x0670
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_FORCE_URGENT_ULTRA_EN 0x0674
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_LATMON_AXURGENT_EN 0x0678
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_CH0 0x0680
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_QOS_VALUE_CH1 0x0684
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_STATUS0 0x0700
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_STATUS1 0x0704
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_STATUS2 0x0708
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_URGENT_COUNT_CH0 0x0710
+#define REG_PUB_QOSC_AHB_RF_M2_QOSC_URGENT_COUNT_CH1 0x0714
+#define REG_PUB_QOSC_AHB_RF_LATMON_EB 0x0800
+#define REG_PUB_QOSC_AHB_RF_LATMON_RESET 0x0804
+#define REG_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_LM0 0x0808
+#define REG_PUB_QOSC_AHB_RF_URGENT_RATIO_LM0 0x080c
+#define REG_PUB_QOSC_AHB_RF_LATMON_SUB_CFG_LM0 0x0810
+#define REG_PUB_QOSC_AHB_RF_LATMON_HW_DFS_CFG 0x0814
+#define REG_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_LM1 0x0820
+#define REG_PUB_QOSC_AHB_RF_URGENT_RATIO_LM1 0x0824
+#define REG_PUB_QOSC_AHB_RF_LATMON_SUB_CFG_LM1 0x0828
+#define REG_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_LM2 0x0830
+#define REG_PUB_QOSC_AHB_RF_URGENT_RATIO_LM2 0x0834
+#define REG_PUB_QOSC_AHB_RF_LATMON_SUB_CFG_LM2 0x0838
+#define REG_PUB_QOSC_AHB_RF_TAR_LAT_OFFSET_LM3 0x0840
+#define REG_PUB_QOSC_AHB_RF_URGENT_RATIO_LM3 0x0844
+#define REG_PUB_QOSC_AHB_RF_LATMON_SUB_CFG_LM3 0x0848
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM0_STATUS0 0x0900
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM0_STATUS1 0x0904
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM0_STATUS2 0x0908
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM0_STATUS3 0x090c
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM1_STATUS0 0x0910
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM1_STATUS1 0x0914
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM1_STATUS2 0x0918
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM1_STATUS3 0x091c
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM2_STATUS0 0x0920
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM2_STATUS1 0x0924
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM2_STATUS2 0x0928
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM2_STATUS3 0x092c
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM3_STATUS0 0x0930
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM3_STATUS1 0x0934
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM3_STATUS2 0x0938
+#define REG_PUB_QOSC_AHB_RF_LATMON_LM3_STATUS3 0x093c
+#define REG_PUB_QOSC_AHB_RF_LATMON_STATUS 0x0940
+#define REG_PUB_QOSC_AHB_RF_BWMON_EB 0x0a00
+#define REG_PUB_QOSC_AHB_RF_BWMON0_UP_WBW_SET 0x0a04
+#define REG_PUB_QOSC_AHB_RF_BWMON0_UP_RBW_SET 0x0a08
+#define REG_PUB_QOSC_AHB_RF_BWMON1_UP_WBW_SET 0x0a0c
+#define REG_PUB_QOSC_AHB_RF_BWMON1_UP_RBW_SET 0x0a10
+#define REG_PUB_QOSC_AHB_RF_BWMON2_UP_WBW_SET 0x0a14
+#define REG_PUB_QOSC_AHB_RF_BWMON2_UP_RBW_SET 0x0a18
+#define REG_PUB_QOSC_AHB_RF_BWMON_STATUS 0x0a70
+#define REG_PUB_QOSC_AHB_RF_BWMON0_WBW_CNT 0x0a80
+#define REG_PUB_QOSC_AHB_RF_BWMON0_RBW_CNT 0x0a84
+#define REG_PUB_QOSC_AHB_RF_BWMON1_WBW_CNT 0x0a88
+#define REG_PUB_QOSC_AHB_RF_BWMON1_RBW_CNT 0x0a8c
+#define REG_PUB_QOSC_AHB_RF_BWMON2_WBW_CNT 0x0a90
+#define REG_PUB_QOSC_AHB_RF_BWMON2_RBW_CNT 0x0a94
+#define REG_PUB_QOSC_AHB_RF_M3_QOS_CTRL_EB 0x0b00
+#define REG_PUB_QOSC_AHB_RF_M3_QOS_CTRL_RESET 0x0b04
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_CLK_CTRL 0x0b08
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_PORT_ENABLE 0x0b0c
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNTER_EN 0x0b10
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_AXURGENT_EN 0x0b14
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_EN 0x0b18
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_CFG 0x0b1c
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x0b20
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x0b24
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x0b30
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x0b34
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNT_OFFSET_CH0 0x0b40
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_SV_COUNT_OFFSET_CH1 0x0b44
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_BW_TIMING_WINDOW0 0x0b50
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_CH0 0x0b60
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_BW_LIMITER_MAX_CH1 0x0b64
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_HIGH_EN 0x0b70
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_FORCE_URGENT_ULTRA_EN 0x0b74
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_LATMON_AXURGENT_EN 0x0b78
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_CH0 0x0b80
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_QOS_VALUE_CH1 0x0b84
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_STATUS0 0x0c00
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_STATUS1 0x0c04
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_STATUS2 0x0c08
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_URGENT_COUNT_CH0 0x0c10
+#define REG_PUB_QOSC_AHB_RF_M3_QOSC_URGENT_COUNT_CH1 0x0c14
+#define REG_PUB_QOSC_AHB_RF_M4_QOS_CTRL_EB 0x0d00
+#define REG_PUB_QOSC_AHB_RF_M4_QOS_CTRL_RESET 0x0d04
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_CLK_CTRL 0x0d08
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_PORT_ENABLE 0x0d0c
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNTER_EN 0x0d10
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_AXURGENT_EN 0x0d14
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_EN 0x0d18
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_CFG 0x0d1c
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_WR_CH0 0x0d20
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_WR_CH1 0x0d24
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_RD_CH0 0x0d30
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_THRESHOLD_HIGH_RD_CH1 0x0d34
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNT_OFFSET_CH0 0x0d40
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_SV_COUNT_OFFSET_CH1 0x0d44
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_BW_TIMING_WINDOW0 0x0d50
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_CH0 0x0d60
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_BW_LIMITER_MAX_CH1 0x0d64
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_HIGH_EN 0x0d70
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_FORCE_URGENT_ULTRA_EN 0x0d74
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_LATMON_AXURGENT_EN 0x0d78
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_CH0 0x0d80
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_QOS_VALUE_CH1 0x0d84
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_STATUS0 0x0e00
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_STATUS1 0x0e04
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_STATUS2 0x0e08
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_URGENT_COUNT_CH0 0x0e10
+#define REG_PUB_QOSC_AHB_RF_M4_QOSC_URGENT_COUNT_CH1 0x0e14
+#define REG_GPU_APB_RF_APB_RST 0x0000
+#define REG_GPU_APB_RF_CLK_GPU_CORE 0x0004
+#define REG_GPU_APB_RF_CLK_GPU_MEM 0x0008
+#define REG_GPU_APB_RF_CLK_GPU_SYS 0x000c
+#define REG_GPU_APB_RF_GPU_NIC400_QOS 0x0010
+#define REG_GPU_APB_RF_LPC_AB_W 0x0014
+#define REG_GPU_APB_RF_LPC_M0 0x0018
+#define REG_GPU_APB_RF_LPC_S0 0x001c
+#define REG_GPU_APB_RF_LPC_S1 0x0020
+#define REG_GPU_APB_RF_ASYBC_BRIDGE_TOP_W 0x0024
+#define REG_GPU_APB_RF_GONDUL_Q_CHANNEL 0x0028
+#define REG_GPU_APB_RF_GONDUL_PDC_CONTROL_STACK0 0x002c
+#define REG_GPU_APB_RF_GONDUL_PDC_CONTROL_STACK1 0x0030
+#define REG_GPU_APB_RF_GONDUL_TEXFMTENABLE 0x0034
+#define REG_GPU_APB_RF_GONDUL_MISCS 0x0038
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_CLKLANE_STATE 0x0000
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE0 0x0004
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE1 0x0008
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_CTRL 0x000c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CTRL_CSI_2L 0x0010
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_MIPI_PHY_BIST_TEST 0x0014
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_SW_CTRL 0x0018
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_DUMY_CTRL 0x001c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_ISO_SW 0x0020
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_CSI_2L_SKEW_CTL 0x0024
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2LANE_REG_SEL_CFG_0 0x0028
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_M 0x002c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_M 0x0030
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_M 0x0034
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CTRL_CSI_2P2L 0x0038
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_S 0x003c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_S 0x0040
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_S 0x0044
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_RSVD 0x0048
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXCLKLANE_DB 0x004c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_0_DB 0x0050
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_1_DB 0x0054
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_2_DB 0x0058
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_3_DB 0x005c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATAESC_DB 0x0060
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_RX_DB 0x0064
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_1 0x0068
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_2 0x006c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DATALANE_CTRL_DB 0x0070
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ERR_DB 0x0074
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_DB 0x0078
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TEST_DB 0x007c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_SKEW 0x0080
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2L_ISO_SW 0x0084
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ATE_TEST 0x0088
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_REG_SEL_CFG_0 0x008c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_2P2LANE_REG_SEL_CFG_1 0x0090
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_CLKLANE_STATE 0x0094
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_STATE0 0x0098
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_STATE1 0x009c
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_CTRL 0x00a0
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CTRL_CSI_4L 0x00a4
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_SW_CTRL 0x00a8
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_ISO_SW 0x00ac
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_SKEW_CTL 0x00b0
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_BIST_TEST 0x00b4
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_DUMY_CTRL 0x00b8
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_CSI_4L_PHY_SEL 0x00bc
+#define REG_ANLG_PHY_G10_RF_ANALOG_MIPI_CSI_COMBO_REG_SEL_CFG_0 0x00c0
+#define REG_AON_CLK_CORE_CGM_AON_APB_CFG 0x0020
+#define REG_AON_CLK_CORE_CGM_ADI_CFG 0x0024
+#define REG_AON_CLK_CORE_CGM_AUX0_CFG 0x0028
+#define REG_AON_CLK_CORE_CGM_AUX1_CFG 0x002c
+#define REG_AON_CLK_CORE_CGM_AUX2_CFG 0x0030
+#define REG_AON_CLK_CORE_CGM_PROBE_CFG 0x0034
+#define REG_AON_CLK_CORE_CGM_PWM0_CFG 0x0038
+#define REG_AON_CLK_CORE_CGM_PWM1_CFG 0x003c
+#define REG_AON_CLK_CORE_CGM_PWM2_CFG 0x0040
+#define REG_AON_CLK_CORE_CGM_PWM3_CFG 0x0044
+#define REG_AON_CLK_CORE_CGM_EFUSE_CFG 0x0048
+#define REG_AON_CLK_CORE_CGM_UART0_CFG 0x004c
+#define REG_AON_CLK_CORE_CGM_UART1_CFG 0x0050
+#define REG_AON_CLK_CORE_CGM_32K_OUT_CFG 0x0054
+#define REG_AON_CLK_CORE_CGM_3K2_OUT_CFG 0x0058
+#define REG_AON_CLK_CORE_CGM_1K_OUT_CFG 0x005c
+#define REG_AON_CLK_CORE_CGM_THM0_CFG 0x0060
+#define REG_AON_CLK_CORE_CGM_THM1_CFG 0x0064
+#define REG_AON_CLK_CORE_CGM_THM2_CFG 0x0068
+#define REG_AON_CLK_CORE_CGM_THM3_CFG 0x006c
+#define REG_AON_CLK_CORE_CGM_CM4_I3C0_CFG 0x0070
+#define REG_AON_CLK_CORE_CGM_CM4_I3C1_CFG 0x0074
+#define REG_AON_CLK_CORE_CGM_CM4_SPI_CFG 0x0078
+#define REG_AON_CLK_CORE_CGM_AON_I2C_CFG 0x007c
+#define REG_AON_CLK_CORE_CGM_AON_IIS_CFG 0x0080
+#define REG_AON_CLK_CORE_CGM_SCC_CFG 0x0084
+#define REG_AON_CLK_CORE_CGM_APCPU_DAP_CFG 0x0088
+#define REG_AON_CLK_CORE_CGM_APCPU_DAP_MTCK_CFG 0x008c
+#define REG_AON_CLK_CORE_CGM_APCPU_TS_CFG 0x0090
+#define REG_AON_CLK_CORE_CGM_DEBUG_TS_CFG 0x0094
+#define REG_AON_CLK_CORE_CGM_DSI_TEST_S_CFG 0x0098
+#define REG_AON_CLK_CORE_CGM_RFTI_SBI_CFG 0x009c
+#define REG_AON_CLK_CORE_CGM_RFTI1_XO_CFG 0x00a0
+#define REG_AON_CLK_CORE_CGM_RFTI_LTH_CFG 0x00a4
+#define REG_AON_CLK_CORE_CGM_RFTI2_XO_CFG 0x00a8
+#define REG_AON_CLK_CORE_CGM_RCO100M_REF_CFG 0x00ac
+#define REG_AON_CLK_CORE_CGM_RCO100M_FDK_CFG 0x00b0
+#define REG_AON_CLK_CORE_CGM_DJTAG_TCK_CFG 0x00b4
+#define REG_AON_CLK_CORE_CGM_DJTAG_TCK_HW_CFG 0x00b8
+#define REG_AON_CLK_CORE_CGM_SP_AHB_CFG 0x00bc
+#define REG_AON_CLK_CORE_CGM_TMR_CFG 0x00c0
+#define REG_AON_CLK_CORE_CGM_DET_32K_CFG 0x00c4
+#define REG_AON_CLK_CORE_CGM_PMU_CFG 0x00c8
+#define REG_AON_CLK_CORE_CGM_DEBOUNCE_CFG 0x00cc
+#define REG_AON_CLK_CORE_CGM_APCPU_PMU_CFG 0x00d0
+#define REG_AON_CLK_CORE_CGM_FUNC_DMA_CFG 0x00d4
+#define REG_AON_CLK_CORE_CGM_TOP_DVFS_CFG 0x00d8
+#define REG_AON_CLK_CORE_CGM_OTG_UTMI_CFG 0x00dc
+#define REG_AON_CLK_CORE_CGM_OTG_REF_CFG 0x00e0
+#define REG_AON_CLK_CORE_CGM_CSSYS_CFG 0x00e4
+#define REG_AON_CLK_CORE_CGM_CSSYS_PUB_CFG 0x00e8
+#define REG_AON_CLK_CORE_CGM_CSSYS_APB_CFG 0x00ec
+#define REG_AON_CLK_CORE_CGM_AP_AXI_CFG 0x00f0
+#define REG_AON_CLK_CORE_CGM_AP_MM_CFG 0x00f4
+#define REG_AON_CLK_CORE_CGM_SDIO2_2X_CFG 0x00f8
+#define REG_AON_CLK_CORE_CGM_SDIO2_1X_CFG 0x00fc
+#define REG_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG 0x0100
+#define REG_AON_CLK_CORE_CGM_DMC_REF_CFG 0x0104
+#define REG_AON_CLK_CORE_CGM_USB20_SCAN_ONLY_CFG 0x0108
+#define REG_AON_CLK_CORE_CGM_EMC_CFG 0x010c
+#define REG_AON_CLK_CORE_CGM_USB_CFG 0x0110
+#define REG_AON_CLK_CORE_CGM_AAPC_TEST_CFG 0x0114
+#define REG_AON_CLK_CORE_CGM_26M_PMU_CFG 0x0118
+#define REG_AON_CLK_CORE_CGM_CPHY_CFG_CFG 0x011c
+#define REG_AON_CLK_CORE_CGM_CSI_PHY_SCAN_ONLY_CFG 0x0120
+#define REG_AON_CLK_CORE_CGM_WCDMA_SLICE_SCAN_ONLY_CFG 0x0124
+#define REG_AON_CLK_CORE_CGM_26M_ETC_CFG 0x0128
+#define REG_AUD_CP_AHB_RF_MODULE_EB0_STS 0x0000
+#define REG_AUD_CP_AHB_RF_MODULE_EB1_STS 0x0004
+#define REG_AUD_CP_AHB_RF_MODULE_RST0_STS 0x0008
+#define REG_AUD_CP_AHB_RF_BUS_CTRL 0x000c
+#define REG_AUD_CP_AHB_RF_ACC_AUTO 0x0010
+#define REG_AUD_CP_AHB_RF_M_S_PUB_FRC_LSLP 0x0014
+#define REG_AUD_CP_AHB_RF_AHB_ARCH_EB 0x0018
+#define REG_AUD_CP_AHB_RF_CORE_SLEEP 0x001c
+#define REG_AUD_CP_AHB_RF_SYS_SLP_EN 0x0020
+#define REG_AUD_CP_AHB_RF_MCACHE_CTRL 0x0024
+#define REG_AUD_CP_AHB_RF_MCU_STATUS 0x0028
+#define REG_AUD_CP_AHB_RF_ID2QOS_AR_0 0x002c
+#define REG_AUD_CP_AHB_RF_ID2QOS_AR_1 0x0030
+#define REG_AUD_CP_AHB_RF_ID2QOS_AW_0 0x0034
+#define REG_AUD_CP_AHB_RF_ID2QOS_AW_1 0x0038
+#define REG_AUD_CP_AHB_RF_EXT_ACC_AUD_SEL 0x003c
+#define REG_AUD_CP_AHB_RF_AUD_RESERVED 0x0040
+#define REG_AUD_CP_AHB_RF_LP_EB_AUDCP 0x0044
+#define REG_AUD_CP_AHB_RF_ACTIVE_SYNC_SEL_AUDCP 0x0048
+#define REG_AUD_CP_AHB_RF_AXILP_NUM 0x004c
+#define REG_AUD_CP_AHB_RF_AWQOS 0x0050
+#define REG_AUD_CP_AHB_RF_ARQOS 0x0054
+#define REG_AUD_CP_AHB_RF_M_S_PUB_CTL_PERI 0x0058
+#define REG_AUD_CP_AHB_RF_M_S_FRC_DOZE 0x005c
+#define REG_AUD_CP_AHB_RF_M_S_PUB_FRC_DSLP 0x0060
+#define REG_AUD_CP_AHB_RF_AUD_BRIDGE_DEBUG_SIG 0x0064
+#define REG_AUD_CP_AHB_RF_AUD_PROT_SEL 0x0068
+#define REG_AUD_CP_AHB_RF_AUD_BRIDGE_STATE 0x006c
+#define REG_AUD_CP_AHB_RF_AUD_BRIDGE_CTL 0x0070
+#define REG_AUD_CP_AHB_RF_M_AXCACHE_CTL 0x0074
+#define REG_AUD_CP_AHB_RF_DSP_DMA_INT_CLEAR 0x0078
+#define REG_AUD_CP_AHB_RF_DSP_PSU_STA 0x007c
+#define REG_AUD_CP_AHB_RF_FORCE_DMA_BUSY 0x0080
+#define REG_AUD_CP_AHB_RF_WAKEUP_EN_INT_H 0x0084
+#define REG_AUD_CP_AHB_RF_WAKEUP_EN_INT_L 0x0088
+#define REG_AUD_CP_AHB_RF_DSP_L2CC_CTRL 0x008c
+#define REG_AUD_CP_AHB_RF_MTX_QOS_THD 0x0090
+#define REG_AUD_CP_AHB_RF_FREQ_FRC_ON_CTRL 0x0094
+#define REG_AUD_CP_AHB_RF_FREQ_FRC_OFF_CTRL 0x0098
+#define REG_AUD_CP_AHB_RF_DBG_DUMMG_REG 0x009c
+#define REG_AUD_CP_AHB_RF_DVFS_CTRL 0x00a0
+#define REG_AUD_CP_AHB_RF_CGM_AUTO_EN 0x00a4
+#define REG_AUD_CP_AHB_RF_BUS_CLK_CTRL 0x00a8
+#define REG_AUD_CP_AHB_RF_LPC_SYNC_SEL 0x00ac
+#define REG_AUD_CP_AHB_RF_BUS_MON_CTRL 0x00b0
+#define REG_AUD_CP_AHB_RF_SYS_DBG_BUS 0x00b4
+#define REG_AUD_CP_AHB_RF_LPC_PU_NUM0 0x00b8
+#define REG_AUD_CP_AHB_RF_LPC_PU_NUM1 0x00bc
+#define REG_AUD_CP_AHB_RF_LPC_PU_NUM2 0x00c0
+#define REG_AUD_CP_AHB_RF_LPC_PU_NUM3 0x00c4
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_HOLD_CTRL 0x0000
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_WAIT_WINDOW_CFG 0x0004
+#define REG_MM_DVFS_AHB_RF_MM_DFS_EN_CTRL 0x0008
+#define REG_MM_DVFS_AHB_RF_MM_DFS_SW_TRIG_CFG 0x000c
+#define REG_MM_DVFS_AHB_RF_MM_MIN_VOLTAGE_CFG 0x0010
+#define REG_MM_DVFS_AHB_RF_MM_SW_DVFS_CTRL 0x002c
+#define REG_MM_DVFS_AHB_RF_MM_FREQ_UPDATE_BYPASS 0x0030
+#define REG_MM_DVFS_AHB_RF_CGM_MM_DVFS_CLK_GATE_CTRL 0x0034
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_VOLTAGE_DBG 0x0038
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_CGM_CFG_DBG 0x0048
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_STATE_DBG 0x004c
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX0_MAP 0x0050
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX1_MAP 0x0054
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX2_MAP 0x0058
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX3_MAP 0x005c
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX4_MAP 0x0060
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX5_MAP 0x0064
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX6_MAP 0x0068
+#define REG_MM_DVFS_AHB_RF_ISP_INDEX7_MAP 0x006c
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX0_MAP 0x0070
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX1_MAP 0x0074
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX2_MAP 0x0078
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX3_MAP 0x007c
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX4_MAP 0x0080
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX5_MAP 0x0084
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX6_MAP 0x0088
+#define REG_MM_DVFS_AHB_RF_JPG_INDEX7_MAP 0x008c
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX0_MAP 0x0090
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX1_MAP 0x0094
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX2_MAP 0x0098
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX3_MAP 0x009c
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX4_MAP 0x0100
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX5_MAP 0x0104
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX6_MAP 0x0108
+#define REG_MM_DVFS_AHB_RF_CPP_INDEX7_MAP 0x010c
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX0_MAP 0x0110
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX1_MAP 0x0114
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX2_MAP 0x0118
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX3_MAP 0x011c
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX4_MAP 0x0120
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX5_MAP 0x0124
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX6_MAP 0x0128
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_INDEX7_MAP 0x012c
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX0_MAP 0x0130
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX1_MAP 0x0134
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX2_MAP 0x0138
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX3_MAP 0x013c
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX4_MAP 0x0140
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX5_MAP 0x0144
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX6_MAP 0x0148
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_INDEX7_MAP 0x014c
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX0_MAP 0x0150
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX1_MAP 0x0154
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX2_MAP 0x0158
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX3_MAP 0x015c
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX4_MAP 0x0160
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX5_MAP 0x0164
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX6_MAP 0x0168
+#define REG_MM_DVFS_AHB_RF_MM_MTX_INDEX7_MAP 0x016c
+#define REG_MM_DVFS_AHB_RF_FD_INDEX0_MAP 0x0170
+#define REG_MM_DVFS_AHB_RF_FD_INDEX1_MAP 0x0174
+#define REG_MM_DVFS_AHB_RF_FD_INDEX2_MAP 0x0178
+#define REG_MM_DVFS_AHB_RF_FD_INDEX3_MAP 0x017c
+#define REG_MM_DVFS_AHB_RF_FD_INDEX4_MAP 0x0180
+#define REG_MM_DVFS_AHB_RF_FD_INDEX5_MAP 0x0184
+#define REG_MM_DVFS_AHB_RF_FD_INDEX6_MAP 0x0188
+#define REG_MM_DVFS_AHB_RF_FD_INDEX7_MAP 0x018c
+#define REG_MM_DVFS_AHB_RF_ISP_DVFS_INDEX_CFG 0x01c0
+#define REG_MM_DVFS_AHB_RF_ISP_DVFS_INDEX_IDLE_CFG 0x01c4
+#define REG_MM_DVFS_AHB_RF_JPG_DVFS_INDEX_CFG 0x01c8
+#define REG_MM_DVFS_AHB_RF_JPG_DVFS_INDEX_IDLE_CFG 0x01cc
+#define REG_MM_DVFS_AHB_RF_CPP_DVFS_INDEX_CFG 0x01d0
+#define REG_MM_DVFS_AHB_RF_CPP_DVFS_INDEX_IDLE_CFG 0x01d4
+#define REG_MM_DVFS_AHB_RF_MM_MTX_DVFS_INDEX_CFG 0x01d8
+#define REG_MM_DVFS_AHB_RF_MM_MTX_DVFS_INDEX_IDLE_CFG 0x01dc
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_DVFS_INDEX_CFG 0x01e0
+#define REG_MM_DVFS_AHB_RF_DCAM_IF_DVFS_INDEX_IDLE_CFG 0x01e4
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_DVFS_INDEX_CFG 0x01e8
+#define REG_MM_DVFS_AHB_RF_DCAM_AXI_DVFS_INDEX_IDLE_CFG 0x01ec
+#define REG_MM_DVFS_AHB_RF_FD_DVFS_INDEX_CFG 0x01f0
+#define REG_MM_DVFS_AHB_RF_FD_DVFS_INDEX_IDLE_CFG 0x01f4
+#define REG_MM_DVFS_AHB_RF_FREQ_UPD_STATE 0x0210
+#define REG_MM_DVFS_AHB_RF_MM_GFREE_WAIT_DELAY_CFG0 0x0214
+#define REG_MM_DVFS_AHB_RF_MM_GFREE_WAIT_DELAY_CFG1 0x0218
+#define REG_MM_DVFS_AHB_RF_MM_GFREE_WAIT_DELAY_CFG2 0x021c
+#define REG_MM_DVFS_AHB_RF_MM_FREQ_UPD_TYPE_CFG 0x0220
+#define REG_MM_DVFS_AHB_RF_MM_DFS_IDLE_DISABLE_CFG 0x0224
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_RESERVED_REG_CFG0 0x0230
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_RESERVED_REG_CFG1 0x0234
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_RESERVED_REG_CFG2 0x0238
+#define REG_MM_DVFS_AHB_RF_MM_DVFS_RESERVED_REG_CFG3 0x023c
+#define REG_AON_APB_APB_EB1 0x0004
+#define REG_AON_APB_APB_RST1 0x0010
+#define REG_AON_APB_CGM_REG1 0x0138
+#define REG_AON_APB_OTG_PHY_CTRL 0x0208
+#define REG_AON_APB_OTG_PHY_TEST 0x0204
+#define REG_AON_APB_RF_APB_EB0 0x0000
+#define REG_AON_APB_RF_APB_EB1 0x0004
+#define REG_AON_APB_RF_APB_EB2 0x0008
+#define REG_AON_APB_RF_APB_RST0 0x000c
+#define REG_AON_APB_RF_APB_RST1 0x0010
+#define REG_AON_APB_RF_APB_RST2 0x0014
+#define REG_AON_APB_RF_APB_RTC_EB0 0x0018
+#define REG_AON_APB_RF_PWR_CTRL 0x0024
+#define REG_AON_APB_RF_TS_CFG 0x0028
+#define REG_AON_APB_RF_BOOT_MODE 0x002c
+#define REG_AON_APB_RF_BB_BG_CTRL 0x0030
+#define REG_AON_APB_RF_CP_ARM_JTAG_CTRL 0x0034
+#define REG_AON_APB_RF_DCXO_LC_REG0 0x003c
+#define REG_AON_APB_RF_DCXO_LC_REG1 0x0040
+#define REG_AON_APB_RF_AUDCP_BOOT_PROT 0x0078
+#define REG_AON_APB_RF_AON_REG_PROT 0x007c
+#define REG_AON_APB_RF_AON_APB_CLK_SEL 0x0080
+#define REG_AON_APB_RF_DAP_DJTAG_SEL 0x0084
+#define REG_AON_APB_RF_USER_RSV_FLAG1 0x0088
+#define REG_AON_APB_RF_CM4_SYS_SOFT_RST 0x008c
+#define REG_AON_APB_RF_MDAR_SYS_HSDL_CFG 0x00c0
+#define REG_AON_APB_RF_AUTO_GATE_CTRL0 0x00d0
+#define REG_AON_APB_RF_AUTO_GATE_CTRL1 0x00d4
+#define REG_AON_APB_RF_AP_AXI_CTRL 0x00d8
+#define REG_AON_APB_RF_AON_CHIP_ID0 0x00e0
+#define REG_AON_APB_RF_AON_CHIP_ID1 0x00e4
+#define REG_AON_APB_RF_AON_PLAT_ID0 0x00e8
+#define REG_AON_APB_RF_AON_PLAT_ID1 0x00ec
+#define REG_AON_APB_RF_AON_IMPL_ID 0x00f0
+#define REG_AON_APB_RF_AON_MFT_ID 0x00f4
+#define REG_AON_APB_RF_AON_VER_ID 0x00f8
+#define REG_AON_APB_RF_AON_CHIP_ID 0x00fc
+#define REG_AON_APB_RF_CCIR_RCVR_CFG 0x0100
+#define REG_AON_APB_RF_PLL_BG_CFG 0x0108
+#define REG_AON_APB_RF_LVDSDIS_SEL 0x010c
+#define REG_AON_APB_RF_AUTO_GATE_CTRL2 0x0114
+#define REG_AON_APB_RF_AUTO_GATE_CTRL3 0x0118
+#define REG_AON_APB_RF_APCPU_CLK_CTRL0 0x011c
+#define REG_AON_APB_RF_SP_CFG_BUS 0x0124
+#define REG_AON_APB_RF_ETC_CTRL0 0x0128
+#define REG_AON_APB_RF_ETC_CTRL1 0x012c
+#define REG_AON_APB_RF_APB_RST3 0x0130
+#define REG_AON_APB_RF_RC100M_CFG 0x0134
+#define REG_AON_APB_RF_CGM_REG1 0x0138
+#define REG_AON_APB_RF_CGM_CLK_TOP_REG1 0x013c
+#define REG_AON_APB_RF_AUDCP_DSP_CTRL0 0x0140
+#define REG_AON_APB_RF_AUDCP_DSP_CTRL1 0x0144
+#define REG_AON_APB_RF_AUDCP_CTRL 0x014c
+#define REG_AON_APB_RF_WTLCP_LDSP_CTRL0 0x0150
+#define REG_AON_APB_RF_WTLCP_LDSP_CTRL1 0x0154
+#define REG_AON_APB_RF_WTLCP_TDSP_CTRL0 0x0158
+#define REG_AON_APB_RF_WTLCP_TDSP_CTRL1 0x015c
+#define REG_AON_APB_RF_WTLCP_CTRL 0x0164
+#define REG_AON_APB_RF_WTL_WCDMA_EB 0x0168
+#define REG_AON_APB_RF_PCP_AON_EB 0x0170
+#define REG_AON_APB_RF_PCP_SOFT_RST 0x0174
+#define REG_AON_APB_RF_PUBCP_CTRL 0x0178
+#define REG_AON_APB_RF_WTLCP_LPC_CTRL 0x0180
+#define REG_AON_APB_RF_PUBCP_LPC_CTRL 0x0184
+#define REG_AON_APB_RF_AON_SOC_USB_CTRL 0x0190
+#define REG_AON_APB_RF_SOFT_RST_AON_ADD1 0x01a0
+#define REG_AON_APB_RF_VDSP_INT_CTRL 0x01a4
+#define REG_AON_APB_RF_EB_AON_ADD1 0x01b0
+#define REG_AON_APB_RF_DBG_DJTAG_CTRL 0x01c0
+#define REG_AON_APB_RF_MBIST_EFUSE_CTRL 0x01fc
+#define REG_AON_APB_RF_OTG_PHY_TUNE 0x0200
+#define REG_AON_APB_RF_OTG_PHY_TEST 0x0204
+#define REG_AON_APB_RF_OTG_PHY_CTRL 0x0208
+#define REG_AON_APB_RF_OTG_CTRL0 0x020c
+#define REG_AON_APB_RF_OTG_CTRL1 0x0210
+#define REG_AON_APB_RF_USB_CLK_REF_SEL 0x0214
+#define REG_AON_APB_RF_LVDSRF_CTRL 0x0218
+#define REG_AON_APB_RF_THM0_CTRL 0x021c
+#define REG_AON_APB_RF_THM1_CTRL 0x0220
+#define REG_AON_APB_RF_THM2_CTRL 0x0224
+#define REG_AON_APB_RF_OVERHEAT_CTRL 0x022c
+#define REG_AON_APB_RF_PUBCP_SIM1_TOP_CTRL 0x0230
+#define REG_AON_APB_RF_PUBCP_SIM2_TOP_CTRL 0x0234
+#define REG_AON_APB_RF_PUBCP_SIM3_TOP_CTRL 0x0238
+#define REG_AON_APB_RF_AP_SIM_TOP_CTRL 0x023c
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL1 0x0250
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL2 0x0254
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL3 0x0258
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL4 0x025c
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL5 0x0260
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL6 0x0264
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL7 0x0268
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL8 0x026c
+#define REG_AON_APB_RF_TOP_PU_NUM_CTRL9 0x0270
+#define REG_AON_APB_RF_APCPU_MONITOR_STATUS 0x0280
+#define REG_AON_APB_RF_APCPU_DEBUG_PWR_LP_CTRL 0x0284
+#define REG_AON_APB_RF_APCPU_GIC_COL_LP_CTRL 0x0288
+#define REG_AON_APB_RF_APCPU_CLUSTER_ATB_LPC_CTRL 0x028c
+#define REG_AON_APB_RF_APCPU_CLUSTER_APB_LPC_CTRL 0x0290
+#define REG_AON_APB_RF_APCPU_CLUSTER_GIC_LPC_CTRL 0x0294
+#define REG_AON_APB_RF_APCPU_GIC600_GIC_LPC_CTRL 0x0298
+#define REG_AON_APB_RF_APCPU_DBG_BLK_LPC_CTRL 0x029c
+#define REG_AON_APB_RF_APCPU_TOP_MTX_M0_LPC_CTRL 0x0300
+#define REG_AON_APB_RF_APCPU_PU_NUM_CTRL 0x0304
+#define REG_AON_APB_RF_APCPU_CLUSTER_SCU_LPC_CTRL 0x0320
+#define REG_AON_APB_RF_APCPU_DDR_AB_LPC_CTRL 0x0324
+#define REG_AON_APB_RF_APCPU_QOS_CTRL 0x0328
+#define REG_AON_APB_RF_MPLL0_CTRL 0x032c
+#define REG_AON_APB_RF_MPLL1_CTRL 0x0330
+#define REG_AON_APB_RF_MPLL2_CTRL 0x0334
+#define REG_AON_APB_RF_DPLL_CTRL 0x0340
+#define REG_AON_APB_RF_PUB_CLK_GATING_CTRL 0x0344
+#define REG_AON_APB_RF_DDRPHY_VREP 0x0348
+#define REG_AON_APB_RF_VDSP2DDR_SLI_LPC_CTRL 0x034c
+#define REG_AON_APB_RF_PUBCP2WTL_ASYNC_BRIDGE_LPC_CTRL 0x037c
+#define REG_AON_APB_RF_CM42AON_LPC_CTRL 0x0380
+#define REG_AON_APB_RF_AON_MTX_MAIN_LPC_CTRL 0x0384
+#define REG_AON_APB_RF_AON_MTX_M0_LPC_CTRL 0x0388
+#define REG_AON_APB_RF_AON_MTX_M1_LPC_CTRL 0x038c
+#define REG_AON_APB_RF_AON_MTX_M2_LPC_CTRL 0x0390
+#define REG_AON_APB_RF_AON_MTX_M3_LPC_CTRL 0x0394
+#define REG_AON_APB_RF_AON_MTX_M4_LPC_CTRL 0x0398
+#define REG_AON_APB_RF_AON_MTX_M5_LPC_CTRL 0x039c
+#define REG_AON_APB_RF_AON_MTX_M6_LPC_CTRL 0x03a0
+#define REG_AON_APB_RF_AON_MTX_S0_LPC_CTRL 0x03a4
+#define REG_AON_APB_RF_AON_MTX_S1_LPC_CTRL 0x03a8
+#define REG_AON_APB_RF_AON_MTX_S2_LPC_CTRL 0x03ac
+#define REG_AON_APB_RF_AON_MTX_S3_LPC_CTRL 0x03b0
+#define REG_AON_APB_RF_AON_MTX_S4_LPC_CTRL 0x03b4
+#define REG_AON_APB_RF_AON_MTX_S5_LPC_CTRL 0x03b8
+#define REG_AON_APB_RF_AON_MTX_S6_LPC_CTRL 0x03bc
+#define REG_AON_APB_RF_AON_MTX_S7_LPC_CTRL 0x03c0
+#define REG_AON_APB_RF_AON_MTX_S8_LPC_CTRL 0x03c4
+#define REG_AON_APB_RF_AON_MTX_S9_LPC_CTRL 0x03c8
+#define REG_AON_APB_RF_AP2GPU_SLI_LPC_CTRL 0x03cc
+#define REG_AON_APB_RF_AP2MM_SLI_LPC_CTRL 0x03d0
+#define REG_AON_APB_RF_WTLCP2DDR_SLI_LPC_CTRL 0x03d4
+#define REG_AON_APB_RF_APCPU2AP_SLI_LPC_CTRL 0x03d8
+#define REG_AON_APB_RF_AUDCP2DDR_SLI_LPC_CTRL 0x03dc
+#define REG_AON_APB_RF_APCPU2DDR_SLI_LPC_CTRL 0x03e0
+#define REG_AON_APB_RF_AON2DDR_BRG_LPC_CTRL 0x03e4
+#define REG_AON_APB_RF_PUBCP2WTLCP_SLI_LPC_CTRL 0x03e8
+#define REG_AON_APB_RF_DCAM2DDR_SLI_LPC_CTRL 0x03ec
+#define REG_AON_APB_RF_DPU2DDR_SLI_LPC_CTRL 0x03f0
+#define REG_AON_APB_RF_GPU2DDR_SLI_LPC_CTRL 0x03f4
+#define REG_AON_APB_RF_ISP2DDR_SLI_LPC_CTRL 0x03f8
+#define REG_AON_APB_RF_AP2DDR_SLI_LPC_CTRL 0x03fc
+#define REG_AON_APB_RF_AON_APB_FREQ_CTRL 0x0400
+#define REG_AON_APB_RF_C2G_ANALOG_BB_TOP_CLK26MHZ_AUD_EN 0x0404
+#define REG_AON_APB_RF_MIPI_CSI_POWER_CTRL 0x0408
+#define REG_AON_APB_RF_SINDRV_POWER_CTRL 0x040c
+#define REG_AON_APB_RF_AP_EMMC_PHY_CTRL 0x0440
+#define REG_AON_APB_RF_AP_SDIO0_PHY_CTRL 0x0444
+#define REG_AON_APB_RF_AP_SDIO1_PHY_CTRL 0x0448
+#define REG_AON_APB_RF_AP_SDIO2_PHY_CTRL 0x044c
+#define REG_AON_APB_RF_PUBCP_SDIO0_PHY_CTRL 0x0450
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL0 0x0500
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL1 0x0504
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL2 0x0508
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL3 0x050c
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL4 0x0510
+#define REG_AON_APB_RF_APCPU_INT_ENABLE_CTRL5 0x0514
+#define REG_AON_APB_RF_WDG_RST_FLAG 0x0824
+#define REG_AON_APB_RF_BOND_OPT0 0x083c
+#define REG_AON_APB_RF_DEVICE_LIFE_CYCLE 0x0840
+#define REG_AON_APB_RF_RES_REG0 0x0844
+#define REG_AON_APB_RF_RES_REG1 0x0848
+#define REG_AON_APB_RF_RES_REG2 0x084c
+#define REG_AON_APB_RF_RES_REG3 0x0850
+#define REG_AON_APB_RF_RES_REG4 0x0854
+#define REG_AON_APB_RF_AON_MTX_PROT_CFG 0x0858
+#define REG_AON_APB_RF_PLL_LOCK_OUT_SEL 0x0864
+#define REG_AON_APB_RF_CPU2DDR_BRIDGE_DEBUG_SIGNAL_R 0x0870
+#define REG_AON_APB_RF_AON2DDR_BRIDGE_DEBUG_SIGNAL_W 0x0874
+#define REG_AON_APB_RF_AON2DDR_BRIDGE_DEBUG_SIGNAL_LIST 0x0878
+#define REG_AON_APB_RF_AUD2DDR_BRIDGE_DEBUG_SIGNAL_R 0x087c
+#define REG_AON_APB_RF_WTL2DDR_BRIDGE_DEBUG_SIGNAL_R 0x0880
+#define REG_AON_APB_RF_PUBCP2WTL_BRIDGE_DEBUG_SIGNAL_R 0x0884
+#define REG_AON_APB_RF_LEAKAGE_MAGIC_WORD 0x0900
+#define REG_AON_APB_RF_LEAKAGE_SWITCH 0x0904
+#define REG_AON_APB_RF_FUNC_TEST_BOOT_ADDR 0x0910
+#define REG_AON_APB_RF_CGM_RESCUE 0x0914
+#define REG_AON_APB_RF_AON_SDIO 0x092c
+#define REG_AON_APB_RF_SP_WAKEUP_MASK_EN0 0x0984
+#define REG_AON_APB_RF_SP_WAKEUP_MASK_EN1 0x0988
+#define REG_AON_APB_RF_SP_WAKEUP_MASK_EN2 0x098c
+#define REG_AON_APB_RF_DBG_BUS_DATA_WTLCP 0x0990
+#define REG_AON_APB_RF_DBG_BUS_DATA_PUBCP 0x0994
+#define REG_AON_APB_RF_DBG_BUS_DATA_AUDCP 0x0998
+#define REG_AON_APB_RF_SCC_DBG_BUS 0x0a00
+#define REG_AON_APB_RF_AON_FUNC_CTRL_0 0x0a04
+#define REG_AON_APB_RF_AON_FUNC_CTRL_1 0x0a08
+#define REG_PMU_APB_RF_PD_APCPU_TOP_CFG 0x0000
+#define REG_PMU_APB_RF_PD_APCPU_C0_CFG 0x0004
+#define REG_PMU_APB_RF_PD_APCPU_C1_CFG 0x0008
+#define REG_PMU_APB_RF_PD_APCPU_C2_CFG 0x000c
+#define REG_PMU_APB_RF_PD_APCPU_TOP_CFG2 0x0014
+#define REG_PMU_APB_RF_PD_AP_VSP_CFG 0x0018
+#define REG_PMU_APB_RF_PD_AP_SYS_CFG 0x001c
+#define REG_PMU_APB_RF_PD_MM_TOP_CFG 0x0024
+#define REG_PMU_APB_RF_PD_GPU_RGX_DUST_CFG0 0x0028
+#define REG_PMU_APB_RF_PD_GPU_RGX_DUST_CFG1 0x002c
+#define REG_PMU_APB_RF_PD_GPU_TOP_CFG0 0x0030
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_CE_CFG 0x0034
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_CFG 0x0038
+#define REG_PMU_APB_RF_PD_WTLCP_LDSP_CFG 0x003c
+#define REG_PMU_APB_RF_PD_WTLCP_TGDSP_CFG 0x0040
+#define REG_PMU_APB_RF_PD_WTLCP_HU3GE_A_CFG 0x0044
+#define REG_PMU_APB_RF_PD_WTLCP_HU3GE_B_CFG 0x0048
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_PROC_CFG 0x004c
+#define REG_PMU_APB_RF_PD_WTLCP_TD_PROC_CFG 0x0050
+#define REG_PMU_APB_RF_PD_WTLCP_SYS_CFG 0x0054
+#define REG_PMU_APB_RF_PD_PUBCP_SYS_CFG 0x0058
+#define REG_PMU_APB_RF_PD_AUDCP_AUDDSP_CFG 0x005c
+#define REG_PMU_APB_RF_PD_AUDCP_SYS_CFG 0x0060
+#define REG_PMU_APB_RF_PUBCP_FRC_STOP_REQ_FOR_WTL 0x0064
+#define REG_PMU_APB_RF_PD_CDMA_SYS_CFG 0x0068
+#define REG_PMU_APB_RF_PD_PUB_SYS_CFG 0x006c
+#define REG_PMU_APB_RF_AP_WAKEUP_POR_CFG 0x0070
+#define REG_PMU_APB_RF_XTL_WAIT_CNT 0x0074
+#define REG_PMU_APB_RF_PLL_WAIT_CNT0 0x0078
+#define REG_PMU_APB_RF_PLL_WAIT_CNT1 0x007c
+#define REG_PMU_APB_RF_PLL_WAIT_CNT2 0x0080
+#define REG_PMU_APB_RF_XTL0_REL_CFG 0x0084
+#define REG_PMU_APB_RF_XTL1_REL_CFG 0x0088
+#define REG_PMU_APB_RF_ISPPLL_REL_CFG 0x008c
+#define REG_PMU_APB_RF_XTLBUF0_REL_CFG 0x0090
+#define REG_PMU_APB_RF_XTLBUF1_REL_CFG 0x0094
+#define REG_PMU_APB_RF_DPLL0_REL_CFG 0x0098
+#define REG_PMU_APB_RF_DPLL1_REL_CFG 0x009c
+#define REG_PMU_APB_RF_LTEPLL_REL_CFG 0x00a0
+#define REG_PMU_APB_RF_TWPLL_REL_CFG 0x00a4
+#define REG_PMU_APB_RF_GPLL_REL_CFG 0x00a8
+#define REG_PMU_APB_RF_RPLL_REL_CFG 0x00ac
+#define REG_PMU_APB_RF_CP_SOFT_RST 0x00b0
+#define REG_PMU_APB_RF_CP_SLP_STATUS_DBG0 0x00b4
+#define REG_PMU_APB_RF_PWR_STATUS4_DBG 0x00b8
+#define REG_PMU_APB_RF_PWR_STATUS0_DBG 0x00bc
+#define REG_PMU_APB_RF_PWR_STATUS1_DBG 0x00c0
+#define REG_PMU_APB_RF_PWR_STATUS2_DBG 0x00c4
+#define REG_PMU_APB_RF_PUB_SYS_AUTO_LIGHT_SLEEP_ENABLE 0x00c8
+#define REG_PMU_APB_RF_SLEEP_CTRL 0x00cc
+#define REG_PMU_APB_RF_DDR_SLEEP_CTRL 0x00d0
+#define REG_PMU_APB_RF_SLEEP_STATUS 0x00d4
+#define REG_PMU_APB_RF_PUB_SYS_SLEEP_BYPASS_CFG 0x00d8
+#define REG_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_POLL0 0x00dc
+#define REG_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_POLL1 0x00e0
+#define REG_PMU_APB_RF_CPPLL_REL_CFG 0x00e4
+#define REG_PMU_APB_RF_CPPLL_RST_CTRL_CFG 0x00e8
+#define REG_PMU_APB_RF_DDR_CHN_SLEEP_CTRL0 0x00f8
+#define REG_PMU_APB_RF_DDR_CHN_SLEEP_CTRL1 0x00fc
+#define REG_PMU_APB_RF_PWR_STATUS3_DBG 0x010c
+#define REG_PMU_APB_RF_DDR_OP_MODE_CFG 0x012c
+#define REG_PMU_APB_RF_DDR_PHY_RET_CFG 0x0130
+#define REG_PMU_APB_RF_CLK26M_SEL_CFG 0x0134
+#define REG_PMU_APB_RF_BISR_DONE_STATUS 0x0138
+#define REG_PMU_APB_RF_BISR_BUSY_STATUS 0x013c
+#define REG_PMU_APB_RF_BISR_BYP_CFG 0x0140
+#define REG_PMU_APB_RF_BISR_EN_CFG 0x0144
+#define REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG0 0x0148
+#define REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG1 0x014c
+#define REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG2 0x0150
+#define REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG3 0x0154
+#define REG_PMU_APB_RF_CGM_FORCE_EN_CFG0 0x0158
+#define REG_PMU_APB_RF_CGM_FORCE_EN_CFG1 0x015c
+#define REG_PMU_APB_RF_CGM_FORCE_EN_CFG2 0x0160
+#define REG_PMU_APB_RF_CGM_FORCE_EN_CFG3 0x0164
+#define REG_PMU_APB_RF_SLEEP_XTLON_CTRL 0x0168
+#define REG_PMU_APB_RF_MEM_SLP_CFG 0x016c
+#define REG_PMU_APB_RF_MEM_SD_CFG 0x0170
+#define REG_PMU_APB_RF_APCPU_CORE_WAKEUP_EN 0x0174
+#define REG_PMU_APB_RF_SP_SYS_HOLD_CGM_EN 0x0178
+#define REG_PMU_APB_RF_PWR_CNT_WAIT_CFG0 0x017c
+#define REG_PMU_APB_RF_PWR_CNT_WAIT_CFG1 0x0180
+#define REG_PMU_APB_RF_RCO_REL_CFG 0x0184
+#define REG_PMU_APB_RF_RCO_CNT_WAIT_CFG 0x018c
+#define REG_PMU_APB_RF_MPLL0_REL_CFG 0x0190
+#define REG_PMU_APB_RF_MPLL1_REL_CFG 0x0194
+#define REG_PMU_APB_RF_MPLL2_REL_CFG 0x0198
+#define REG_PMU_APB_RF_MEM_AUTO_SLP_CFG 0x019c
+#define REG_PMU_APB_RF_MEM_AUTO_SD_CFG 0x01a0
+#define REG_PMU_APB_RF_WAKEUP_LOCK_EN 0x01a4
+#define REG_PMU_APB_RF_AUDCP_SYS_CORE_INT_DISABLE 0x01a8
+#define REG_PMU_APB_RF_WTLCP_TGDSP_CORE_INT_DISABLE 0x01b0
+#define REG_PMU_APB_RF_WTLCP_LDSP_CORE_INT_DISABLE 0x01b4
+#define REG_PMU_APB_RF_PUBCP_CORE_INT_DISABLE 0x01b8
+#define REG_PMU_APB_RF_APCPU_C0_CORE_INT_DISABLE 0x01bc
+#define REG_PMU_APB_RF_APCPU_C1_CORE_INT_DISABLE 0x01c0
+#define REG_PMU_APB_RF_APCPU_C2_CORE_INT_DISABLE 0x01c4
+#define REG_PMU_APB_RF_APCPU_C7_CORE_INT_DISABLE 0x01d8
+#define REG_PMU_APB_RF_APCPU_C7_DSLP_ENA 0x01e8
+#define REG_PMU_APB_RF_CDMA_DSLP_ENA 0x01ec
+#define REG_PMU_APB_RF_WTLCP_TGDSP_DSLP_ENA 0x0200
+#define REG_PMU_APB_RF_WTLCP_LDSP_DSLP_ENA 0x0204
+#define REG_PMU_APB_RF_AP_DSLP_ENA 0x0208
+#define REG_PMU_APB_RF_PUBCP_DSLP_ENA 0x020c
+#define REG_PMU_APB_RF_WTLCP_DSLP_ENA 0x0210
+#define REG_PMU_APB_RF_APCPU_TOP_DSLP_ENA 0x0214
+#define REG_PMU_APB_RF_SP_SYS_DSLP_ENA 0x0218
+#define REG_PMU_APB_RF_PUB_DEEP_SLEEP_ENA 0x021c
+#define REG_PMU_APB_RF_PUB_DEEP_SLEEP_WAKEUP_EN 0x0220
+#define REG_PMU_APB_RF_LIGHT_SLEEP_WAKEUP_EN 0x0224
+#define REG_PMU_APB_RF_LIGHT_SLEEP_ENABLE 0x0230
+#define REG_PMU_APB_RF_LIGHT_SLEEP_MON 0x0234
+#define REG_PMU_APB_RF_DOZE_SLEEP_ENABLE 0x0238
+#define REG_PMU_APB_RF_DOZE_SLEEP_MON 0x023c
+#define REG_PMU_APB_RF_DOZE_FORCE_SLEEP_CTRL 0x0240
+#define REG_PMU_APB_RF_AUDCP_SYS_DSLP_ENA 0x0244
+#define REG_PMU_APB_RF_AUDCP_AUDDSP_DSLP_ENA 0x0248
+#define REG_PMU_APB_RF_PUB_ACC_RDY 0x0250
+#define REG_PMU_APB_RF_PUB_CLK_RDY 0x0254
+#define REG_PMU_APB_RF_EIC_SEL 0x0258
+#define REG_PMU_APB_RF_AXI_LP_CTRL_DISABLE 0x0260
+#define REG_PMU_APB_RF_PMU_DEBUG 0x0270
+#define REG_PMU_APB_RF_SLEEP_CNT_CLR 0x0274
+#define REG_PMU_APB_RF_LVDSRFPLL_REL_CFG 0x0280
+#define REG_PMU_APB_RF_EXT_XTL_EN_CTRL 0x0284
+#define REG_PMU_APB_RF_PAD_OUT_CHIP_SLEEP_CFG 0x0288
+#define REG_PMU_APB_RF_PAD_OUT_XTL_EN0_CFG 0x028c
+#define REG_PMU_APB_RF_PAD_OUT_XTL_EN1_CFG 0x0290
+#define REG_PMU_APB_RF_PAD_OUT_DCDC_ARM0_EN_CFG 0x0294
+#define REG_PMU_APB_RF_PAD_OUT_DCDC_ARM1_EN_CFG 0x0298
+#define REG_PMU_APB_RF_DCXO_LP_DEEP_SLEEP_CFG 0x029c
+#define REG_PMU_APB_RF_BISR_FORCE_SEL 0x0300
+#define REG_PMU_APB_RF_AON_MEM_CTRL 0x0330
+#define REG_PMU_APB_RF_PWR_DOMAIN_INT_CLR 0x0334
+#define REG_PMU_APB_RF_DDR_SLP_WAIT_CNT 0x0338
+#define REG_PMU_APB_RF_PMU_CLK_DIV_CFG 0x033c
+#define REG_PMU_APB_RF_CGM_PMU_SEL 0x0340
+#define REG_PMU_APB_RF_PWR_DGB_PARAMETER 0x0344
+#define REG_PMU_APB_RF_APCPU_C0_DSLP_ENA 0x0348
+#define REG_PMU_APB_RF_APCPU_C1_DSLP_ENA 0x034c
+#define REG_PMU_APB_RF_APCPU_C2_DSLP_ENA 0x0350
+#define REG_PMU_APB_RF_APCPU_GIC_RST_EN 0x0358
+#define REG_PMU_APB_RF_ANALOG_PHY_PD_CFG 0x035c
+#define REG_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_SEL 0x0360
+#define REG_PMU_APB_RF_PD_APCPU_C7_CFG 0x0370
+#define REG_PMU_APB_RF_PD_APCPU_TOP_CFG3 0x0374
+#define REG_PMU_APB_RF_APCU_PWR_STATE0 0x0378
+#define REG_PMU_APB_RF_APCU_PWR_STATE1 0x037c
+#define REG_PMU_APB_RF_APCPU_TOP_CFG 0x0380
+#define REG_PMU_APB_RF_APCPU_C0_CFG 0x0384
+#define REG_PMU_APB_RF_APCPU_C1_CFG 0x0388
+#define REG_PMU_APB_RF_APCPU_C2_CFG 0x038c
+#define REG_PMU_APB_RF_APCPU_DSLP_ENA_SRST_MASK_CFG 0x0390
+#define REG_PMU_APB_RF_APCPU_C7_CFG 0x03a0
+#define REG_PMU_APB_RF_GIC_CFG 0x03a8
+#define REG_PMU_APB_RF_FIREWALL_WAKEUP_PUB 0x03ac
+#define REG_PMU_APB_RF_APCPU_TOP_RMA_CTRL 0x03b0
+#define REG_PMU_APB_RF_APCPU_MODE_ST_CFG 0x03b4
+#define REG_PMU_APB_RF_APCPU_C0_SIMD_RET_MODE 0x03b8
+#define REG_PMU_APB_RF_APCPU_C1_SIMD_RET_MODE 0x03bc
+#define REG_PMU_APB_RF_APCPU_C2_SIMD_RET_MODE 0x03c0
+#define REG_PMU_APB_RF_APCPU_CORE_FORCE_STOP 0x03d4
+#define REG_PMU_APB_RF_APCU_MODE_STATE0 0x03d8
+#define REG_PMU_APB_RF_APCU_MODE_STATE1 0x03dc
+#define REG_PMU_APB_RF_PD_GPU_TOP_CFG1 0x03e0
+#define REG_PMU_APB_RF_MPLL_WAIT_CLK_DIV_CFG 0x03e4
+#define REG_PMU_APB_RF_MPLL0_RST_CTRL_CFG 0x03e8
+#define REG_PMU_APB_RF_MPLL1_RST_CTRL_CFG 0x03ec
+#define REG_PMU_APB_RF_MPLL2_RST_CTRL_CFG 0x03f0
+#define REG_PMU_APB_RF_DPLL0_RST_CTRL_CFG 0x03f8
+#define REG_PMU_APB_RF_DPLL1_RST_CTRL_CFG 0x03fc
+#define REG_PMU_APB_RF_TWPLL_RST_CTRL_CFG 0x0400
+#define REG_PMU_APB_RF_LTEPLL_RST_CTRL_CFG 0x0404
+#define REG_PMU_APB_RF_GPLL_RST_CTRL_CFG 0x0408
+#define REG_PMU_APB_RF_RPLL_RST_CTRL_CFG 0x040c
+#define REG_PMU_APB_RF_ISPPLL_RST_CTRL_CFG 0x0410
+#define REG_PMU_APB_RF_PLL_RST_CTRL_STATE0 0x0414
+#define REG_PMU_APB_RF_PLL_RST_CTRL_STATE1 0x0418
+#define REG_PMU_APB_RF_DUAL_RAIL_MEM_POWER_CTRL 0x0420
+#define REG_PMU_APB_RF_WTLCP_HU3GE_NEST_DOMAIN_CTRL 0x0424
+#define REG_PMU_APB_RF_DEBUG_RECOV_TYPE_CFG 0x0428
+#define REG_PMU_APB_RF_APCPU_MODE_ST_CFG1 0x042c
+#define REG_PMU_APB_RF_APCPU_MODE_ST_CFG2 0x0430
+#define REG_PMU_APB_RF_APCPU_MODE_ST_CFG3 0x0434
+#define REG_PMU_APB_RF_DEBUG_STATE_MARK 0x0438
+#define REG_PMU_APB_RF_ANANKELITE_MEM_POWER_CFG 0x043c
+#define REG_PMU_APB_RF_APCPU_MODE_ST_FRC_ON_CFG 0x0440
+#define REG_PMU_APB_RF_APCPU_SOFT_RST_TYPE_CFG 0x0444
+#define REG_PMU_APB_RF_APCPU_CORINTH_SCU_CLK_GATE_CFG 0x0448
+#define REG_PMU_APB_RF_APCPU_PCHANNEL_STATE0 0x044c
+#define REG_PMU_APB_RF_APCPU_PCHANNEL_STATE1 0x0450
+#define REG_PMU_APB_RF_APCPU_SOFT_INT_GEN 0x0454
+#define REG_PMU_APB_RF_DUAL_RAIL_RAM_FORCE_PD_CFG 0x0458
+#define REG_PMU_APB_RF_DUAL_RAIL_RAM_FORCE_SLP_CFG 0x045c
+#define REG_PMU_APB_RF_PUB_DFS_FRQ_SEL 0x0460
+#define REG_PMU_APB_RF_APCPU_CORE0_SW_PACTIVE 0x0464
+#define REG_PMU_APB_RF_APCPU_CORE1_SW_PACTIVE 0x0468
+#define REG_PMU_APB_RF_APCPU_CORE2_SW_PACTIVE 0x046c
+#define REG_PMU_APB_RF_APCPU_CORE7_SW_PACTIVE 0x0480
+#define REG_PMU_APB_RF_APCPU_CLUSTER_SW_PACTIVE 0x0484
+#define REG_PMU_APB_RF_SOFTWARE_APCPU_PACTIVE_ENABLE 0x0488
+#define REG_PMU_APB_RF_SOFTWARE_APCPU_PCHANNEL_HANDSHAKE_ENABLE 0x048c
+#define REG_PMU_APB_RF_APCPU_CORE0_SW_PCHANNEL_HANDSHAKE 0x0490
+#define REG_PMU_APB_RF_APCPU_CORE1_SW_PCHANNEL_HANDSHAKE 0x0494
+#define REG_PMU_APB_RF_APCPU_CORE2_SW_PCHANNEL_HANDSHAKE 0x0498
+#define REG_PMU_APB_RF_APCPU_CORE7_SW_PCHANNEL_HANDSHAKE 0x04ac
+#define REG_PMU_APB_RF_APCPU_CLUSTER_SW_PCHANNEL_HANDSHAKE 0x04b0
+#define REG_PMU_APB_RF_WTLCP_DPFEC_NEST_DOMAIN_CTRL 0x04b4
+#define REG_PMU_APB_RF_GPIO_FORCE_GATING_PLL_CFG 0x04b8
+#define REG_PMU_APB_RF_ANALOG_PHY_PWRON_CFG 0x04bc
+#define REG_PMU_APB_RF_APCPU_MODE_ST_CGM_EN_CFG 0x04c0
+#define REG_PMU_APB_RF_APCPU_DENY_TIME_THRESHOLD_CFG 0x04c4
+#define REG_PMU_APB_RF_INT_REQ_APCPU_MODE_ST_ENABLE 0x04c8
+#define REG_PMU_APB_RF_INT_REQ_APCPU_MODE_ST_CLR 0x04cc
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_RECORD 0x04d0
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE0_INF 0x04d4
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE1_INF 0x04d8
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE2_INF 0x04dc
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE7_INF 0x04f0
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CLUSTER_INF 0x04f4
+#define REG_PMU_APB_RF_APCPU_CSYSPWRUP_WAKEUP_EN_CFG 0x04f8
+#define REG_PMU_APB_RF_DVFS_BLOCK_SHUTDOWN_CFG 0x04fc
+#define REG_PMU_APB_RF_OFF_EMU_CLR_IN_DISABLE_CFG 0x0500
+#define REG_PMU_APB_RF_ANANKE_LITE_DUAL_RAIL_RAM_FORCE_ON_CFG 0x0504
+#define REG_PMU_APB_RF_OFF_EMU_TO_OFF_CFG 0x0508
+#define REG_PMU_APB_RF_ALL_PLL_PD_RCO_BYP 0x050c
+#define REG_PMU_APB_RF_SP_CLK_GATE_BYP_CFG 0x0510
+#define REG_PMU_APB_RF_DPLL1_CNT_DONE_BYP 0x0514
+#define REG_PMU_APB_RF_SRAM_DLY_CTRL_CFG 0x0518
+#define REG_PMU_APB_RF_WDG_TRIG_DBG_RECOV_CFG 0x051c
+#define REG_PMU_APB_RF_PD_CDMA_SYS_SHUTDOWN_MARK_STATUS 0x0600
+#define REG_PMU_APB_RF_CDMA_DEEP_SLEEP_CNT 0x0610
+#define REG_PMU_APB_RF_CDMA_DEEP_SLEEP_CFG 0x0620
+#define REG_PMU_APB_RF_CDMA_WAKEUP_CFG 0x0624
+#define REG_PMU_APB_RF_CDMA_PROC1_PWR_CFG 0x0630
+#define REG_PMU_APB_RF_PD_APCPU_C0_SHUTDOWN_MARK_STATUS 0x0700
+#define REG_PMU_APB_RF_PD_APCPU_C1_SHUTDOWN_MARK_STATUS 0x0704
+#define REG_PMU_APB_RF_PD_APCPU_C2_SHUTDOWN_MARK_STATUS 0x0708
+#define REG_PMU_APB_RF_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS 0x070c
+#define REG_PMU_APB_RF_PD_AP_SYS_SHUTDOWN_MARK_STATUS 0x0710
+#define REG_PMU_APB_RF_PD_GPU_TOP_SHUTDOWN_MARK_STATUS 0x0714
+#define REG_PMU_APB_RF_PD_MM_TOP_SHUTDOWN_MARK_STATUS 0x0718
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_CE_SHUTDOWN_MARK_STATUS 0x071c
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_DPFEC_SHUTDOWN_MARK_STATUS 0x0720
+#define REG_PMU_APB_RF_PD_AP_VSP_SHUTDOWN_MARK_STATUS 0x0724
+#define REG_PMU_APB_RF_PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS 0x0728
+#define REG_PMU_APB_RF_PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS 0x072c
+#define REG_PMU_APB_RF_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS 0x0730
+#define REG_PMU_APB_RF_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS 0x0734
+#define REG_PMU_APB_RF_PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS 0x0738
+#define REG_PMU_APB_RF_PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS 0x073c
+#define REG_PMU_APB_RF_PD_WTLCP_LTE_PROC_SHUTDOWN_MARK_STATUS 0x0740
+#define REG_PMU_APB_RF_PD_WTLCP_TD_PROC_SHUTDOWN_MARK_STATUS 0x0744
+#define REG_PMU_APB_RF_PD_AUDCP_SYS_SHUTDOWN_MARK_STATUS 0x0748
+#define REG_PMU_APB_RF_PD_PUB_SYS_SHUTDOWN_MARK_STATUS 0x074c
+#define REG_PMU_APB_RF_PD_AUDCP_AUDDSP_SHUTDOWN_MARK_STATUS 0x0750
+#define REG_PMU_APB_RF_PD_GPU_RGX_DUST_SHUTDOWN_MARK_STATUS 0x0754
+#define REG_PMU_APB_RF_APCPU_TOP_SLEEP_CNT 0x0758
+#define REG_PMU_APB_RF_AP_SYS_SLEEP_CNT 0x075c
+#define REG_PMU_APB_RF_WTLCP_SYS_SLEEP_CNT 0x0760
+#define REG_PMU_APB_RF_PUBCP_SYS_SLEEP_CNT 0x0764
+#define REG_PMU_APB_RF_AUDCP_SYS_SLEEP_CNT 0x0768
+#define REG_PMU_APB_RF_PUB_SYS_LIGHT_SLEEP_CNT 0x076c
+#define REG_PMU_APB_RF_AP_DEEP_SLEEP_CNT 0x0770
+#define REG_PMU_APB_RF_SP_SYS_DEEP_SLEEP_CNT 0x0774
+#define REG_PMU_APB_RF_WTLCP_DEEP_SLEEP_CNT 0x0778
+#define REG_PMU_APB_RF_PUBCP_DEEP_SLEEP_CNT 0x077c
+#define REG_PMU_APB_RF_AUDCP_SYS_DEEP_SLEEP_CNT 0x0780
+#define REG_PMU_APB_RF_PUB_SYS_DEEP_SLEEP_CNT 0x0784
+#define REG_PMU_APB_RF_AP_LIGHT_SLEEP_CNT 0x0788
+#define REG_PMU_APB_RF_WTLCP_LIGHT_SLEEP_CNT 0x078c
+#define REG_PMU_APB_RF_PUBCP_LIGHT_SLEEP_CNT 0x0790
+#define REG_PMU_APB_RF_AUDCP_SYS_LIGHT_SLEEP_CNT 0x0794
+#define REG_PMU_APB_RF_AON_SYS_LIGHT_SLEEP_CNT 0x0798
+#define REG_PMU_APB_RF_SYS_SOFT_RST_BUSY 0x079c
+#define REG_PMU_APB_RF_REG_SYS_SRST_FRC_LP_ACK 0x07a0
+#define REG_PMU_APB_RF_SOFT_RST_SEL 0x07a4
+#define REG_PMU_APB_RF_REG_SYS_DDR_PWR_HS_ACK 0x07a8
+#define REG_PMU_APB_RF_CSI_DSI_PWR_CNT_DONE 0x07ac
+#define REG_PMU_APB_RF_PD_AP_SYS_DBG_SHUTDOWN_EN 0x07b0
+#define REG_PMU_APB_RF_EIC_SYS_SEL 0x07b4
+#define REG_PMU_APB_RF_DDR_SLP_CTRL_STATE 0x07b8
+#define REG_PMU_APB_RF_PD_APCPU_C7_SHUTDOWN_MARK_STATUS 0x07bc
+#define REG_PMU_APB_RF_APCPU_TOP_DEEP_SLEEP_CNT 0x07c0
+#define REG_PMU_APB_RF_APCPU_TOP_LIGHT_SLEEP_CNT 0x07c4
+#define REG_PMU_APB_RF_AP_DOZE_SLEEP_CNT 0x07c8
+#define REG_PMU_APB_RF_WTLCP_DOZE_SLEEP_CNT 0x07cc
+#define REG_PMU_APB_RF_PUBCP_DOZE_SLEEP_CNT 0x07d0
+#define REG_PMU_APB_RF_AUDCP_DOZE_SLEEP_CNT 0x07d4
+#define REG_PMU_APB_RF_PD_APCPU_C3_CFG 0x07d8
+#define REG_PMU_APB_RF_PD_APCPU_C4_CFG 0x07dc
+#define REG_PMU_APB_RF_PD_APCPU_C5_CFG 0x07e0
+#define REG_PMU_APB_RF_PD_AP_VDSP_CFG 0x07e4
+#define REG_PMU_APB_RF_APCPU_C3_CORE_INT_DISABLE 0x07e8
+#define REG_PMU_APB_RF_APCPU_C4_CORE_INT_DISABLE 0x07ec
+#define REG_PMU_APB_RF_APCPU_C5_CORE_INT_DISABLE 0x07f0
+#define REG_PMU_APB_RF_APCPU_C6_CORE_INT_DISABLE 0x07f4
+#define REG_PMU_APB_RF_AP_VDSP_CORE_INT_DISABLE 0x07f8
+#define REG_PMU_APB_RF_APCPU_WFI_MARK 0x07fc
+#define REG_PMU_APB_RF_APCPU_C6_DSLP_ENA 0x0800
+#define REG_PMU_APB_RF_AP_VDSP_DSLP_ENA 0x0804
+#define REG_PMU_APB_RF_APCPU_C3_DSLP_ENA 0x0808
+#define REG_PMU_APB_RF_APCPU_C4_DSLP_ENA 0x080c
+#define REG_PMU_APB_RF_APCPU_C5_DSLP_ENA 0x0810
+#define REG_PMU_APB_RF_PD_APCPU_C6_CFG 0x0814
+#define REG_PMU_APB_RF_PD_APCPU_CPU1_CFG1 0x0818
+#define REG_PMU_APB_RF_PD_APCPU_CPU1_CFG2 0x081c
+#define REG_PMU_APB_RF_APCU_PWR_STATE_FIG 0x0820
+#define REG_PMU_APB_RF_APCPU_C3_CFG 0x0824
+#define REG_PMU_APB_RF_APCPU_C4_CFG 0x0828
+#define REG_PMU_APB_RF_APCPU_C5_CFG 0x082c
+#define REG_PMU_APB_RF_APCPU_C6_CFG 0x0830
+#define REG_PMU_APB_RF_APCPU_C3_SIMD_RET_MODE 0x0834
+#define REG_PMU_APB_RF_APCPU_C4_SIMD_RET_MODE 0x0838
+#define REG_PMU_APB_RF_APCPU_C5_SIMD_RET_MODE 0x083c
+#define REG_PMU_APB_RF_APCU_MODE_STATE_FIG 0x0840
+#define REG_PMU_APB_RF_APCPU_CORE3_SW_PACTIVE 0x0844
+#define REG_PMU_APB_RF_APCPU_CORE4_SW_PACTIVE 0x0848
+#define REG_PMU_APB_RF_APCPU_CORE5_SW_PACTIVE 0x084c
+#define REG_PMU_APB_RF_APCPU_CORE6_SW_PACTIVE 0x0850
+#define REG_PMU_APB_RF_APCPU_CORE3_SW_PCHANNEL_HANDSHAKE 0x0854
+#define REG_PMU_APB_RF_APCPU_CORE4_SW_PCHANNEL_HANDSHAKE 0x0858
+#define REG_PMU_APB_RF_APCPU_CORE5_SW_PCHANNEL_HANDSHAKE 0x085c
+#define REG_PMU_APB_RF_APCPU_CORE6_SW_PCHANNEL_HANDSHAKE 0x0860
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE3_INF 0x0864
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE4_INF 0x0868
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE5_INF 0x086c
+#define REG_PMU_APB_RF_INT_REQ_MODE_ST_APCPU_CORE6_INF 0x0870
+#define REG_PMU_APB_RF_PD_APCPU_C3_SHUTDOWN_MARK_STATUS 0x0874
+#define REG_PMU_APB_RF_PD_APCPU_C4_SHUTDOWN_MARK_STATUS 0x0878
+#define REG_PMU_APB_RF_PD_APCPU_C5_SHUTDOWN_MARK_STATUS 0x087c
+#define REG_PMU_APB_RF_PD_AP_VDSP_SHUTDOWN_MARK_STATUS 0x0880
+#define REG_PMU_APB_RF_PD_APCPU_C6_SHUTDOWN_MARK_STATUS 0x0884
+#define REG_PMU_APB_RF_MEM_AUTO_SLP_CFG_FIG 0x0888
+#define REG_PMU_APB_RF_MEM_AUTO_SD_CFG_FIG 0x088c
+#define REG_PMU_APB_RF_MEM_SLP_CFG_FIG 0x0890
+#define REG_PMU_APB_RF_MEM_SD_CFG_FIG 0x0894
+#define REG_PMU_APB_RF_PD_GPU_CORE_CFG0 0x0898
+#define REG_PMU_APB_RF_EPPLL_REL_CFG 0x089c
+#define REG_PMU_APB_RF_EPPLL_RST_CTRL_CFG 0x08a0
+#define REG_PMU_APB_RF_EPPLL_DELAY_CTRL_CFG0 0x08a4
+#define REG_PMU_APB_RF_EPPLL_DELAY_CTRL_CFG1 0x08a8
+#define REG_PMU_APB_RF_EPPLL_DELAY_CTRL_CFG2 0x08ac
+#define REG_PMU_APB_RF_EPPLL_DELAY_CTRL_CFG3 0x08b0
+#define REG_PMU_APB_RF_EPPLL_PLL_SEL_CFG 0x08b4
+#define REG_DBG_APB_RF_SUB_SYS_DBG_BUSY_TIMER_FOR_BUSMON 0x0000
+#define REG_DBG_APB_RF_SUB_SYS_DBG_MISC_SIGNAL 0x0004
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PWR_CTRL 0x0008
+#define REG_DBG_APB_RF_SUB_SYS_DBG_DBG_CTRL 0x000c
+#define REG_DBG_APB_RF_SUB_SYS_DBG_STM_SOFT_RST 0x0010
+#define REG_DBG_APB_RF_SUB_SYS_DBG_RCO_CLK_CTRL 0x0014
+#define REG_DBG_APB_RF_SUB_SYS_DBG_SEL_CFG0 0x0018
+#define REG_DBG_APB_RF_SUB_SYS_DBG_SEL_CFG1 0x001c
+#define REG_DBG_APB_RF_SUB_SYS_DBG_SEL_CFG2 0x0020
+#define REG_DBG_APB_RF_SUB_SYS_DBG_SEL_CFG3 0x0024
+#define REG_DBG_APB_RF_SUB_SYS_DBG_SEL_CFG4 0x0028
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG0 0x002c
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG1 0x0030
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG2 0x0034
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG3 0x0038
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG4 0x003c
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG5 0x0040
+#define REG_DBG_APB_RF_SUB_SYS_DBG_PAD_SEL_CFG6 0x0044
+#define REG_DBG_APB_RF_PAD_DBG_BUS_DATA_A 0x0048
+#define REG_DBG_APB_RF_PAD_DBG_BUS_DATA_B 0x004c
+#define REG_DBG_APB_RF_PAD_DBG_BUS_DATA_OUT 0x0050
+#define REG_DBG_APB_RF_ETR_AXI_MON_INT_EN 0x0054
+#define REG_DBG_APB_RF_ETR_AXI_MON_INT_CLR 0x0058
+#define REG_DBG_APB_RF_ETR_AXI_MON_INT_RAW 0x005c
+#define REG_DBG_APB_RF_ETR_AXI_MON_INT_STAT 0x0060
+#define REG_DBG_APB_RF_ETR_AXI_MON_AWADDR0 0x0064
+#define REG_DBG_APB_RF_ETR_AXI_MON_AWADDR1 0x0068
+#define REG_DBG_APB_RF_ETR_AXI_MON_AWADDR2 0x006c
+#define REG_DBG_APB_RF_ETR_AXI_MON_AWADDR3 0x0070
+#define REG_REG_FW1_AON_REG_RD_CTRL_0 0x0000
+#define REG_REG_FW1_AON_REG_RD_CTRL_1 0x0004
+#define REG_REG_FW1_AON_REG_RD_CTRL_2 0x0008
+#define REG_REG_FW1_AON_REG_RD_CTRL_3 0x000c
+#define REG_REG_FW1_AON_REG_RD_CTRL_4 0x0010
+#define REG_REG_FW1_AON_REG_RD_CTRL_5 0x0014
+#define REG_REG_FW1_AON_REG_RD_CTRL_6 0x0018
+#define REG_REG_FW1_AON_REG_RD_CTRL_7 0x001c
+#define REG_REG_FW1_AON_REG_RD_CTRL_8 0x0020
+#define REG_REG_FW1_AON_REG_RD_CTRL_9 0x0024
+#define REG_REG_FW1_AON_REG_RD_CTRL_10 0x0028
+#define REG_REG_FW1_AON_REG_WR_CTRL_0 0x002c
+#define REG_REG_FW1_AON_REG_WR_CTRL_1 0x0030
+#define REG_REG_FW1_AON_REG_WR_CTRL_2 0x0034
+#define REG_REG_FW1_AON_REG_WR_CTRL_3 0x0038
+#define REG_REG_FW1_AON_REG_WR_CTRL_4 0x003c
+#define REG_REG_FW1_AON_REG_WR_CTRL_5 0x0040
+#define REG_REG_FW1_AON_REG_WR_CTRL_6 0x0044
+#define REG_REG_FW1_AON_REG_WR_CTRL_7 0x0048
+#define REG_REG_FW1_AON_REG_WR_CTRL_8 0x004c
+#define REG_REG_FW1_AON_REG_WR_CTRL_9 0x0050
+#define REG_REG_FW1_AON_REG_WR_CTRL_10 0x0054
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY0 0x0058
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY1 0x005c
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY2 0x0060
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY3 0x0064
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY4 0x0068
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY5 0x006c
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY6 0x0070
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY7 0x0074
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY8 0x0078
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY9 0x007c
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY10 0x0080
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY11 0x0084
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY12 0x0088
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY13 0x008c
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY14 0x0090
+#define REG_REG_FW1_AON_BIT_CTRL_ADDR_ARRAY15 0x0094
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY0 0x0098
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY1 0x009c
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY2 0x00a0
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY3 0x00a4
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY4 0x00a8
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY5 0x00ac
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY6 0x00b0
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY7 0x00b4
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY8 0x00b8
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY9 0x00bc
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY10 0x00c0
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY11 0x00c4
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY12 0x00c8
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY13 0x00cc
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY14 0x00d0
+#define REG_REG_FW1_AON_BIT_CTRL_ARRAY15 0x00d4
+#define REG_MM_CLK_CORE_CGM_MM_AHB_CFG 0x0020
+#define REG_MM_CLK_CORE_CGM_MM_MTX_CFG 0x0024
+#define REG_MM_CLK_CORE_CGM_SENSOR0_CFG 0x0028
+#define REG_MM_CLK_CORE_CGM_SENSOR1_CFG 0x002c
+#define REG_MM_CLK_CORE_CGM_SENSOR2_CFG 0x0030
+#define REG_MM_CLK_CORE_CGM_CPP_CFG 0x0034
+#define REG_MM_CLK_CORE_CGM_JPG_CFG 0x0038
+#define REG_MM_CLK_CORE_CGM_FD_CFG 0x003c
+#define REG_MM_CLK_CORE_CGM_DCAM_IF_CFG 0x0040
+#define REG_MM_CLK_CORE_CGM_DCAM_AXI_CFG 0x0044
+#define REG_MM_CLK_CORE_CGM_ISP_CFG 0x0048
+#define REG_MM_CLK_CORE_CGM_MIPI_CSI0_CFG 0x004c
+#define REG_MM_CLK_CORE_CGM_MIPI_CSI1_CFG 0x0050
+#define REG_MM_CLK_CORE_CGM_MIPI_CSI2_CFG 0x0054
+#define REG_MM_CLK_CORE_CGM_CPHY_CFG_CFG 0x0058
+#define REG_MM_CLK_CORE_CGM_CSI_PHY_SCAN_ONLY_CFG 0x005c
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_ANA_DPLL_DUMY 0x0000
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL0 0x0004
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL2 0x0008
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL3 0x000c
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL4 0x0010
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL5 0x0014
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_DPLL_CTRL13 0x0018
+#define REG_ANLG_PHY_G0_RF_ANALOG_DPLL_TOP_REG_SEL_CFG_0 0x001c
+#define REG_AUD_CP_APB_RF_APB_EB 0x0000
+#define REG_AUD_CP_APB_RF_APB_RST 0x0004
+#define REG_AUD_CP_APB_RF_AON_BUS_CTRL0 0x0008
+#define REG_AUD_CP_APB_RF_SLEEP_CTRL0 0x000c
+#define REG_AUD_CP_APB_RF_SLEEP_STATUS 0x0014
+#define REG_AUD_CP_APB_RF_INT_MASK 0x0018
+#define REG_AUD_CP_APB_RF_MEM_SLP 0x001c
+#define REG_AUD_CP_APB_RF_AON_RESERVED 0x0020
+#define REG_AUD_CP_APB_RF_IRAM_ENDIAN 0x0024
+#define REG_PUB_AHB_RF_DMC_EXT_LPCTRL_CFG 0x3000
+#define REG_PUB_AHB_RF_DMC_EXT_LPCTRL_SEQL 0x3004
+#define REG_PUB_AHB_RF_DMC_EXT_LPCTRL_SEQH 0x3008
+#define REG_PUB_AHB_RF_DMC_EXT_LPCTRL_STEP 0x300c
+#define REG_PUB_AHB_RF_MPU_DUMP_ADDR 0x3010
+#define REG_PUB_AHB_RF_DMC_MPU_VIO_ADDR 0x3014
+#define REG_PUB_AHB_RF_DMC_MPU_VIO_CMD 0x3018
+#define REG_PUB_AHB_RF_DMC_MPU_BASE_CFG 0x301c
+#define REG_PUB_AHB_RF_RF_MPU_CFG0 0x3020
+#define REG_PUB_AHB_RF_RF_MPU_CFG0_ID_MASK_VAL 0x3024
+#define REG_PUB_AHB_RF_RF_MPU_CFG0_LOW_RANGE 0x3028
+#define REG_PUB_AHB_RF_RF_MPU_CFG0_HIGH_RANGE 0x302c
+#define REG_PUB_AHB_RF_RF_MPU_CFG1 0x3030
+#define REG_PUB_AHB_RF_RF_MPU_CFG1_ID_MASK_VAL 0x3034
+#define REG_PUB_AHB_RF_RF_MPU_CFG1_LOW_RANGE 0x3038
+#define REG_PUB_AHB_RF_RF_MPU_CFG1_HIGH_RANGE 0x303c
+#define REG_PUB_AHB_RF_RF_MPU_CFG2 0x3040
+#define REG_PUB_AHB_RF_RF_MPU_CFG2_ID_MASK_VAL 0x3044
+#define REG_PUB_AHB_RF_RF_MPU_CFG2_LOW_RANGE 0x3048
+#define REG_PUB_AHB_RF_RF_MPU_CFG2_HIGH_RANGE 0x304c
+#define REG_PUB_AHB_RF_RF_MPU_CFG3 0x3050
+#define REG_PUB_AHB_RF_RF_MPU_CFG3_ID_MASK_VAL 0x3054
+#define REG_PUB_AHB_RF_RF_MPU_CFG3_LOW_RANGE 0x3058
+#define REG_PUB_AHB_RF_RF_MPU_CFG3_HIGH_RANGE 0x305c
+#define REG_PUB_AHB_RF_RF_MPU_CFG4 0x3060
+#define REG_PUB_AHB_RF_RF_MPU_CFG4_ID_MASK_VAL 0x3064
+#define REG_PUB_AHB_RF_RF_MPU_CFG4_LOW_RANGE 0x3068
+#define REG_PUB_AHB_RF_RF_MPU_CFG4_HIGH_RANGE 0x306c
+#define REG_PUB_AHB_RF_RF_MPU_CFG5 0x3070
+#define REG_PUB_AHB_RF_RF_MPU_CFG5_ID_MASK_VAL 0x3074
+#define REG_PUB_AHB_RF_RF_MPU_CFG5_LOW_RANGE 0x3078
+#define REG_PUB_AHB_RF_RF_MPU_CFG5_HIGH_RANGE 0x307c
+#define REG_PUB_AHB_RF_RF_MPU_CFG6 0x3080
+#define REG_PUB_AHB_RF_RF_MPU_CFG6_ID_MASK_VAL 0x3084
+#define REG_PUB_AHB_RF_RF_MPU_CFG6_LOW_RANGE 0x3088
+#define REG_PUB_AHB_RF_RF_MPU_CFG6_HIGH_RANGE 0x308c
+#define REG_PUB_AHB_RF_RF_MPU_CFG7 0x3090
+#define REG_PUB_AHB_RF_RF_MPU_CFG7_ID_MASK_VAL 0x3094
+#define REG_PUB_AHB_RF_RF_MPU_CFG7_LOW_RANGE 0x3098
+#define REG_PUB_AHB_RF_RF_MPU_CFG7_HIGH_RANGE 0x309c
+#define REG_PUB_AHB_RF_RF_MPU_CFG8 0x30a0
+#define REG_PUB_AHB_RF_RF_MPU_CFG8_ID_MASK_VAL 0x30a4
+#define REG_PUB_AHB_RF_RF_MPU_CFG8_LOW_RANGE 0x30a8
+#define REG_PUB_AHB_RF_RF_MPU_CFG8_HIGH_RANGE 0x30ac
+#define REG_PUB_AHB_RF_RF_MPU_CFG9 0x30b0
+#define REG_PUB_AHB_RF_RF_MPU_CFG9_ID_MASK_VAL 0x30b4
+#define REG_PUB_AHB_RF_RF_MPU_CFG9_LOW_RANGE 0x30b8
+#define REG_PUB_AHB_RF_RF_MPU_CFG9_HIGH_RANGE 0x30bc
+#define REG_PUB_AHB_RF_RF_MPU_CFG10 0x30c0
+#define REG_PUB_AHB_RF_RF_MPU_CFG10_ID_MASK_VAL 0x30c4
+#define REG_PUB_AHB_RF_RF_MPU_CFG10_LOW_RANGE 0x30c8
+#define REG_PUB_AHB_RF_RF_MPU_CFG10_HIGH_RANGE 0x30cc
+#define REG_PUB_AHB_RF_RF_MPU_CFG11 0x30d0
+#define REG_PUB_AHB_RF_RF_MPU_CFG11_ID_MASK_VAL 0x30d4
+#define REG_PUB_AHB_RF_RF_MPU_CFG11_LOW_RANGE 0x30d8
+#define REG_PUB_AHB_RF_RF_MPU_CFG11_HIGH_RANGE 0x30dc
+#define REG_PUB_AHB_RF_RF_MPU_CFG12 0x30e0
+#define REG_PUB_AHB_RF_RF_MPU_CFG12_ID_MASK_VAL 0x30e4
+#define REG_PUB_AHB_RF_RF_MPU_CFG12_LOW_RANGE 0x30e8
+#define REG_PUB_AHB_RF_RF_MPU_CFG12_HIGH_RANGE 0x30ec
+#define REG_PUB_AHB_RF_RF_MPU_CFG13 0x30f0
+#define REG_PUB_AHB_RF_RF_MPU_CFG13_ID_MASK_VAL 0x30f4
+#define REG_PUB_AHB_RF_RF_MPU_CFG13_LOW_RANGE 0x30f8
+#define REG_PUB_AHB_RF_RF_MPU_CFG13_HIGH_RANGE 0x30fc
+#define REG_PUB_AHB_RF_RF_MPU_CFG14 0x3100
+#define REG_PUB_AHB_RF_RF_MPU_CFG14_ID_MASK_VAL 0x3104
+#define REG_PUB_AHB_RF_RF_MPU_CFG14_LOW_RANGE 0x3108
+#define REG_PUB_AHB_RF_RF_MPU_CFG14_HIGH_RANGE 0x310c
+#define REG_PUB_AHB_RF_RF_MPU_CFG15 0x3110
+#define REG_PUB_AHB_RF_RF_MPU_CFG15_ID_MASK_VAL 0x3114
+#define REG_PUB_AHB_RF_RF_MPU_CFG15_LOW_RANGE 0x3118
+#define REG_PUB_AHB_RF_RF_MPU_CFG15_HIGH_RANGE 0x311c
--
2.25.1
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