linux-kernel - [PATCH 2/3] phy: qcom-qmp: clean up define alignment

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Message-Id: <20220609120338.4080-3-johan+linaro@kernel.org>
Date:   Thu,  9 Jun 2022 14:03:37 +0200
From:   Johan Hovold <johan+linaro@...nel.org>
To:     Vinod Koul <vkoul@...nel.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Johan Hovold <johan+linaro@...nel.org>
Subject: [PATCH 2/3] phy: qcom-qmp: clean up define alignment

Clean up the QMP defines by removing some stray white space and making
sure values are aligned.

Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp.h | 48 ++++++++++++++---------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 626be0ccede2..6d410826ae90 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -627,8 +627,8 @@
 #define QSERDES_V4_TX_INTERFACE_SELECT			0x2c
 #define QSERDES_V4_TX_RES_CODE_LANE_TX			0x34
 #define QSERDES_V4_TX_RES_CODE_LANE_RX			0x38
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 		0x3c
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX		0x3c
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX		0x40
 #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN		0x54
 #define QSERDES_V4_TX_HIGHZ_DRVR_EN			0x58
 #define QSERDES_V4_TX_TX_POL_INV			0x5c
@@ -678,7 +678,7 @@
 #define QSERDES_V4_RX_UCDR_SB2_THRESH2			0x050
 #define QSERDES_V4_RX_UCDR_SB2_GAIN1			0x054
 #define QSERDES_V4_RX_UCDR_SB2_GAIN2			0x058
-#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE			0x060
+#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE		0x060
 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL			0x064
 #define QSERDES_V4_RX_AC_JTAG_ENABLE			0x068
 #define QSERDES_V4_RX_AC_JTAG_MODE			0x078
@@ -759,26 +759,26 @@
 #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2		0x23c
 
 /* Only for QMP V4 PHY - UFS PCS registers */
-#define QPHY_V4_PCS_UFS_PHY_START				0x000
-#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004
-#define QPHY_V4_PCS_UFS_SW_RESET				0x008
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB		0x00c
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB		0x010
-#define QPHY_V4_PCS_UFS_PLL_CNTL				0x02c
-#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL			0x030
-#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL			0x038
-#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL			0x060
-#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY			0x074
-#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY			0x0b4
-#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124
-#define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148
-#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150
-#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158
-#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160
-#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168
+#define QPHY_V4_PCS_UFS_PHY_START			0x000
+#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL		0x004
+#define QPHY_V4_PCS_UFS_SW_RESET			0x008
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010
+#define QPHY_V4_PCS_UFS_PLL_CNTL			0x02c
+#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030
+#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038
+#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL		0x060
+#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY		0x074
+#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY		0x0b4
+#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL		0x124
+#define QPHY_V4_PCS_UFS_LINECFG_DISABLE			0x148
+#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME		0x150
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2			0x158
+#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND		0x160
+#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND			0x168
 #define QPHY_V4_PCS_UFS_READY_STATUS			0x180
-#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1			0x1d8
-#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1			0x1e0
+#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1		0x1d8
+#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1		0x1e0
 
 /* PCIE GEN3 COM registers */
 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER			0x14
@@ -1140,8 +1140,8 @@
 /* Only for QMP V5 PHY - TX registers */
 #define QSERDES_V5_TX_RES_CODE_LANE_TX			0x34
 #define QSERDES_V5_TX_RES_CODE_LANE_RX			0x38
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 		0x3c
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 		0x40
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX		0x3c
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX		0x40
 #define QSERDES_V5_TX_LANE_MODE_1			0x84
 #define QSERDES_V5_TX_LANE_MODE_2			0x88
 #define QSERDES_V5_TX_LANE_MODE_3			0x8c
-- 
2.35.1