linux-kernel - Re: [PATCH net-next v2 5/5] net: dsa: realtek: rtl8365mb: handle PHY interface modes correctly

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220610174504.myd3z5vcs6ldhbei@bang-olufsen.dk>
Date:   Fri, 10 Jun 2022 17:45:05 +0000
From:   Alvin Šipraga <ALSI@...g-olufsen.dk>
To:     "Russell King (Oracle)" <linux@...linux.org.uk>
CC:     Alvin Šipraga <alvin@...s.dk>,
        "hauke@...ke-m.de" <hauke@...ke-m.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next v2 5/5] net: dsa: realtek: rtl8365mb: handle PHY
 interface modes correctly

On Fri, Jun 10, 2022 at 05:36:39PM +0100, Russell King (Oracle) wrote:
> On Fri, Jun 10, 2022 at 05:38:29PM +0200, Alvin ┼áipraga wrote:
> > Finally, rtl8365mb_phylink_get_caps() is fixed up to return supported
> > capabilities based on the external interface properties described above.
> > This allows for ports with an external interface to be treated as DSA
> > user ports, and for ports with an internal PHY to be treated as DSA CPU
> > ports.
> 
> I've needed to read that a few times... and I'm still not sure. You seem
> to be saying that:
> - ports with an internal PHY (which presumably provide baseT connections?)
>   are used as DSA CPU ports.

With this change they now _can_ be used as CPU ports. In practice I think most
application would use ports with internal PHY as DSA user ports. But the
hardware can treat any port as a CPU port, and as Vladimir pointed out in the
thread I added in the Link:, the previous test (dsa_is_user_port()) was
spurious.

> - ports with an external interface supporting a range of RGMII, SGMII and
>   HSGMII interface modes are DSA user ports.

Same as above: previously they could not be configured as DSA user ports. Now
they can be. The utility is up for debate, but at least the code is correct.

> 
> With Marvell switches, it's the other way around - the ports with an
> internal PHY are normally DSA user ports. Other ports can be a user,
> inter-switch or CPU port.
> 
> So, I'm slightly confused by your description.

After reading the above, please let me know if you are still confused.

Kind regards,
Alvin