[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <bf0e81ff59a73e6a2f56a04287cb3f62d8d7aa60.camel@intel.com>
Date: Fri, 10 Jun 2022 23:32:45 +0000
From: "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>
To: "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
"peterz@...radead.org" <peterz@...radead.org>,
"Lutomirski, Andy" <luto@...nel.org>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"hjl.tools@...il.com" <hjl.tools@...il.com>,
"linux-mm@...ck.org" <linux-mm@...ck.org>,
"kcc@...gle.com" <kcc@...gle.com>,
"andreyknvl@...il.com" <andreyknvl@...il.com>,
"ak@...ux.intel.com" <ak@...ux.intel.com>,
"dvyukov@...gle.com" <dvyukov@...gle.com>,
"x86@...nel.org" <x86@...nel.org>,
"ryabinin.a.a@...il.com" <ryabinin.a.a@...il.com>,
"glider@...gle.com" <glider@...gle.com>
Subject: Re: [PATCHv3 1/8] x86/mm: Fix CR3_ADDR_MASK
On Fri, 2022-06-10 at 17:35 +0300, Kirill A. Shutemov wrote:
> The mask must not include bits above physical address mask. These
> bits
> are reserved and can be used for other things. Bits 61 and 62 are
> used
> for Linear Address Masking.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
> ---
> arch/x86/include/asm/processor-flags.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/processor-flags.h
> b/arch/x86/include/asm/processor-flags.h
> index 02c2cbda4a74..a7f3d9100adb 100644
> --- a/arch/x86/include/asm/processor-flags.h
> +++ b/arch/x86/include/asm/processor-flags.h
> @@ -35,7 +35,7 @@
> */
> #ifdef CONFIG_X86_64
> /* Mask off the address space ID and SME encryption bits. */
> -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
> +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK)
> #define CR3_PCID_MASK 0xFFFull
> #define CR3_NOFLUSH BIT_ULL(63)
>
Reviewed-by: Rick Edgecombe <rick.p.edgecombe@...el.com>
Powered by blists - more mailing lists