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Message-Id: <20220610072924.12362-6-alim.akhtar@samsung.com>
Date: Fri, 10 Jun 2022 12:59:23 +0530
From: Alim Akhtar <alim.akhtar@...sung.com>
To: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-scsi@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: devicetree@...r.kernel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, vkoul@...nel.org,
avri.altman@....com, bvanassche@....org,
martin.petersen@...cle.com, chanho61.park@...sung.com,
pankaj.dubey@...sung.com, Alim Akhtar <alim.akhtar@...sung.com>
Subject: [PATCH v3 5/6] ufs: host: ufs-exynos: add mphy apb clock mask
Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.
Signed-off-by: Alim Akhtar <alim.akhtar@...sung.com>
Reviewed-by: Chanho Park <chanho61.park@...sung.com>
Tested-by: Chanho Park <chanho61.park@...sung.com>
---
drivers/ufs/host/ufs-exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..cc128aff8871 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
#define HCI_ERR_EN_DME_LAYER 0x88
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
+#define MPHY_APBCLK_STOP BIT(3)
#define REFCLK_STOP BIT(2)
#define UNIPRO_MCLK_STOP BIT(1)
#define UNIPRO_PCLK_STOP BIT(0)
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
- UNIPRO_MCLK_STOP |\
+ UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
--
2.25.1
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