linux-kernel - [irqchip: irq/irqchip-fixes] irqchip/loongson-liointc: Use architecture register to get coreid

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Message-ID: <165484829710.4207.11924416657167515441.tip-bot2@tip-bot2>
Date:   Fri, 10 Jun 2022 08:04:57 -0000
From:   "irqchip-bot for Jiaxun Yang" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Jiaxun Yang <jiaxun.yang@...goat.com>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-fixes] irqchip/loongson-liointc: Use
 architecture register to get coreid

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     6fac824f40987a54a08dfbcc36145869d02e45b1
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/6fac824f40987a54a08dfbcc36145869d02e45b1
Author:        Jiaxun Yang <jiaxun.yang@...goat.com>
AuthorDate:    Thu, 09 Jun 2022 18:52:41 +01:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Fri, 10 Jun 2022 08:57:19 +01:00

irqchip/loongson-liointc: Use architecture register to get coreid

fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.

Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.

Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20220609175242.977-1-jiaxun.yang@flygoat.com
---
 drivers/irqchip/irq-loongson-liointc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index aed8885..8d05d8b 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -39,6 +39,12 @@
 
 #define LIOINTC_ERRATA_IRQ	10
 
+#if defined(CONFIG_MIPS)
+#define liointc_core_id get_ebase_cpunum()
+#else
+#define liointc_core_id get_csr_cpuid()
+#endif
+
 struct liointc_handler_data {
 	struct liointc_priv	*priv;
 	u32			parent_int_map;
@@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
 	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct irq_chip_generic *gc = handler->priv->gc;
-	int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
+	int core = liointc_core_id % LIOINTC_NUM_CORES;
 	u32 pending;
 
 	chained_irq_enter(chip, desc);