lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <BY5PR02MB69470346E9E634F6C699FB95A5A69@BY5PR02MB6947.namprd02.prod.outlook.com>
Date:   Fri, 10 Jun 2022 08:47:41 +0000
From:   Bharat Kumar Gogada <bharatku@...inx.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Michal Simek <michals@...inx.com>,
        "robh@...nel.org" <robh@...nel.org>
Subject: RE: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
 Port

> 
> On Wed, Jun 08, 2022 at 10:10:46PM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additional register bit
> >   to enable and handle legacy interrupts.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
> > ---
> >  drivers/pci/controller/pcie-xilinx-cpm.c | 33
> > +++++++++++++++++++++++-
> >  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> Per MAINTAINERS, xilinx-cpm lacks a maintainer.  Can we get one?
> 
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index c7cd44ed4dfc..a3b04083b6b3 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -35,6 +35,10 @@
> >  #define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348
> >  #define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)
> >
> > +#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
> > +#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
> > +#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
> > +
> >  /* Interrupt registers definitions */
> >  #define XILINX_CPM_PCIE_INTR_LINK_DOWN		0
> >  #define XILINX_CPM_PCIE_INTR_HOT_RESET		3
> > @@ -109,6 +113,7 @@
> >   * @intx_irq: legacy interrupt number
> >   * @irq: Error interrupt number
> >   * @lock: lock protecting shared register access
> > + * @is_cpm5: value to check cpm version
> 
> s/cpm version/CPM version/ to match commit log usage.
> 
> > +	port->is_cpm5 = of_device_is_compatible(dev->of_node,
> > +						"xlnx,versal-cpm5-host");
> 
> One use of of_device_is_compatible() is OK, I guess, but
> of_device_get_match_data() is a better pattern if we ever need more.
> 
> I would lean toward of_device_get_match_data() even here, just to reduce
> the number of ways to identify device-specific things across drivers.
> 
Thanks Bjorn, will add this change in next patch.

Regards,
bharat

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ