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Message-ID: <2f386fc3-d496-62e3-20b0-ac962169e7a1@linaro.org>
Date: Fri, 10 Jun 2022 11:59:47 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Geert Uytterhoeven <geert@...ux-m68k.org>,
Tomer Maimon <tmaimon77@...il.com>
Cc: Avi Fishman <avifishman70@...il.com>,
Tali Perry <tali.perry1@...il.com>,
Joel Stanley <joel@....id.au>,
Patrick Venture <venture@...gle.com>,
Nancy Yuen <yuenn@...gle.com>,
Benjamin Fair <benjaminfair@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Greg KH <gregkh@...uxfoundation.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Arnd Bergmann <arnd@...db.de>,
Olof Johansson <olof@...om.net>,
Jiri Slaby <jirislaby@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
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Lubomir Rintel <lkundrak@...sk>,
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Subject: Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device
tree
On 10/06/2022 09:57, Geert Uytterhoeven wrote:
>> "+ cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + clocks = <&clk NPCM8XX_CLK_CPU>;
>> + reg = <0x0 0x0>;
>> Why do you have two address cells? A bit more complicated and not
>> necessary, I think."
>> the arm,cortex-a35 is 64 Bit this is why we use #address-cells = <2>;
>> and therefore reg = <0x0 0x0>;
>
> These addresses are not addresses on the main memory bus (which
> is indeed 64-bit), but on the logical CPU bus.
> Now, Documentation/devicetree/bindings/arm/cpus.yaml says you can
> have #address-cells = <2> if you have non-zero MPIDR_EL1 high bits.
>
Thanks Tomer and Geert for explanation. OK for me.
Best regards,
Krzysztof
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