linux-kernel - Re: [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs

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Message-ID: <2039a18c-5f4f-f33e-eed6-c89f4561af25@sholland.org>
Date:   Sun, 12 Jun 2022 14:18:24 -0500
From:   Samuel Holland <samuel@...lland.org>
To:     Heiko Stuebner <heiko@...ech.de>, palmer@...belt.com,
        paul.walmsley@...ive.com
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        wefu@...hat.com, guoren@...nel.org, cmuellner@...ux.com,
        philipp.tomsich@...ll.eu, hch@....de, atishp@...shpatra.org,
        anup@...infault.org, mick@....forth.gr, robh+dt@...nel.org,
        krzk+dt@...nel.org, devicetree@...r.kernel.org,
        drew@...gleboard.org
Subject: Re: [PATCH 3/3] riscv: implement cache-management errata for T-Head
 SoCs

On 6/9/22 7:43 PM, Heiko Stuebner wrote:
> The T-Head C906 and C910 implement a scheme for handling
> cache operations different from the generic Zicbom extension.
> 
> Add an errata for it next to the generic dma coherency ops.
> 
> Tested-by: Samuel Holland <samuel@...lland.org>

v3 breaks Ethernet on D1, because the packet tx buffers are not aligned to the
cache block size. See my comments on patch 2. With the changes suggested there,
all functionality is again working.

Please drop this tag until I have a chance to test the next version.

Regards,
Samuel