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Date: Mon, 13 Jun 2022 12:12:28 +0200 From: Greg Kroah-Hartman <gregkh@...uxfoundation.org> To: linux-kernel@...r.kernel.org Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, stable@...r.kernel.org, Johan Hovold <johan+linaro@...nel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, Bjorn Helgaas <bhelgaas@...gle.com>, Bjorn Andersson <bjorn.andersson@...aro.org> Subject: [PATCH 5.15 246/247] PCI: qcom: Fix pipe clock imbalance From: Johan Hovold <johan+linaro@...nel.org> commit fdf6a2f533115ec5d4d9629178f8196331f1ac50 upstream. Fix a clock imbalance introduced by ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller"), which enables the pipe clock both in init() and in post_init() but only disables in post_deinit(). Note that the pipe clock was also never disabled in the init() error paths and that enabling the clock before powering up the PHY looks questionable. Link: https://lore.kernel.org/r/20220401133351.10113-1-johan+linaro@kernel.org Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") Signed-off-by: Johan Hovold <johan+linaro@...nel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@....com> Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org> Cc: stable@...r.kernel.org # 5.6 Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ------ 1 file changed, 6 deletions(-) --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1203,12 +1203,6 @@ static int qcom_pcie_init_2_7_0(struct q goto err_disable_clocks; } - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - goto err_disable_clocks; - } - /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
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