linux-kernel - Re: [PATCH 2/5] dt-bindings: gpio: gpio-thunderx: Describe pin-cfg option

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 13 Jun 2022 01:04:52 -0700
From:   Piyush Malgujar <pmalgujar@...vell.com>
To:     Linus Walleij <linus.walleij@...aro.org>
CC:     <linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <brgl@...ev.pl>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <rric@...nel.org>, <cchavva@...vell.com>, <wsadowski@...vell.com>
Subject: Re: [PATCH 2/5] dt-bindings: gpio: gpio-thunderx: Describe pin-cfg
 option

On Fri, Jun 03, 2022 at 12:35:57PM +0200, Linus Walleij wrote:
> On Fri, Jun 3, 2022 at 11:06 AM Piyush Malgujar <pmalgujar@...vell.com> wrote:
> 
> > The purpose of this pin-cfg entry is different than the standard GPIO pin config usage.
> > It is to write a value to GPIO_BIT_CFG register which is used to configure fields like
> > pin function, selecting which signal is reported to GPIO output or which signal GPIO
> > input need to connect, filters, XOR and output mode.
> 
> Then implement pin control for this driver instead of inventing a custom hack?
> https://docs.kernel.org/driver-api/pin-control.html
> 
> Several drivers implement pin control with a GPIO front-end, for example:
> drivers/gpio/gpio-pl061.c is used as a front end with
> drivers/pinctrl/pinctrl-single.c
> 
> There are also composite drivers in drivers/pinctrl that implement both
> pincontrol (incl muxing) and GPIO, such as drivers/pinctrl/pinctrl-sx150x.c
> 
> Yours,
> Linus Walleij

Hi Linus,

Thanks for the reply.
But as in this case, we expect a 32 bit reg value via DTS for this driver
only from user with internal understanding of marvell soc and this reg bit
value can have many different combinations as the register fields can vary
for different marvell SoCs.
This patch just reads the reg value from DTS and writes it to the register.

Thanks,
Piyush