lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 13 Jun 2022 15:10:31 +0200 From: Wolfram Sang <wsa+renesas@...g-engineering.com> To: linux-renesas-soc@...r.kernel.org Cc: Linh Phung <linh.phung.jy@...esas.com>, Wolfram Sang <wsa+renesas@...g-engineering.com>, Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add HSCIF 0+1 nodes From: Linh Phung <linh.phung.jy@...esas.com> Extracted from a bigger patch in the BSP, rebased and DMA properties added. HSCIF0+1 work fine, HSCIF2+3 skipped because they haven't been tested yet. Signed-off-by: Linh Phung <linh.phung.jy@...esas.com> Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index d89064f86d85..ebc4a052207a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -271,6 +271,40 @@ i2c5: i2c@...e0000 { status = "disabled"; }; + hscif0: serial@...40000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@...50000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + scif3: serial@...50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; -- 2.35.1
Powered by blists - more mailing lists