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Message-ID: <1655108645-1517-2-git-send-email-quic_srivasam@quicinc.com>
Date: Mon, 13 Jun 2022 13:54:02 +0530
From: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
To: <agross@...nel.org>, <bjorn.andersson@...aro.org>,
<robh+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_rohkumar@...cinc.com>, <srinivas.kandagatla@...aro.org>,
<dianders@...omium.org>, <swboyd@...omium.org>,
<judyhsiao@...omium.org>
CC: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>,
"Venkata Prasad Potturu" <quic_potturu@...cinc.com>
Subject: [PATCH v15 1/4] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset
Add pinmux nodes for primary and secondary I2S for SC7280 based platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@...cinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@...cinc.com>
Reviewed-by: Matthias Kaehlcke <mka@...omium.org>
Reviewed-by: Stephen Boyd <swboyd@...omium.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 5eb6689..acf407a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -367,6 +367,20 @@
bias-disable;
};
+&mi2s1_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s1_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s1_ws {
+ drive-strength = <6>;
+};
+
&pm7325_gpios {
key_vol_up_default: key-vol-up-default {
pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67..fde55c3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3898,6 +3898,46 @@
function = "edp_hot";
};
+ mi2s0_data0: mi2s0-data0 {
+ pins = "gpio98";
+ function = "mi2s0_data0";
+ };
+
+ mi2s0_data1: mi2s0-data1 {
+ pins = "gpio99";
+ function = "mi2s0_data1";
+ };
+
+ mi2s0_mclk: mi2s0-mclk {
+ pins = "gpio96";
+ function = "pri_mi2s";
+ };
+
+ mi2s0_sclk: mi2s0-sclk {
+ pins = "gpio97";
+ function = "mi2s0_sck";
+ };
+
+ mi2s0_ws: mi2s0-ws {
+ pins = "gpio100";
+ function = "mi2s0_ws";
+ };
+
+ mi2s1_data0: mi2s1-data0 {
+ pins = "gpio107";
+ function = "mi2s1_data0";
+ };
+
+ mi2s1_sclk: mi2s1-sclk {
+ pins = "gpio106";
+ function = "mi2s1_sck";
+ };
+
+ mi2s1_ws: mi2s1-ws {
+ pins = "gpio108";
+ function = "mi2s1_ws";
+ };
+
pcie1_clkreq_n: pcie1-clkreq-n {
pins = "gpio79";
function = "pcie1_clkreqn";
--
2.7.4
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