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Message-ID: <165510894684.4207.9191600089709041341.tip-bot2@tip-bot2>
Date:   Mon, 13 Jun 2022 08:29:06 -0000
From:   "tip-bot2 for Like Xu" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Yongchao Duan <yongduan@...cent.com>, Like Xu <likexu@...cent.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] x86/events/intel/ds: Enable large PEBS for
 PERF_SAMPLE_WEIGHT_TYPE

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     e60b7cb089f216a26d478f5ad8f811a1de65f382
Gitweb:        https://git.kernel.org/tip/e60b7cb089f216a26d478f5ad8f811a1de65f382
Author:        Like Xu <likexu@...cent.com>
AuthorDate:    Thu, 19 May 2022 23:19:13 +08:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Mon, 13 Jun 2022 10:15:13 +02:00

x86/events/intel/ds: Enable large PEBS for PERF_SAMPLE_WEIGHT_TYPE

All the information required by the PERF_SAMPLE_WEIGHT is
available in the pebs record. Thus large PEBS could be enabled
for PERF_SAMPLE_WEIGHT sample type to save PMIs overhead until
other non-compatible flags such as PERF_SAMPLE_DATA_PAGE_SIZE
(due to lack of munmap tracking) stop it.

To cover new weight extension, add PERF_SAMPLE_WEIGHT_TYPE
to the guardian LARGE_PEBS_FLAGS.

Tested it with:

$ perf mem record -c 1000 workload
Before: Captured and wrote 0.126 MB perf.data (958 samples) [958 PMIs]
After: Captured and wrote 0.313 MB perf.data (4859 samples) [3 PMIs]

Reported-by: Yongchao Duan <yongduan@...cent.com>
Signed-off-by: Like Xu <likexu@...cent.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20220519151913.80545-1-likexu@tencent.com
---
 arch/x86/events/perf_event.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 21a5482..1ca6200 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -136,7 +136,8 @@ struct amd_nb {
 	PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
 	PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
 	PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
-	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
+	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
+	PERF_SAMPLE_WEIGHT_TYPE)
 
 #define PEBS_GP_REGS			\
 	((1ULL << PERF_REG_X86_AX)    | \

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