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Message-ID: <ecfa5816-1ada-5d8a-7189-c70e45a311ac@infradead.org>
Date:   Tue, 14 Jun 2022 07:50:42 -0700
From:   Randy Dunlap <rdunlap@...radead.org>
To:     Qin Jian <qinjian@...lus1.com>, sboyd@...nel.org
Cc:     krzysztof.kozlowski+dt@...aro.org, robh+dt@...nel.org,
        mturquette@...libre.com, linux@...linux.org.uk, arnd@...db.de,
        olof@...om.net, soc@...nel.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
        Philipp Zabel <p.zabel@...gutronix.de>
Subject: Re: [PATCH v18 03/10] reset: Add Sunplus SP7021 reset driver



On 6/14/22 01:31, Qin Jian wrote:
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index b496028b6..e6540036b 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -231,6 +231,15 @@ config RESET_STARFIVE_JH7100
>  	help
>  	  This enables the reset controller driver for the StarFive JH7100 SoC.
>  
> +config RESET_SUNPLUS
> +	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
> +	default ARCH_SUNPLUS
> +	help
> +	  This enables the reset driver support for Sunplus SoCs.
> +	  The reset lines that can be asserted and deasserted by toggling bits
> +	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
> +	  which means each register hold 16 reset lines.

	                            holds

-- 
~Randy

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