linux-kernel - RE: [Intel-wired-lan] [PATCH v2 2/2] igb: Make DMA faster when CPU is active on the PCIe link

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Message-ID: <BYAPR11MB336759CD46D7A1BD30A86BC9FCAA9@BYAPR11MB3367.namprd11.prod.outlook.com>
Date:   Tue, 14 Jun 2022 15:01:11 +0000
From:   "G, GurucharanX" <gurucharanx.g@...el.com>
To:     Kai-Heng Feng <kai.heng.feng@...onical.com>,
        "Brandeburg, Jesse" <jesse.brandeburg@...el.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Eric Dumazet" <edumazet@...gle.com>,
        "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>,
        Jeff Kirsher <jeffrey.t.kirsher@...el.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        "David S. Miller" <davem@...emloft.net>
Subject: RE: [Intel-wired-lan] [PATCH v2 2/2] igb: Make DMA faster when CPU is
 active on the PCIe link



> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of
> Kai-Heng Feng
> Sent: Wednesday, May 25, 2022 5:01 PM
> To: Brandeburg, Jesse <jesse.brandeburg@...el.com>; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>
> Cc: linux-kernel@...r.kernel.org; Eric Dumazet <edumazet@...gle.com>;
> Kai-Heng Feng <kai.heng.feng@...onical.com>; intel-wired-
> lan@...ts.osuosl.org; Jeff Kirsher <jeffrey.t.kirsher@...el.com>;
> netdev@...r.kernel.org; Jakub Kicinski <kuba@...nel.org>; Paolo Abeni
> <pabeni@...hat.com>; David S. Miller <davem@...emloft.net>
> Subject: [Intel-wired-lan] [PATCH v2 2/2] igb: Make DMA faster when CPU is
> active on the PCIe link
> 
> Intel I210 on some Intel Alder Lake platforms can only achieve ~750Mbps Tx
> speed via iperf. The RR2DCDELAY shows around 0x2xxx DMA delay, which
> will be significantly lower when 1) ASPM is disabled or 2) SoC package c-state
> stays above PC3. When the RR2DCDELAY is around 0x1xxx the Tx speed can
> reach to ~950Mbps.
> 
> According to the I210 datasheet "8.26.1 PCIe Misc. Register - PCIEMISC",
> "DMA Idle Indication" doesn't seem to tie to DMA coalesce anymore, so set it
> to 1b for "DMA is considered idle when there is no Rx or Tx AND when there
> are no TLPs indicating that CPU is active detected on the PCIe link (such as
> the host executes CSR or Configuration register read or write operation)" and
> performing Tx should also fall under "active CPU on PCIe link" case.
> 
> In addition to that, commit b6e0c419f040 ("igb: Move DMA Coalescing init
> code to separate function.") seems to wrongly changed from enabling
> E1000_PCIEMISC_LX_DECISION to disabling it, also fix that.
> 
> Fixes: b6e0c419f040 ("igb: Move DMA Coalescing init code to separate
> function.")
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@...onical.com>
> ---
>  drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 

Tested-by: Gurucharan <gurucharanx.g@...el.com> (A Contingent worker at Intel)