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Message-ID: <YqpdDeD5DA5byI0B@google.com>
Date:   Wed, 15 Jun 2022 23:28:29 +0100
From:   Lee Jones <lee.jones@...aro.org>
To:     Tinghan Shen <tinghan.shen@...iatek.com>
Cc:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Mathieu Poirier <mathieu.poirier@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Benson Leung <bleung@...omium.org>,
        Guenter Roeck <groeck@...omium.org>,
        Daisuke Nojiri <dnojiri@...omium.org>,
        Sebastian Reichel <sebastian.reichel@...labora.com>,
        "Dustin L. Howett" <dustin@...ett.net>,
        Tzung-Bi Shih <tzungbi@...nel.org>,
        "Gustavo A. R. Silva" <gustavoars@...nel.org>,
        Prashant Malani <pmalani@...omium.org>,
        Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        Brian Norris <briannorris@...omium.org>,
        linux-remoteproc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        chrome-platform@...ts.linux.dev,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        weishunc@...gle.com
Subject: Re: [PATCH v1 15/15] mfd: cros_ec: Add SCP core 1 as a new CrOS EC
 MCU

On Wed, 01 Jun 2022, Tinghan Shen wrote:

> MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU.
> Add a new cros feature id to represent the SCP 2nd core.
> 
> The 1st core is referred to as 'core 0', and the 2nd core is referred
> to as 'core 1'.
> 
> Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
> ---
>  drivers/mfd/cros_ec_dev.c                      | 5 +++++
>  include/linux/platform_data/cros_ec_commands.h | 2 ++
>  include/linux/platform_data/cros_ec_proto.h    | 1 +
>  3 files changed, 8 insertions(+)

Applied, thanks.

-- 
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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