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Message-ID: <20220615113218.5444-1-r-ravikumar@ti.com>
Date: Wed, 15 Jun 2022 17:02:18 +0530
From: Rahul T R <r-ravikumar@...com>
To: <dri-devel@...ts.freedesktop.org>
CC: <andrzej.hajda@...el.com>, <narmstrong@...libre.com>,
<robert.foss@...aro.org>, <jonas@...boo.se>,
<jernej.skrabec@...il.com>, <airlied@...ux.ie>, <daniel@...ll.ch>,
<p.zabel@...gutronix.de>, <tomi.valkeinen@...asonboard.com>,
<laurent.pinchart@...asonboard.com>,
<linux-kernel@...r.kernel.org>, <jpawar@...ence.com>,
<sjakhade@...ence.com>, <mparab@...ence.com>, <a-bhatia1@...com>,
Rahul T R <r-ravikumar@...com>
Subject: [PATCH] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on
j721e. Also set the DPI input to DPI0
Signed-off-by: Rahul T R <r-ravikumar@...com>
---
drivers/gpu/drm/bridge/Kconfig | 10 ++++++++++
drivers/gpu/drm/bridge/cdns-dsi.c | 24 ++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 8ffd601e68f9..72c4c962d752 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -26,6 +26,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DPI/DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DSI wrapper. This wrapper adds
+ support to select which DPI input to use for the bridge.
+endif
+
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cdns-dsi.c
index 20bece84ff8c..d6f99963b7e2 100644
--- a/drivers/gpu/drm/bridge/cdns-dsi.c
+++ b/drivers/gpu/drm/bridge/cdns-dsi.c
@@ -424,6 +424,16 @@
#define DSI_NULL_FRAME_OVERHEAD 6
#define DSI_EOT_PKT_SIZE 4
+#define DSI_WRAP_REVISION 0x0
+#define DSI_WRAP_DPI_CONTROL 0x4
+#define DSI_WRAP_DSC_CONTROL 0x8
+#define DSI_WRAP_DPI_SECURE 0xc
+#define DSI_WRAP_DSI_0_ASF_STATUS 0x10
+
+#define DSI_WRAP_DPI_0_EN BIT(0)
+#define DSI_WRAP_DSI2_MUX_SEL BIT(4)
+
+
struct cdns_dsi_output {
struct mipi_dsi_device *dev;
struct drm_panel *panel;
@@ -453,6 +463,9 @@ struct cdns_dsi_input {
struct cdns_dsi {
struct mipi_dsi_host base;
void __iomem *regs;
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+ void __iomem *wrap_regs;
+#endif
struct cdns_dsi_input input;
struct cdns_dsi_output output;
unsigned int direct_cmd_fifo_depth;
@@ -1212,6 +1225,12 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs))
return PTR_ERR(dsi->regs);
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+ dsi->wrap_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(dsi->wrap_regs))
+ return PTR_ERR(dsi->wrap_regs);
+#endif
+
dsi->dsi_p_clk = devm_clk_get(&pdev->dev, "dsi_p_clk");
if (IS_ERR(dsi->dsi_p_clk))
return PTR_ERR(dsi->dsi_p_clk);
@@ -1244,6 +1263,11 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+ /* Select DPI0 as input */
+ writel(DSI_WRAP_DPI_0_EN, dsi->wrap_regs + DSI_WRAP_DPI_CONTROL);
+#endif
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
--
2.36.1
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