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Date:   Wed, 15 Jun 2022 12:42:27 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <broonie@...nel.org>
CC:     <Daire.McNamara@...rochip.com>, <Lewis.Hanly@...rochip.com>,
        <linux-riscv@...ts.infradead.org>, <linux-spi@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <dan.carpenter@...cle.com>
Subject: Re: [PATCH] spi: microchip-core: fix passing zero to PTR_ERR warning

On 15/06/2022 13:37, Mark Brown wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Wed, Jun 15, 2022 at 11:57:37AM +0000, Conor.Dooley@...rochip.com wrote:
>> On 15/06/2022 12:40, Mark Brown wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>> On Wed, Jun 15, 2022 at 12:30:22PM +0100, Conor Dooley wrote:
> 
>>>> -             ret = PTR_ERR(spi->clk);
>>>> +             ret = !spi->clk ? -ENXIO : PTR_ERR(spi->clk);
> 
>>> I think you're looking for PTR_ERR_OR_ZERO() here?
> 
>> Maybe I don't understand, so let me explain what I think you're
>> suggesting & maybe you can correct me:
> 
>>> -             ret = PTR_ERR(spi->clk);
>>> +             ret = PTR_ERR_OR_ZERO(spi->clk);
> 
>> But if spi->clk is NULL, this will return 0 from the probe
>> rather than returning an error?
>> If that's not what you meant, lmk
> 
> Oh, hang on - what error conditions can clk_get() return 0 in?  The
> documentation doesn't mention any...

If !CONFIG_HAVE_CLK, (without which it won't boot on the coreplex)
but I don't think I can be sure that CONFIG_HAVE_CLK will /always/
be enabled for other uses of the FPGA.

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