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Message-ID: <20220616212813.GA3991754-robh@kernel.org>
Date: Thu, 16 Jun 2022 15:28:13 -0600
From: Rob Herring <robh@...nel.org>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>
Cc: chunkuang.hu@...nel.org, p.zabel@...gutronix.de, daniel@...ll.ch,
krzysztof.kozlowski+dt@...aro.org, mripard@...nel.org,
tzimmermann@...e.de, matthias.bgg@...il.com, deller@....de,
airlied@...ux.ie, msp@...libre.com, granquet@...libre.com,
jitao.shi@...iatek.com, wenst@...omium.org,
angelogioacchino.delregno@...labora.com, ck.hu@...iatek.com,
dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-fbdev@...r.kernel.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v11 01/10] dt-bindings: mediatek,dp: Add Display Port
binding
On Thu, Jun 16, 2022 at 09:22:16PM +0800, Rex-BC Chen wrote:
> On Tue, 2022-06-14 at 14:23 -0600, Rob Herring wrote:
> > On Fri, Jun 10, 2022 at 06:55:13PM +0800, Bo-Chen Chen wrote:
> > > From: Markus Schneider-Pargmann <msp@...libre.com>
> > >
> > > This controller is present on several mediatek hardware. Currently
> > > mt8195 and mt8395 have this controller without a functional
> > > difference,
> > > so only one compatible field is added.
> > >
> > > The controller can have two forms, as a normal display port and as
> > > an
> > > embedded display port.
> > >
> > > Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> > > Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> > > [Bo-Chen: Fix reviewers' comment]
> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> > > ---
> > > .../display/mediatek/mediatek,dp.yaml | 101
> > > ++++++++++++++++++
> > > 1 file changed, 101 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > > ml
> > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > > ml
> > > new file mode 100644
> > > index 000000000000..10f50a0dcf49
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya
> > > ml
> > > @@ -0,0 +1,101 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI45ipbhsw$
> > >
> > > +$schema:
> > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yqAl1KhfbHqHN7-5aeqhzqeOVhPU_Z5beko5q-y-s5pcfp1WL5oVGvY5UF4EfWm4PWjc5mjBwyBUMsr_RI5WzYKENQ$
> > >
> > > +
> > > +title: MediaTek Display Port Controller
> > > +
> > > +maintainers:
> > > + - Chun-Kuang Hu <chunkuang.hu@...nel.org>
> > > + - Jitao shi <jitao.shi@...iatek.com>
> > > +
> > > +description: |
> > > + Device tree bindings for the MediaTek display port and
> > > + embedded display port controller present on some MediaTek SoCs.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - mediatek,mt8195-dp-tx
> > > + - mediatek,mt8195-edp-tx
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + nvmem-cells:
> > > + maxItems: 1
> > > + description: efuse data for display port calibration
> > > +
> > > + nvmem-cell-names:
> > > + const: dp_calibration_data
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + ports:
> > > + $ref: /schemas/graph.yaml#/properties/ports
> > > + properties:
> > > + port@0:
> > > + $ref: /schemas/graph.yaml#/properties/port
> > > + description: Input endpoint of the controller, usually
> > > dp_intf
> > > +
> > > + port@1:
> > > + $ref: /schemas/graph.yaml#/properties/port
> > > + description: Output endpoint of the controller
> > > +
> > > + required:
> > > + - port@0
> > > + - port@1
> > > +
> > > + max-lanes:
> > > + maxItems: 1
> > > + description: maximum number of lanes supported by the
> > > hardware.
> >
> > We already have a 'data-lanes' property defined in
> > 'video-interfaces.yaml' that can serve this purpose.
> >
>
> Hello Rob,
>
> Thanks for review.
> From the description of video-interfaces.yaml, I think it's not quite
> match what we need. We only need this value be one of "1,2,4".
data-lanes = <0>;
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
Limiting the number of lanes to something less than the max is exactly
how this property is used in addition to being able to show the mapping
of lanes.
Rob
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