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Message-ID: <d99deddb-c4a9-d5a1-d0a6-0e7f94fbdd9a@gmail.com>
Date: Thu, 16 Jun 2022 14:57:53 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, yong.wu@...iatek.com
Cc: joro@...tes.org, will@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
iommu@...ts.linux-foundation.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
krzysztof.kozlowski@...aro.org, miles.chen@...iatek.com
Subject: Re: [PATCH v4 1/5] dt-bindings: iommu: mediatek: Add
mediatek,infracfg phandle
On 16/06/2022 13:08, AngeloGioacchino Del Regno wrote:
> Add property "mediatek,infracfg" to let the mtk_iommu driver retrieve
> a phandle to the infracfg syscon instead of performing a per-soc
> compatible lookup in the entire devicetree and set it as a required
> property for MT2712 and MT8173.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>
> ---
> .../bindings/iommu/mediatek,iommu.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index 2ae3bbad7f1a..fee0241b5098 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -101,6 +101,10 @@ properties:
> items:
> - const: bclk
>
> + mediatek,infracfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle to the mediatek infracfg syscon
> +
> mediatek,larbs:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> minItems: 1
> @@ -167,6 +171,18 @@ allOf:
> required:
> - power-domains
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt2712-m4u
> + - mediatek,mt8173-m4u
> +
> + then:
> + required:
> + - mediatek,infracfg
> +
> - if: # The IOMMUs don't have larbs.
> not:
> properties:
> @@ -191,6 +207,7 @@ examples:
> interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg CLK_INFRA_M4U>;
> clock-names = "bclk";
> + mediatek,infracfg = <&infracfg>;
> mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> <&larb3>, <&larb4>, <&larb5>;
> #iommu-cells = <1>;
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