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Date: Thu, 16 Jun 2022 19:47:35 +0530
From: Venkateshwar Rao Gannavarapu
<venkateshwar.rao.gannavarapu@...inx.com>
To: <laurent.pinchart@...asonboard.com>, <sam@...nborg.org>,
<dri-devel@...ts.freedesktop.org>
CC: <airlied@...ux.ie>, <daniel@...ll.ch>,
<linux-kernel@...r.kernel.org>, <vgannava@...inx.com>,
Venkateshwar Rao Gannavarapu
<venkateshwar.rao.gannavarapu@...inx.com>
Subject: [PATCH V2 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation
This patch adds dt binding for Xilinx DSI-TX subsystem.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with the programmable logic (FPGA).
Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@...inx.com>
---
.../bindings/display/xlnx/xlnx,dsi-tx.yaml | 101 +++++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
new file mode 100644
index 0000000..644934d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx DSI Transmitter subsystem Device Tree Bindings
+
+maintainers:
+ - Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@...inx.com>
+
+description: |
+ The Xilinx DSI Transmitter Subsystem implements the Mobile Industry
+ Processor Interface based display interface. It supports the interface
+ with the programmable logic (FPGA).
+
+ For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem.
+
+properties:
+ compatible:
+ const: xlnx,dsi-tx-v2.0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AXI Lite CPU clock
+ - description: D-PHY clock
+
+ clock-names:
+ items:
+ - const: s_axis_aclk
+ - const: dphy_clk_200M
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ This port should be the input endpoint.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ This port should be the output endpoint.
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi0: dsi_tx@...20000 {
+ compatible = "xlnx,dsi-tx-v2.0";
+ reg = <0x80020000 0x20000>;
+ clocks = <&misc_clk_0>, <&misc_clk_1>;
+ clock-names = "s_axis_aclk", "dphy_clk_200M";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mipi_dsi_in: endpoint {
+ remote-endpoint = <&pl_disp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "auo,b101uan01";
+ reg = <0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+ };
+
+...
--
1.8.3.1
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