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Message-ID: <4c801d6c6e9642d4f2d0b639cdd95718ea45df13.camel@mediatek.com>
Date: Fri, 17 Jun 2022 16:28:43 +0800
From: Rex-BC Chen <rex-bc.chen@...iatek.com>
To: CK Hu <ck.hu@...iatek.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"daniel@...ll.ch" <daniel@...ll.ch>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"mripard@...nel.org" <mripard@...nel.org>,
"tzimmermann@...e.de" <tzimmermann@...e.de>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"deller@....de" <deller@....de>,
"airlied@...ux.ie" <airlied@...ux.ie>
CC: "msp@...libre.com" <msp@...libre.com>,
"granquet@...libre.com" <granquet@...libre.com>,
Jitao Shi (石记涛)
<jitao.shi@...iatek.com>,
"wenst@...omium.org" <wenst@...omium.org>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-fbdev@...r.kernel.org" <linux-fbdev@...r.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort
driver
On Wed, 2022-06-15 at 13:50 +0800, CK Hu wrote:
> Hi, Bo-Chen:
>
> On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@...libre.com>
> >
> > This patch adds a embedded displayport driver for the MediaTek
> > mt8195
> > SoC.
> >
> > It supports the MT8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> >
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> >
> > This driver is based on an initial version by
> > Jitao shi <jitao.shi@...iatek.com>
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> > ---
>
> [snip]
>
> > +
> > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8
> > target_link_rate,
> > + u8 target_lane_count)
> > +{
> > + u8 lane_adjust[2] = {};
> > + bool pass_tps1 = false;
> > + bool pass_tps2_3 = false;
> > + int train_retries;
> > + int status_control;
> > + int iteration_count;
> > + int ret;
> > + u8 prev_lane_adjust;
> > +
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET,
> > target_link_rate);
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
> > + target_lane_count |
> > DP_LANE_COUNT_ENHANCED_FRAME_EN);
> > +
> > + if (mtk_dp->train_info.sink_ssc)
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,
> > + DP_SPREAD_AMP_0_5);
> > +
> > + train_retries = 0;
> > + status_control = 0;
> > + iteration_count = 1;
> > + prev_lane_adjust = 0xFF;
> > +
> > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2);
> > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate,
> > target_lane_count);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + dev_dbg(mtk_dp->dev,
> > + "Link train target_link_rate = 0x%x, target_lane_count
> > = 0x%x\n",
> > + target_link_rate, target_lane_count);
> > +
> > + do {
> > + train_retries++;
> > + if (!mtk_dp->train_info.cable_plugged_in ||
> > + mtk_dp->train_info.irq_sta.hpd_disconnect) {
> > + return -ENODEV;
> > + }
> > +
> > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING)
>
> This checking would never be true, so remove it.
>
Hello CK,
ok, I will do this.
> > + return -EAGAIN;
> > +
> > + if (!pass_tps1) {
> > + ret = mtk_dp_train_tps_1(mtk_dp,
> > target_lane_count,
> > + &iteration_count,
> > lane_adjust,
> > + &status_control,
> > + &prev_lane_adjust);
> > + if (!ret) {
> > + pass_tps1 = true;
> > + train_retries = 0;
> > + } else if (ret == -EINVAL) {
> > + break;
> > + }
> > + } else {
> > + ret = mtk_dp_train_tps_2_3(mtk_dp,
> > target_link_rate,
> > + target_lane_count,
> > + &iteration_count,
> > + lane_adjust,
> > &status_control,
> > + &prev_lane_adjust);
> > + if (!ret) {
> > + pass_tps2_3 = true;
> > + break;
> > + } else if (ret == -EINVAL) {
> > + break;
> > + }
> > + }
> > +
> > + drm_dp_dpcd_read(&mtk_dp->aux,
> > DP_ADJUST_REQUEST_LANE0_1,
> > + lane_adjust, sizeof(lane_adjust));
> > + mtk_dp_train_update_swing_pre(mtk_dp,
> > target_lane_count,
> > + lane_adjust);
> > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT &&
> > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS);
>
> mtk_dp_train_tps_1() & mtk_dp_train_tps_2_3() would only be called
> once
> and never be called twice, so remove this loop.
>
> Regards,
> CK
>
> > +
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
> > + DP_TRAINING_PATTERN_DISABLE);
> > + ret = mtk_dp_train_set_pattern(mtk_dp, 0);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + if (!pass_tps2_3)
> > + return -ETIMEDOUT;
> > +
> > + mtk_dp->train_info.link_rate = target_link_rate;
> > + mtk_dp->train_info.lane_count = target_lane_count;
> > +
> > + mtk_dp_training_set_scramble(mtk_dp, true);
> > +
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
> > + target_lane_count |
> > + DP_LANE_COUNT_ENHANCED_FRAME_EN);
> > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true);
> > +
> > + return ret;
> > +}
>
>
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