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Message-ID: <a3c480a3aa87b87c707b92bc80040764d2434a03.camel@mediatek.com>
Date:   Fri, 17 Jun 2022 18:10:42 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        "mturquette@...libre.com" <mturquette@...libre.com>
CC:     "sboyd@...nel.org" <sboyd@...nel.org>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "wenst@...omium.org" <wenst@...omium.org>,
        "Miles Chen (陳民樺)" 
        <Miles.Chen@...iatek.com>,
        "chun-jie.chen@...iatek.com" <chun-jie.chen@...iatek.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set
 rate on vdo1_dpintf's parent

On Fri, 2022-06-17 at 17:34 +0800, AngeloGioacchino Del Regno wrote:
> Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP),
> add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP)
> and also fix its parent clock name as it has to be "top_dp" for two
> reasons:
>  - This is its real parent!
>  - Likewise to eDP/VDO0 counterpart, we need clock source
>    selection on CLK_TOP_DP.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock
> support")
> 
Hello Angelo,

Thanks for this series.
I can use this series to do modetest using MT8195 Tomato Chromebook for
both dp and edp in kernel v5.19-rc1.

Therefore,
Tested-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
and,
Reviewed-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>

BRs,
Bo-Chen

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