linux-kernel - Re: [PATCH v2] ARM: dts: aspeed: Adding Facebook Yosemite V3.5 BMC

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Message-ID: <Yqyu+y9ms/DmFCbJ@heinlein.stwcx.org.github.beta.tailscale.net>
Date:   Fri, 17 Jun 2022 11:42:35 -0500
From:   Patrick Williams <patrick@...cx.xyz>
To:     Logananth Sundararaj <logananth13.hcl@...il.com>
Cc:     Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
        soc@...nel.org, Rob Herring <robh+dt@...nel.org>,
        Joel Stanley <joel@....id.au>,
        Andrew Jeffery <andrew@...id.au>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-aspeed@...ts.ozlabs.org,
        openbmc@...ts.ozlabs.org, garnermic@...il.com, thangavel.k@....com,
        naveen.mosess@....com
Subject: Re: [PATCH v2] ARM: dts: aspeed: Adding Facebook Yosemite V3.5 BMC

On Thu, Jun 16, 2022 at 05:37:07PM +0530, Logananth Sundararaj wrote:
> The Yosemite V3.5 is a facebook multi-node server
> platform that host four OCP server. The BMC
> in the Yosemite V3.5 platform based on AST2600 SoC.
> 
> This patch adds linux device tree entry related to
> Yosemite V3.5 specific devices connected to BMC SoC.
> 
> Signed-off-by: Logananth Sundararaj <logananth_s@....com>
> 
> ---
> --- v2 - Enabled i2c drivers.
> --- v1 - Initial draft.
> ---
>  arch/arm/boot/dts/Makefile                    |   1 +
>  .../boot/dts/aspeed-bmc-facebook-fby35.dts    | 277 ++++++++++++++++++
>  2 files changed, 278 insertions(+)
>  create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts

A few comments below.

...
> +&uart5 {
> +	status = "okay";
> +	/* Workaround for AST2600 A0 */
> +	compatible = "snps,dw-apb-uart";
> +};

Is this comment accurate?  Are we using A0 hardware on this system?

> +&fmc {
> +	status = "okay";
> +	reg = <0x1e620000 0xc4>, <0x20000000 0x8000000>;
> +	flash@0 {
> +		status = "okay";
> +		m25p,fast-read;
> +		label = "spi0.1";
> +		spi-max-frequency = <50000000>;
> +		spi-tx-bus-width = <2>;
> +		spi-rx-bus-width = <2>;
> +		#include "openbmc-flash-layout-64.dtsi"
> +	};
> +};

Aren't there two SPI flashes?  It seems like it based on:
https://github.com/facebook/openbmc-linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts#L162

> +
> +&spi1 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_spi1_default>;
> +
> +	flash@0 {
> +		status = "okay";
> +		m25p,fast-read;
> +		label = "pnor";
> +		spi-rx-bus-width = <4>;
> +		spi-max-frequency = <100000000>;
> +	};
> +};

What is SPI1 used for?  I don't see it in the facebook/openbmc-linux
DTS.

> -- 
> 2.17.1
> 

Are we missing the pwm/tach support?  Or is that still not upstream from
Aspeed?

-- 
Patrick Williams

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