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Date: Sun, 19 Jun 2022 22:32:10 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: palmer@...belt.com, paul.walmsley@...ive.com
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
wefu@...hat.com, guoren@...nel.org, cmuellner@...ux.com,
philipp.tomsich@...ll.eu, hch@....de, samuel@...lland.org,
atishp@...shpatra.org, anup@...infault.org, mick@....forth.gr,
robh+dt@...nel.org, krzk+dt@...nel.org, devicetree@...r.kernel.org,
drew@...gleboard.org, rdunlap@...radead.org,
Heiko Stuebner <heiko@...ech.de>, Rob Herring <robh@...nel.org>
Subject: [PATCH 2/4] dt-bindings: riscv: document cbom-block-size
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.
So add the necessary property for the system to know the core's
block-size.
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Reviewed-by: Anup Patel <anup@...infault.org>
Acked-by: Rob Herring <robh@...nel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..873dd12f6e89 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
+ riscv,cbom-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbom cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.35.1
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