lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220621180749.GA22098@francesco-nb.int.toradex.com>
Date:   Tue, 21 Jun 2022 20:07:49 +0200
From:   Francesco Dolcini <francesco.dolcini@...adex.com>
To:     Shawn Guo <shawnguo@...nel.org>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Andrejs Cainikovs <andrejs.cainikovs@...adex.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Marcel Ziswiler <marcel.ziswiler@...adex.com>,
        Francesco Dolcini <francesco.dolcini@...adex.com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8mm-verdin: update CAN clock to 40MHz

Hello Shawn, just a ping on this.

Francesco

On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote:
> Update SPI CAN controller clock to match current hardware design.
> 
> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@...adex.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 0d84d29e70f1..d309bc0ab8f6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -32,10 +32,10 @@ backlight: backlight {
>  	};
>  
>  	/* Fixed clock dedicated to SPI CAN controller */
> -	clk20m: oscillator {
> +	clk40m: oscillator {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> -		clock-frequency = <20000000>;
> +		clock-frequency = <40000000>;
>  	};
>  
>  	gpio-keys {
> @@ -194,7 +194,7 @@ &ecspi3 {
>  
>  	can1: can@0 {
>  		compatible = "microchip,mcp251xfd";
> -		clocks = <&clk20m>;
> +		clocks = <&clk40m>;
>  		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_can1_int>;
> -- 
> 2.34.1
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ