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Message-ID: <72f2458be7440100d1309c72d5e51e14bc2e5436.camel@mediatek.com>
Date: Tue, 21 Jun 2022 15:30:07 +0800
From: CK Hu <ck.hu@...iatek.com>
To: Bo-Chen Chen <rex-bc.chen@...iatek.com>, <chunkuang.hu@...nel.org>,
<p.zabel@...gutronix.de>, <daniel@...ll.ch>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <mripard@...nel.org>,
<tzimmermann@...e.de>, <matthias.bgg@...il.com>, <deller@....de>,
<airlied@...ux.ie>
CC: <msp@...libre.com>, <granquet@...libre.com>,
<jitao.shi@...iatek.com>, <wenst@...omium.org>,
<angelogioacchino.delregno@...labora.com>,
<dri-devel@...ts.freedesktop.org>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-fbdev@...r.kernel.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort
driver
Hi, Bo-Chen:
On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@...libre.com>
>
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
>
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
>
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
>
> This driver is based on an initial version by
> Jitao shi <jitao.shi@...iatek.com>
>
> Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> ---
[snip]
> +
> +/* multiple of 0.27Gbps */
> +enum mtk_dp_linkrate {
> + MTK_DP_LINKRATE_RBR = 0x6,
> + MTK_DP_LINKRATE_HBR = 0xA,
> + MTK_DP_LINKRATE_HBR2 = 0x14,
> + MTK_DP_LINKRATE_HBR25 = 0x19,
> + MTK_DP_LINKRATE_HBR3 = 0x1E,
> +};
Use the definition in drm_dp.h:
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
# define DP_LINK_BW_1_62 0x06
# define DP_LINK_BW_2_7 0x0a
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
# define DP_LINK_BW_8_1 0x1e /* 1.4 */
# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b
Link Layer */
# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b
Link Layer */
# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b
Link Layer */
Regards,
CK
>
>
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