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Message-ID: <20220622154920.95075-7-chenzhongjin@huawei.com>
Date: Wed, 22 Jun 2022 23:48:53 +0800
From: Chen Zhongjin <chenzhongjin@...wei.com>
To: <linux-kernel@...r.kernel.org>, <linux-arch@...r.kernel.org>,
<linuxppc-dev@...ts.ozlabs.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kbuild@...r.kernel.org>, <live-patching@...r.kernel.org>
CC: <jpoimboe@...nel.org>, <peterz@...radead.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<masahiroy@...nel.org>, <michal.lkml@...kovi.net>,
<ndesaulniers@...gle.com>, <mark.rutland@....com>,
<pasha.tatashin@...een.com>, <broonie@...nel.org>,
<chenzhongjin@...wei.com>, <rmk+kernel@...linux.org.uk>,
<madvenka@...ux.microsoft.com>, <christophe.leroy@...roup.eu>
Subject: [PATCH v5 06/33] objtool: arm64: Decode load/store instructions
Decode load/store operations and create corresponding stack_ops for
operations targeting SP or FP.
Operations storing/loading multiple registers are split into separate
stack_ops storing single registers.
Operations modifying the base register get an additional stack_op
for the register update. Since the atomic register(s) load/store + base
register update gets split into multiple operations, to make sure
objtool always sees a valid stack, consider store instruction to perform
stack allocations (i.e. modifying the base pointer before the storing)
and loads de-allocations (i.e. modifying the base pointer after the
load).
Signed-off-by: Julien Thierry <jthierry@...hat.com>
Signed-off-by: Chen Zhongjin <chenzhongjin@...wei.com>
---
tools/objtool/arch/arm64/decode.c | 113 ++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 19840862f3aa..c8d50d041889 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -132,6 +132,114 @@ static inline void make_add_op(enum aarch64_insn_register dest,
op->src.offset = val;
}
+static inline void make_store_op(enum aarch64_insn_register base,
+ enum aarch64_insn_register reg,
+ int offset, struct stack_op *op)
+{
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = base;
+ op->dest.offset = offset;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = reg;
+ op->src.offset = 0;
+}
+
+static inline void make_load_op(enum aarch64_insn_register base,
+ enum aarch64_insn_register reg,
+ int offset, struct stack_op *op)
+{
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = reg;
+ op->dest.offset = 0;
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = base;
+ op->src.offset = offset;
+}
+
+static inline bool aarch64_insn_is_ldst_pre(u32 insn)
+{
+ return aarch64_insn_is_store_pre(insn) ||
+ aarch64_insn_is_load_pre(insn) ||
+ aarch64_insn_is_stp_pre(insn) ||
+ aarch64_insn_is_ldp_pre(insn);
+}
+
+static inline bool aarch64_insn_is_ldst_post(u32 insn)
+{
+ return aarch64_insn_is_store_post(insn) ||
+ aarch64_insn_is_load_post(insn) ||
+ aarch64_insn_is_stp_post(insn) ||
+ aarch64_insn_is_ldp_post(insn);
+}
+
+static int decode_load_store(u32 insn, unsigned long *immediate,
+ struct list_head *ops_list)
+{
+ enum aarch64_insn_register base;
+ enum aarch64_insn_register rt;
+ struct stack_op *op;
+ int size;
+ int offset;
+
+ if (aarch64_insn_is_store_single(insn) ||
+ aarch64_insn_is_load_single(insn))
+ size = 1 << ((insn & GENMASK(31, 30)) >> 30);
+ else
+ size = 4 << ((insn >> 31) & 1);
+
+ if (aarch64_insn_is_store_pair(insn) ||
+ aarch64_insn_is_load_pair(insn))
+ *immediate = size * sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_7,
+ insn), 7);
+ else if (aarch64_insn_is_store_imm(insn) ||
+ aarch64_insn_is_load_imm(insn))
+ *immediate = size * aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, insn);
+ else /* load/store_pre/post */
+ *immediate = sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_9,
+ insn), 9);
+
+ base = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
+ if (!is_SPFP(base))
+ return 0;
+
+ if (aarch64_insn_is_ldst_post(insn))
+ offset = 0;
+ else
+ offset = *immediate;
+
+ /* First register */
+ rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
+ ADD_OP(op) {
+ if (aarch64_insn_is_store_single(insn) ||
+ aarch64_insn_is_store_pair(insn))
+ make_store_op(base, rt, offset, op);
+ else
+ make_load_op(base, rt, offset, op);
+ }
+
+ /* Second register (if present) */
+ if (aarch64_insn_is_store_pair(insn) ||
+ aarch64_insn_is_load_pair(insn)) {
+ rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2,
+ insn);
+ ADD_OP(op) {
+ if (aarch64_insn_is_store_pair(insn))
+ make_store_op(base, rt, offset + size, op);
+ else
+ make_load_op(base, rt, offset + size, op);
+ }
+ }
+
+ if (aarch64_insn_is_ldst_pre(insn) ||
+ aarch64_insn_is_ldst_post(insn)) {
+ ADD_OP(op) {
+ make_add_op(base, base, *immediate, op);
+ }
+ }
+
+ return 0;
+}
+
static void decode_add_sub_imm(u32 instr, bool set_flags,
unsigned long *immediate,
struct stack_op *op)
@@ -241,6 +349,11 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec
*immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn);
}
break;
+ case AARCH64_INSN_CLS_LDST:
+ {
+ return decode_load_store(insn, immediate, ops_list);
+ }
default:
break;
}
--
2.17.1
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