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Date:   Wed, 22 Jun 2022 23:58:23 +0100
From:   Conor Dooley <mail@...chuod.ie>
To:     palmer@...osinc.com, palmer@...belt.com
Cc:     Conor.Dooley@...rochip.com, Cyril.Jean@...rochip.com,
        Daire.McNamara@...rochip.com, Lewis.Hanly@...rochip.com,
        aou@...s.berkeley.edu, arnd@...db.de, gregkh@...uxfoundation.org,
        herbert@...dor.apana.org.au, kw@...ux.com,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org, linux-riscv@...ts.infradead.org,
        lorenzo.pieralisi@....com, mturquette@...libre.com,
        paul.walmsley@...ive.com, robh@...nel.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Stephen Boyd <sboyd@...nel.org>
Subject: [RESEND PATCH v4] MAINTAINERS: add polarfire rng, pci and clock drivers

From: Conor Dooley <conor.dooley@...rochip.com>

Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.

Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>
Acked-by: Stephen Boyd <sboyd@...nel.org>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 MAINTAINERS | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..01a7bfa49bdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17136,12 +17136,15 @@ N:	riscv
 K:	riscv
 
 RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
-M:	Lewis Hanly <lewis.hanly@...rochip.com>
 M:	Conor Dooley <conor.dooley@...rochip.com>
+M:	Daire McNamara <daire.mcnamara@...rochip.com>
 L:	linux-riscv@...ts.infradead.org
 S:	Supported
 F:	arch/riscv/boot/dts/microchip/
+F:	drivers/char/hw_random/mpfs-rng.c
+F:	drivers/clk/microchip/clk-mpfs.c
 F:	drivers/mailbox/mailbox-mpfs.c
+F:	drivers/pci/controller/pcie-microchip-host.c
 F:	drivers/soc/microchip/
 F:	include/soc/microchip/mpfs.h
 
-- 
2.36.1

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