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Message-Id: <20220622061410.853301-12-peng.fan@oss.nxp.com>
Date: Wed, 22 Jun 2022 14:14:07 +0800
From: "Peng Fan (OSS)" <peng.fan@....nxp.com>
To: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
shawnguo@...nel.org, s.hauer@...gutronix.de
Cc: festevam@...il.com, linux-imx@....com, hvilleneuve@...onoff.com,
l.stach@...gutronix.de, abbaraju.manojsai@...rulasolutions.com,
jagan@...rulasolutions.com, matteo.lisi@...icam.com,
tharvey@...eworks.com, t.remmet@...tec.de,
u.kleine-koenig@...gutronix.de, t.remmet@...tec.deh,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Peng Fan <peng.fan@....com>
Subject: [PATCH 11/14] arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings
From: Peng Fan <peng.fan@....com>
BIT3 and BIT0 are reserved bits, should not touch.
Fixes: 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Peng Fan <peng.fan@....com>
---
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 984a6b9ded8d..e34076954897 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -156,8 +156,8 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
--
2.25.1
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