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Message-ID: <f8b71e08-7f40-0438-1d07-ec637cf9552f@somainline.org>
Date: Wed, 22 Jun 2022 12:23:26 +0200
From: Konrad Dybcio <konrad.dybcio@...ainline.org>
To: Robert Foss <robert.foss@...aro.org>, bjorn.andersson@...aro.org,
agross@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
robh+dt@...nel.org, krzk+dt@...nel.org, jonathan@...ek.ca,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v6 6/6] arm64: dts: qcom: sm8350: Add DISPCC node
On 22.06.2022 01:34, Robert Foss wrote:
> Add the dispcc clock-controller DT node for sm8350.
>
> Signed-off-by: Robert Foss <robert.foss@...aro.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
Konrad
>
> Changes since v2
> - Remove interconnect include - Bjorn
>
> Changes since v3
> - Switch from .fw_name to .index
>
> Changes since v5
> - Revert .fw_name to .index change
>
>
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 52428b6df64e..99464cd1299e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> @@ -2525,6 +2526,31 @@ usb_2_dwc3: usb@...0000 {
> };
> };
>
> + dispcc: clock-controller@...0000 {
> + compatible = "qcom,sm8350-dispcc";
> + reg = <0 0x0af00000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_byteclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + power-domains = <&rpmhpd SM8350_MMCX>;
> + power-domain-names = "mmcx";
> + };
> +
> adsp: remoteproc@...00000 {
> compatible = "qcom,sm8350-adsp-pas";
> reg = <0 0x17300000 0 0x100>;
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