linux-kernel - [PATCH v6 08/33] objtool: arm64: Accept non-instruction data in code sections

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Message-ID: <20220623014917.199563-9-chenzhongjin@huawei.com>
Date:   Thu, 23 Jun 2022 09:48:52 +0800
From:   Chen Zhongjin <chenzhongjin@...wei.com>
To:     <linux-kernel@...r.kernel.org>, <linux-arch@...r.kernel.org>,
        <linuxppc-dev@...ts.ozlabs.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kbuild@...r.kernel.org>, <live-patching@...r.kernel.org>
CC:     <jpoimboe@...nel.org>, <peterz@...radead.org>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <masahiroy@...nel.org>, <michal.lkml@...kovi.net>,
        <ndesaulniers@...gle.com>, <mark.rutland@....com>,
        <pasha.tatashin@...een.com>, <broonie@...nel.org>,
        <chenzhongjin@...wei.com>, <rmk+kernel@...linux.org.uk>,
        <madvenka@...ux.microsoft.com>, <christophe.leroy@...roup.eu>,
        <daniel.thompson@...aro.org>
Subject: [PATCH v6 08/33] objtool: arm64: Accept non-instruction data in code sections

The compiler can generate some '0x0' words in code sections to pad the
end of functions. Also some pesudo-instructions can generate data in
code sections. Mark them as INSN_NOP.

If there are other undecoded instructions, just record and remove them
from validation list.

These doesn't influence check and orc generation because these undecoded
instructions also won't be excuted.

Signed-off-by: Chen Zhongjin <chenzhongjin@...wei.com>
---
 tools/objtool/arch/arm64/decode.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 30300d05c8f3..771d37d872c8 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -347,8 +347,14 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec
 
 	switch (aarch64_get_insn_class(insn)) {
 	case AARCH64_INSN_CLS_UNKNOWN:
-		WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
-		return -1;
+		if (insn == 0x0) {
+			*type = INSN_NOP;
+		} else {
+			WARN("undecoded insn at %s:0x%lx", sec->name, offset);
+			return record_invalid_insn(sec, offset);
+		}
+
+		break;
 	case AARCH64_INSN_CLS_DP_IMM:
 		/* Mov register to and from SP are aliases of add_imm */
 		if (aarch64_insn_is_add_imm(insn) ||
-- 
2.17.1