linux-kernel - Re: [PATCH 1/3] phy: qcom-qmp: clean up v4 and v5 define order

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Message-ID: <80da3045-5351-5d21-ffb2-e514e0b25961@linaro.org>
Date:   Thu, 23 Jun 2022 14:49:39 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Johan Hovold <johan+linaro@...nel.org>,
        Vinod Koul <vkoul@...nel.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] phy: qcom-qmp: clean up v4 and v5 define order

On 09/06/2022 15:03, Johan Hovold wrote:
> Clean up the QMP v4 and v5 defines by moving a few entries that were out
> of order.
> 
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

> ---
>   drivers/phy/qualcomm/phy-qcom-qmp.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index eb5705d1e32c..626be0ccede2 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -577,8 +577,8 @@
>   #define QSERDES_V4_COM_LOCK_CMP1_MODE0			0x0ac
>   #define QSERDES_V4_COM_LOCK_CMP2_MODE0			0x0b0
>   #define QSERDES_V4_COM_LOCK_CMP1_MODE1			0x0b4
> -#define QSERDES_V4_COM_DEC_START_MODE0			0x0bc
>   #define QSERDES_V4_COM_LOCK_CMP2_MODE1			0x0b8
> +#define QSERDES_V4_COM_DEC_START_MODE0			0x0bc
>   #define QSERDES_V4_COM_DEC_START_MODE1			0x0c4
>   #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0		0x0cc
>   #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0		0x0d0
> @@ -1106,8 +1106,8 @@
>   #define QSERDES_V5_COM_LOCK_CMP1_MODE0			0x0ac
>   #define QSERDES_V5_COM_LOCK_CMP2_MODE0			0x0b0
>   #define QSERDES_V5_COM_LOCK_CMP1_MODE1			0x0b4
> -#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc
>   #define QSERDES_V5_COM_LOCK_CMP2_MODE1			0x0b8
> +#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc
>   #define QSERDES_V5_COM_DEC_START_MODE1			0x0c4
>   #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0		0x0cc
>   #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0		0x0d0
> @@ -1134,8 +1134,8 @@
>   #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
>   #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
>   #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> -#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
>   #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
>   
>   /* Only for QMP V5 PHY - TX registers */
>   #define QSERDES_V5_TX_RES_CODE_LANE_TX			0x34


-- 
With best wishes
Dmitry