[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <1655950142-2026-2-git-send-email-hayashi.kunihiko@socionext.com>
Date: Thu, 23 Jun 2022 11:09:01 +0900
From: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
To: Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Masami Hiramatsu <mhiramat@...nel.org>, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
Subject: [PATCH v4 1/2] dt-bindings: PCI: designware-ep: Increase maxItems of reg and reg-names
UniPhier PCIe EP controller has up to 5 register mappings (dbi, dbi2, link,
addr_space and atu), so maxItems of "reg" and "reg-names" should allow 5.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
Acked-by: Rob Herring <robh@...nel.org>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index b78535040f04..f9390d729958 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -28,11 +28,11 @@ properties:
versions.
For designware core version >= 4.80, it may contain ATU address space.
minItems: 2
- maxItems: 4
+ maxItems: 5
reg-names:
minItems: 2
- maxItems: 4
+ maxItems: 5
items:
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
--
2.25.1
Powered by blists - more mailing lists