linux-kernel - Re: [RFC PATCH v2] riscv: Add Zawrs support for spinlocks

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Message-ID: <CAEg0e7g2jfT1X0pMo8oNaaeQ5B6d=qJe-YK0r8vrDzbFYE_ARQ@mail.gmail.com>
Date:   Fri, 24 Jun 2022 09:33:15 +0200
From:   Christoph Müllner <christoph.muellner@...ll.eu>
To:     Heiko Stübner <heiko@...ech.de>
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Aaron Durbin <adurbin@...osinc.com>,
        Randy Dunlap <rdunlap@...radead.org>,
        Atish Patra <atishp@...shpatra.org>
Subject: Re: [RFC PATCH v2] riscv: Add Zawrs support for spinlocks

On Thu, Jun 23, 2022 at 6:32 PM Heiko Stübner <heiko@...ech.de> wrote:
>
> Hi Christoph,
>
> Am Donnerstag, 23. Juni 2022, 17:29:48 CEST schrieb Christoph Muellner:
> > From: Christoph Müllner <christoph.muellner@...ll.eu>
> >
> > The current RISC-V code uses the generic ticket lock implementation,
> > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire().
> > Currently, RISC-V uses the generic implementation of these macros.
> > This patch introduces a RISC-V specific implementation, of these
> > macros, that peels off the first loop iteration and modifies the waiting
> > loop such, that it is possible to use the WRS.STO instruction of the Zawrs
> > ISA extension to stall the CPU.
> >
> > The resulting implementation of smp_cond_load_*() will only work for
> > 32-bit or 64-bit types for RV64 and 32-bit types for RV32.
> > This is caused by the restrictions of the LR instruction (RISC-V only
> > has LR.W and LR.D). Compiler assertions guard this new restriction.
> >
> > This patch uses the existing RISC-V ISA extension framework
> > to detect the presents of Zawrs at run-time.
> > If available a NOP instruction will be replaced by WRS.NTO or WRS.STO.
> >
> > The whole mechanism is gated by Kconfig setting, which defaults to Y.
> >
> > The Zawrs specification can be found here:
> > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
> >
> > Note, that the Zawrs extension is not frozen or ratified yet.
> > Therefore this patch is an RFC and not intended to get merged.
> >
> > Changes since v1:
> > * Adding "depends on !XIP_KERNEL" to RISCV_ISA_ZAWRS
> > * Fixing type checking code in __smp_load_reserved*
> > * Adjustments according to the specification change
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@...ll.eu>
>
> With the matching Qemu-Patch on
> - rv64 + Debian rootfs
> - rv32 + 32bit-Buildroot rootfs
>
> Tested-by: Heiko Stuebner <heiko@...ech.de>
>
> apart from the one nit below
> Reviewed-by: Heiko Stuebner <heiko@...ech.de>
>
> > ---
> >  arch/riscv/Kconfig                   | 11 ++++
> >  arch/riscv/include/asm/barrier.h     | 92 ++++++++++++++++++++++++++++
> >  arch/riscv/include/asm/errata_list.h | 19 +++++-
> >  arch/riscv/include/asm/hwcap.h       |  3 +-
> >  arch/riscv/kernel/cpu.c              |  1 +
> >  arch/riscv/kernel/cpufeature.c       | 13 ++++
> >  6 files changed, 136 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 32ffef9f6e5b..9d40569237c9 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -358,6 +358,17 @@ config RISCV_ISA_C
> >
> >          If you don't know what to do here, say Y.
> >
> > +config RISCV_ISA_ZAWRS
> > +     bool "Zawrs extension support"
> > +     depends on !XIP_KERNEL
> > +     select RISCV_ALTERNATIVE
> > +     default y
> > +     help
> > +        Adds support to dynamically detect the presence of the Zawrs extension
> > +        (wait for reservation set) and enable its usage.
> > +
> > +        If you don't know what to do here, say Y.
> > +
> >  config RISCV_ISA_SVPBMT
> >       bool "SVPBMT extension support"
> >       depends on 64BIT && MMU
> > diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
> > index d0e24aaa2aa0..1f9628aaa7cb 100644
> > --- a/arch/riscv/include/asm/barrier.h
> > +++ b/arch/riscv/include/asm/barrier.h
> > @@ -12,6 +12,8 @@
> >
> >  #ifndef __ASSEMBLY__
> >
> > +#include <asm/errata_list.h>
> > +
> >  #define nop()                __asm__ __volatile__ ("nop")
> >
> >  #define RISCV_FENCE(p, s) \
> > @@ -42,6 +44,64 @@ do {                                                                       \
> >       ___p1;                                                          \
> >  })
> >
> > +#if __riscv_xlen == 64
> > +
>
> nit: I guess we could do without the extra blanks?
> asm.h does so, and also the #else block below also doesn't
> use them ;-) . But I guess that is more a style debate

Ok, will remove the empty lines in a new revision.

Thanks!


>
> > +#define __riscv_lrsc_word(t)                                         \
> > +     (sizeof(t) == sizeof(int) ||                                    \
> > +      sizeof(t) == sizeof(long))
> > +
> > +#elif __riscv_xlen == 32
> > +
> > +#define __riscv_lrsc_word(t)                                         \
> > +     (sizeof(t) == sizeof(int))
> > +
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif /* __riscv_xlen */
>
> [...]
>
> Thanks
> Heiko
>
>