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Message-ID: <59ab9423-c0ea-ae5e-2f2e-c2f06c881559@quicinc.com>
Date: Fri, 24 Jun 2022 13:32:27 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: <helgaas@...nel.org>
CC: <linux-pci@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_vbadigan@...cinc.com>,
<quic_hemantk@...cinc.com>, <quic_nitegupt@...cinc.com>,
<quic_skananth@...cinc.com>, <quic_ramkri@...cinc.com>,
<manivannan.sadhasivam@...aro.org>, <swboyd@...omium.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
"Stanimir Varbanov" <svarbanov@...sol.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v2] PCI: qcom: Allow L1 and its sub states
A gentle remainder.
On 6/15/2022 6:45 PM, Krishna chaitanya chundru wrote:
> Allow L1 and its sub-states in the qcom pcie driver.
> By default this is disabled in the hardware. So enabling it explicitly.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 6ab9089..0d8efcc 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -41,6 +41,9 @@
> #define L23_CLK_RMV_DIS BIT(2)
> #define L1_CLK_RMV_DIS BIT(1)
>
> +#define PCIE20_PARF_PM_CTRL 0x20
> +#define REQ_NOT_ENTR_L1 BIT(5)
> +
> #define PCIE20_PARF_PHY_CTRL 0x40
> #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
> #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
> @@ -1267,6 +1270,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> val |= BIT(4);
> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>
> + /* Enable L1 and L1ss */
> + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
> + val &= ~REQ_NOT_ENTR_L1;
> + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
> +
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> val |= BIT(31);
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