linux-kernel - [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 24 Jun 2022 19:00:50 +0300
From:   Nikita Shubin <nikita.shubin@...uefel.me>
To:     Atish Patra <atishp@...shpatra.org>,
        Anup Patel <anup@...infault.org>
Cc:     João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>, linux@...ro.com,
        Nikita Shubin <n.shubin@...ro.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Ingo Molnar <mingo@...hat.com>, Jiri Olsa <jolsa@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, linux-riscv@...ts.infradead.org,
        Mark Rutland <mark.rutland@....com>,
        Namhyung Kim <namhyung@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Will Deacon <will@...nel.org>
Subject: [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU

From: Nikita Shubin <n.shubin@...ro.com>

This series aims to provide matching vendor SoC with corresponded JSON bindings.

The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example 
for Sifive Unmatched the corresponding string will be:

0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core

Where MIMPID can vary as all impl supported the same number of events, this might not 
be true for all future SoC however.

Also added 3 counters which are standart for all RISC-V implementations and SBI firmware 
events prerry names, as any firmware that supports SBI PMU should also support firmare 
events.

Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Link: https://patchwork.kernel.org/project/linux-riscv/list/?series=648017
---
v3->v4:
- drop pmuid in riscv_pmu_sbi, we are using /proc/cpuinfo
- rework util/header.c to use /proc/cpuinfo
- add SBI firmware events
- add firmware and std arch events to U74 pmu bindings
- change U74 id string and description in mapfile.csv
---
Nikita Shubin (5):
  drivers/perf: riscv_pmu_sbi: perf format
  perf tools riscv: Add support for get_cpuid_str function
  perf arch events: riscv arch std event files
  perf arch events: riscv sbi firmare std event files
  perf vendor events riscv: add Sifive U74 JSON file

 drivers/perf/riscv_pmu_sbi.c                  |  20 +++
 tools/perf/arch/riscv/util/Build              |   1 +
 tools/perf/arch/riscv/util/header.c           | 109 ++++++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  17 +++
 .../pmu-events/arch/riscv/riscv-generic.json  |  20 +++
 .../arch/riscv/riscv-sbi-firmware.json        | 134 ++++++++++++++++++
 .../arch/riscv/sifive/u74/firmware.json       |  68 +++++++++
 .../arch/riscv/sifive/u74/generic.json        |  11 ++
 .../arch/riscv/sifive/u74/instructions.json   |  92 ++++++++++++
 .../arch/riscv/sifive/u74/memory.json         |  32 +++++
 .../arch/riscv/sifive/u74/microarch.json      |  57 ++++++++
 11 files changed, 561 insertions(+)
 create mode 100644 tools/perf/arch/riscv/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/generic.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json

-- 
2.35.1