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Message-Id: <20220624162159.3403541-1-niravkumar.l.rabara@intel.com>
Date: Sat, 25 Jun 2022 00:21:59 +0800
From: niravkumar.l.rabara@...el.com
To: dinguyen@...nel.org
Cc: devicetree@...r.kernel.org, krzysztof.kozlowski+dt@...aro.org,
linux-kernel@...r.kernel.org, niravkumar.l.rabara@...el.com,
robh+dt@...nel.org
Subject: [PATCHv3] arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
The clocks are not part of the SoC but provided on the board
(external oscillators). Moving them out of soc node.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
---
.../boot/dts/altera/socfpga_stratix10.dtsi | 56 +++++++++----------
.../dts/altera/socfpga_stratix10_socdk.dts | 10 ++--
.../altera/socfpga_stratix10_socdk_nand.dts | 10 ++--
3 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index aa2bba75265f..5c7d926d18f7 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -97,6 +97,34 @@ intc: interrupt-controller@...c1000 {
<0x0 0xfffc6000 0x0 0x2000>;
};
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -119,34 +147,6 @@ clkmgr: clock-controller@...10000 {
#clock-cells = <1>;
};
- clocks {
- cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- cb_intosc_ls_clk: cb-intosc-ls-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- f2s_free_clk: f2s-free-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- osc1: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- qspi_clk: qspi-clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
- };
-
gmac0: ethernet@...00000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 5159cd5771dc..48424e459f12 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
};
soc {
- clocks {
- osc1 {
- clock-frequency = <25000000>;
- };
- };
-
eccmgr {
sdmmca-ecc@...c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -113,6 +107,10 @@ &mmc {
bus-width = <4>;
};
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
index 0ab676c639a1..847a7c01f5af 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
};
soc {
- clocks {
- osc1 {
- clock-frequency = <25000000>;
- };
- };
-
eccmgr {
sdmmca-ecc@...c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -126,6 +120,10 @@ partition@...000 {
};
};
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
--
2.25.1
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