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Message-ID: <CAOnJCUKpru5s=ktUKj3k5-L1sh8FzTm4t18BcudFXKT4SHaftQ@mail.gmail.com>
Date:   Fri, 24 Jun 2022 09:51:40 -0700
From:   Atish Patra <atishp@...shpatra.org>
To:     Nikita Shubin <nikita.shubin@...uefel.me>
Cc:     Anup Patel <anup@...infault.org>,
        João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>, linux <linux@...ro.com>,
        Nikita Shubin <n.shubin@...ro.com>,
        Will Deacon <will@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 1/5] drivers/perf: riscv_pmu_sbi: perf format

On Fri, Jun 24, 2022 at 9:02 AM Nikita Shubin <nikita.shubin@...uefel.me> wrote:
>
> From: Nikita Shubin <n.shubin@...ro.com>
>
> Update driver to export formatting and event information to sysfs so it
> can be used by the perf user space tools with the syntaxes:
>
> perf stat -e cpu/event=0x05
> perf stat -e cpu/event=0x05,firmware=0x1/
>
> 63-bit is used to distinguish hardware events from firmware. Firmware
> events are defined by "RISC-V Supervisor Binary Interface
> Specification".
>
> perf stat -e cpu/event=0x05,firmware=0x1/
>
> is equivalent to
>
> perf stat -e r8000000000000005
>
> Inspired-by: João Mário Domingos <joao.mario@...nico.ulisboa.pt>
> Signed-off-by: Nikita Shubin <n.shubin@...ro.com>
> Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
> ---
>  drivers/perf/riscv_pmu_sbi.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index dca3537a8dcc..2b5861a10d8e 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -21,6 +21,25 @@
>  #include <asm/sbi.h>
>  #include <asm/hwcap.h>
>
> +PMU_FORMAT_ATTR(event, "config:0-62");

This format is used for raw events as well. Raw event data only
encodes 48 bits as per the SBI spec.
The RISCV_PMU_RAW_EVENT_MASK in the sbi.h is incorrect. I will send a fix.

> +PMU_FORMAT_ATTR(firmware, "config:63-63");
> +
> +static struct attribute *riscv_arch_formats_attr[] = {
> +       &format_attr_event.attr,
> +       &format_attr_firmware.attr,
> +       NULL,
> +};
> +
> +static struct attribute_group riscv_pmu_format_group = {
> +       .name = "format",
> +       .attrs = riscv_arch_formats_attr,
> +};
> +
> +static const struct attribute_group *riscv_pmu_attr_groups[] = {
> +       &riscv_pmu_format_group,
> +       NULL,
> +};
> +
>  union sbi_pmu_ctr_info {
>         unsigned long value;
>         struct {
> @@ -720,6 +739,7 @@ static int pmu_sbi_device_probe(struct platform_device *pdev)
>                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
>                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
>         }
> +       pmu->pmu.attr_groups = riscv_pmu_attr_groups;
>         pmu->num_counters = num_counters;
>         pmu->ctr_start = pmu_sbi_ctr_start;
>         pmu->ctr_stop = pmu_sbi_ctr_stop;
> --
> 2.35.1
>


-- 
Regards,
Atish

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