lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <CAFULd4byUDS6U527qLuh78KmvM2OWbtappDfxLSiT_iMUz8Ghw@mail.gmail.com>
Date:   Sat, 25 Jun 2022 09:37:19 +0200
From:   Uros Bizjak <ubizjak@...il.com>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     LKML <linux-kernel@...r.kernel.org>, kvm@...r.kernel.org
Subject: Re: [PATCH] KVM: nVMX: clean up posted interrupt descriptor try_cmpxchg

On Fri, Jun 24, 2022 at 5:45 PM Paolo Bonzini <pbonzini@...hat.com> wrote:
>
> Rely on try_cmpxchg64 for re-reading the PID on failure, using READ_ONCE
> only right before the first iteration.
>
> Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>
> ---
>  arch/x86/kvm/vmx/posted_intr.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c
> index 73f60aa480fe..1b56c5e5c9fb 100644
> --- a/arch/x86/kvm/vmx/posted_intr.c
> +++ b/arch/x86/kvm/vmx/posted_intr.c
> @@ -34,7 +34,7 @@ static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
>         return &(to_vmx(vcpu)->pi_desc);
>  }
>
> -static int pi_try_set_control(struct pi_desc *pi_desc, u64 old, u64 new)
> +static int pi_try_set_control(struct pi_desc *pi_desc, u64 *pold, u64 new)
>  {
>         /*
>          * PID.ON can be set at any time by a different vCPU or by hardware,
> @@ -42,7 +42,7 @@ static int pi_try_set_control(struct pi_desc *pi_desc, u64 old, u64 new)
>          * update must be retried with a fresh snapshot an ON change causes
>          * the cmpxchg to fail.
>          */
> -       if (!try_cmpxchg64(&pi_desc->control, &old, new))
> +       if (!try_cmpxchg64(&pi_desc->control, pold, new))
>                 return -EBUSY;
>
>         return 0;
> @@ -96,8 +96,9 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
>         if (!x2apic_mode)
>                 dest = (dest << 8) & 0xFF00;
>
> +       old.control = READ_ONCE(pi_desc->control);
>         do {
> -               old.control = new.control = READ_ONCE(pi_desc->control);
> +               new.control = old.control;
>
>                 /*
>                  * Clear SN (as above) and refresh the destination APIC ID to
> @@ -111,7 +112,7 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
>                  * descriptor was modified on "put" to use the wakeup vector.
>                  */
>                 new.nv = POSTED_INTR_VECTOR;
> -       } while (pi_try_set_control(pi_desc, old.control, new.control));
> +       } while (pi_try_set_control(pi_desc, &old.control, new.control));
>
>         local_irq_restore(flags);
>
> @@ -156,12 +157,12 @@ static void pi_enable_wakeup_handler(struct kvm_vcpu *vcpu)
>
>         WARN(pi_desc->sn, "PI descriptor SN field set before blocking");
>
> +       old.control = READ_ONCE(pi_desc->control);
>         do {
> -               old.control = new.control = READ_ONCE(pi_desc->control);
> -
>                 /* set 'NV' to 'wakeup vector' */
> +               new.control = old.control;

This assignment should be above the comment, similar to vmx_vcpu_pi_load.

Uros.
>                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
> -       } while (pi_try_set_control(pi_desc, old.control, new.control));
> +       } while (pi_try_set_control(pi_desc, &old.control, new.control));
>
>         /*
>          * Send a wakeup IPI to this CPU if an interrupt may have been posted
> --
> 2.31.1
>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ