linux-kernel - Re: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver

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Message-ID: <CA+V-a8tKfGngEz51+Gw_3wK7zNzuw4Ubfm0zEB-jQJijS8f+2g@mail.gmail.com>
Date:   Sat, 25 Jun 2022 20:26:43 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Thomas Gleixner <tglx@...utronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <brgl@...ev.pl>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-tegra <linux-tegra@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Phil Edworthy <phil.edworthy@...esas.com>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver

Hi Marc,

On Sat, Jun 25, 2022 at 5:09 PM Marc Zyngier <maz@...nel.org> wrote:
>
> On Sat, 25 Jun 2022 13:48:08 +0100,
> "Lad, Prabhakar" <prabhakar.csengg@...il.com> wrote:
> >
> > Hi Marc,
> >
> > On Sat, Jun 25, 2022 at 1:08 PM Marc Zyngier <maz@...nel.org> wrote:
> > >
> > > On Sat, 25 Jun 2022 11:54:44 +0100,
> > > "Lad, Prabhakar" <prabhakar.csengg@...il.com> wrote:
> > > >
> > > > Hi Marc,
> > > >
> > > > Thank you for the review.
> > > >
> > > > On Sat, Jun 25, 2022 at 10:30 AM Marc Zyngier <maz@...nel.org> wrote:
> > > > >
> > > > > On Mon, 23 May 2022 18:42:35 +0100,
> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > > > >
> > >
> > > [...]
> > >
> > > > > > +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
> > > > > > +                         unsigned int nr_irqs, void *arg)
> > > > > > +{
> > > > > > +     struct rzg2l_irqc_priv *priv = domain->host_data;
> > > > > > +     unsigned long *chip_data = NULL;
> > > > >
> > > > > Why the init to NULL?
> > > > >
> > > > Can be dropped.
> > > >
> > > > > > +     struct irq_fwspec spec;
> > > > > > +     irq_hw_number_t hwirq;
> > > > > > +     int tint = -EINVAL;
> > > > > > +     unsigned int type;
> > > > > > +     unsigned int i;
> > > > > > +     int ret;
> > > > > > +
> > > > > > +     ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
> > > > > > +     if (ret)
> > > > > > +             return ret;
> > > > > > +
> > > > > > +     /*
> > > > > > +      * For TINT interrupts ie where pinctrl driver is child of irqc domain
> > > > > > +      * the hwirq and TINT are encoded in fwspec->param[0].
> > > > > > +      * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
> > > > > > +      * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
> > > > > > +      * in IRQC registers to enable a given gpio pin as interrupt.
> > > > > > +      */
> > > > > > +     if (hwirq > IRQC_IRQ_COUNT) {
> > > > > > +             tint = TINT_EXTRACT_GPIOINT(hwirq);
> > > > > > +             hwirq = TINT_EXTRACT_HWIRQ(hwirq);
> > > > > > +
> > > > > > +             if (hwirq < IRQC_TINT_START)
> > > > > > +                     return -EINVAL;
> > > > > > +     }
> > > > > > +
> > > > > > +     if (hwirq > (IRQC_NUM_IRQ - 1))
> > > > > > +             return -EINVAL;
> > > > > > +
> > > > > > +     chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> > > > >
> > > > > Are we really allocating an unsigned long for something that already
> > > > > fits in something that is pointer-sized?
> > > > >
> > > > I think I received some feedback to use unsigned long.  Let me know
> > > > what you want me to use here.
> > >
> > > I think this is just a waste of memory, but I don't really care.
> > >
> > Is there any better way I can handle it?
>
> How about (shock, horror) a cast?
>
Right I get you now..

> >
> > > >
> > > > > > +     if (!chip_data)
> > > > > > +             return -ENOMEM;
> > > > > > +     *chip_data = tint;
> > > > >
> > > > > So here, *chip_data can be set to -EINVAL if hwirq <= IRQC_IRQ_COUNT?
> > > > > This can't be right.
> > > > >
> > > > Yes *chip_data can be -EINVAL. IRQC block handles IRQ0-7 and
> > > > GPIOINT0-122. So the -EINVAL here is for IRQ0-7 case were dont
> > > > required the chip data in the call backs hence -EINVAL, Whereas for
> > > > GPIOINT0-122 we need chip_data in the callbacks as this value needs to
> > > > be programmed in the hardware registers.
> > >
> > > I can't see anything that checks it (let alone the difference in
> > > types). And if it isn't checked, this means that the allocation is
> > > pointless.
> > >
> > There are checks for example below:
> >
> > static void rzg2l_irqc_irq_enable(struct irq_data *d)
> > {
> >     unsigned int hw_irq = irqd_to_hwirq(d);
> >
> >     if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> >         struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> >         unsigned long chip_data = *(unsigned long *)d->chip_data;
> >         u32 offset = hw_irq - IRQC_TINT_START;
> >         u32 tssr_offset = TSSR_OFFSET(offset);
> >         u8 tssr_index = TSSR_INDEX(offset);
> >         u32 reg;
> >
> >         raw_spin_lock(&priv->lock);
> >         reg = readl_relaxed(priv->base + TSSR(tssr_index));
> >         reg |= (TIEN | chip_data) << TSSEL_SHIFT(tssr_offset);
> >         writel_relaxed(reg, priv->base + TSSR(tssr_index));
> >         raw_spin_unlock(&priv->lock);
> >     }
> >     irq_chip_enable_parent(d);
> > }
> >
> > This check hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ here
> > would mean its GPIOINT0-122 and then the chip data will be used.
>
> That doesn't check the content of chip_data if outside of this
> condition. Nonetheless, you allocate an unsigned long to store
> -EINVAL. Not only this is a pointless allocation, but you use it to
> store something that you never retrieve the first place. Don't you see
> the problem?
>
... and when using cast I no longer need the allocation.

Cheers,
Prabhakar