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Message-Id: <20220626004326.8548-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 26 Jun 2022 01:43:25 +0100
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Sagar Kadam <sagar.kadam@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org
Cc: Geert Uytterhoeven <geert+renesas@...der.be>,
linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
Document Renesas RZ/Five (R9A07G043) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
v1->v2:
* Fixed binding doc
* Fixed review comments pointed by Krzysztof.
RFC->v1:
* Fixed Review comments pointed by Geert and Rob
---
.../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..59df367d1e44 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -28,7 +28,10 @@ description:
While the PLIC supports both edge-triggered and level-triggered interrupts,
interrupt handlers are oblivious to this distinction and therefore it is not
- specified in the PLIC device-tree binding.
+ specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
+ but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
+ to specify the interrupt type as the flow for EDGE interrupts is different
+ compared to LEVEL interrupts.
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -57,6 +60,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - const: renesas,r9a07g043-plic
reg:
maxItems: 1
@@ -64,8 +68,7 @@ properties:
'#address-cells':
const: 0
- '#interrupt-cells':
- const: 1
+ '#interrupt-cells': true
interrupt-controller: true
@@ -82,6 +85,12 @@ properties:
description:
Specifies how many external interrupts are supported by this controller.
+ clocks: true
+
+ power-domains: true
+
+ resets: true
+
required:
- compatible
- '#address-cells'
@@ -91,6 +100,35 @@ required:
- interrupts-extended
- riscv,ndev
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g043-plic
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 2
+
+ required:
+ - clocks
+ - resets
+ - power-domains
+ else:
+ properties:
+ '#interrupt-cells':
+ const: 1
+
additionalProperties: false
examples:
--
2.25.1
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