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Message-Id: <20220627051257.38543-1-samuel@sholland.org>
Date: Mon, 27 Jun 2022 00:12:54 -0500
From: Samuel Holland <samuel@...lland.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Prabhakar <prabhakar.csengg@...il.com>,
Marc Zyngier <maz@...nel.org>,
Sagar Kadam <sagar.kadam@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>
Cc: linux-renesas-soc@...r.kernel.org, Guo Ren <guoren@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Thomas Gleixner <tglx@...utronix.de>,
Biju Das <biju.das.jz@...renesas.com>,
Samuel Holland <samuel@...lland.org>,
Albert Ou <aou@...s.berkeley.edu>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: [PATCH v1 0/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
This is a follow-up to the series "[PATCH v2 0/2] Add PLIC support for
Renesas RZ/Five SoC"[1].
The change made there is also needed for the already-supported T-HEAD
C9xx PLIC. So this binding change is necessary before I can send the
Allwinner D1 devicetree.
[1]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/
Changes in v1:
- Use a flag for enabling the changes instead of a variant ID
- Use handle_edge_irq instead of handle_fasteoi_ack_irq
- Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL
Samuel Holland (3):
dt-bindings: interrupt-controller: Require trigger type for T-HEAD
PLIC
irqchip/sifive-plic: Name the chip more generically
irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
.../sifive,plic-1.0.0.yaml | 31 ++++++-
drivers/irqchip/irq-sifive-plic.c | 91 +++++++++++++++++--
2 files changed, 108 insertions(+), 14 deletions(-)
--
2.35.1
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