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Message-ID: <9cdf2ca0-4f86-09b0-8834-c0c39eb70054@baylibre.com>
Date: Mon, 27 Jun 2022 09:01:01 +0200
From: Neil Armstrong <narmstrong@...libre.com>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: dri-devel@...ts.freedesktop.org, linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Jagan Teki <jagan@...rulasolutions.com>
Subject: Re: [PATCH v3 6/6] drm/meson: add support for MIPI-DSI transceiver
Hi,
On 27/06/2022 00:32, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Fri, Jun 17, 2022 at 9:27 AM Neil Armstrong <narmstrong@...libre.com> wrote:
>> +/* [31:16] RW intr_stat/clr. Default 0.
>> + * For each bit, read as this interrupt level status,
>> + * write 1 to clear.
> Do you know if an interrupt line from GIC is routed to the MIPI-DSI
> transceiver? If so, we should make it mandatory in patch #1 of this
> series (dt-bindings patch), even though it's not in use by the driver
> at the moment.
Probably yes, let me check
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