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Message-ID: <2111b4a7-d195-0333-1d43-02fcd91f89e2@collabora.com>
Date: Mon, 27 Jun 2022 09:44:50 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
David Heidelberg <david.heidelberg@...labora.com>
Cc: krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com,
mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
y.oudjana@...tonmail.com, jason-jh.lin@...iatek.com,
ck.hu@...iatek.com, fparent@...libre.com, rex-bc.chen@...iatek.com,
tinghan.shen@...iatek.com, chun-jie.chen@...iatek.com,
weiyi.lu@...iatek.com, ikjn@...omium.org, miles.chen@...iatek.com,
sam.shih@...iatek.com, wenst@...omium.org,
bgolaszewski@...libre.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
konrad.dybcio@...ainline.org, marijn.suijten@...ainline.org,
martin.botka@...ainline.org, ~postmarketos/upstreaming@...ts.sr.ht,
phone-devel@...r.kernel.org, paul.bouchara@...ainline.org,
kernel@...labora.com
Subject: Re: [PATCH v3 4/7] dt-bindings: clock: mediatek: Add clock driver
bindings for MT6795
Il 26/06/22 12:31, Krzysztof Kozlowski ha scritto:
> On 26/06/2022 11:47, David Heidelberg wrote:
>> On 25/06/2022 22:29, Krzysztof Kozlowski wrote:
>>> On 24/06/2022 11:35, AngeloGioacchino Del Regno wrote:
>>>> Add the bindings for the clock drivers of the MediaTek Helio X10
>>>> MT6795 SoC.
>>>>
>>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
>>>> ---
>>>> .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++
>>>> .../clock/mediatek,mt6795-sys-clock.yaml | 74 +++++++++++++++++++
>>>> 2 files changed, 140 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml
>>>> new file mode 100644
>>>> index 000000000000..795fb18721c3
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml
>>>> @@ -0,0 +1,66 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#"
>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>> +
>>>> +title: MediaTek Functional Clock Controller for MT6795
>>>> +
>>>> +maintainers:
>>>> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
>>>> + - Chun-Jie Chen <chun-jie.chen@...iatek.com>
>>>> +
>>>> +description: |
>>>> + The clock architecture in MediaTek like below
>>>> + PLLs -->
>>>> + dividers -->
>>>> + muxes
>>>> + -->
>>>> + clock gate
>>>> +
>>>> + The devices provide clock gate control in different IP blocks.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + enum:
>>>> + - mediatek,mt6795-mfgcfg
>>>> + - mediatek,mt6795-vdecsys
>>>> + - mediatek,mt6795-vencsys
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + '#clock-cells':
>>>> + const: 1
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - '#clock-cells'
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + soc {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> +
>>>> + mfgcfg: clock-controller@...00000 {
>>>> + compatible = "mediatek,mt6795-mfgcfg";
>>>> + reg = <0 0x13000000 0 0x1000>;
>>>> + #clock-cells = <1>;
>>>> + };
>>>> +
>>>> + vdecsys: clock-controller@...00000 {
>>>> + compatible = "mediatek,mt6795-vdecsys";
>>>> + reg = <0 0x16000000 0 0x1000>;
>>>> + #clock-cells = <1>;
>>>> + };
>>>> +
>>>> + vencsys: clock-controller@...00000 {
>>>> + compatible = "mediatek,mt6795-vencsys";
>>>> + reg = <0 0x18000000 0 0x1000>;
>>>> + #clock-cells = <1>;
>>>> + };
>>>> + };
>>>> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml
>>>> new file mode 100644
>>>> index 000000000000..44b96af9ceaf
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml
>>>> @@ -0,0 +1,74 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: "http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#"
>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>> +
>>>> +title: MediaTek System Clock Controller for MT6795
>>>> +
>>>> +maintainers:
>>>> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
>>>> + - Chun-Jie Chen <chun-jie.chen@...iatek.com>
>>>> +
>>>> +description:
>>>> + The Mediatek system clock controller provides various clocks and system configuration
>>> Wrap according to Linux coding convention, so at 80.
>>
>> What I understood that 100 length was agreed [1] as a limit. I haven't
>> noticed any recent change regarding to line length.
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bdc48fa11e46f867ea4d75fa59ee87a7f48be144
>
> The coding style (also in change above) clearly states:
> "The preferred limit on the length of a single line is 80 columns."
> Just read the first line of new diff/hunk...
>
> checkpatch was indeed long time converted not to complain on 80 but on
> 100, but that does not change coding style. The point of that was only
> to accept 100 wrapping when it is beneficial, iow, it increases the
> code readability.
>
> It's not the case here and coding style clearly asks for 80. Wrap at 80.
>
Hello David, Krzysztof,
there's no problem at all, I can resend... after all, it's a fast fix and
all it takes is 10 minutes of my time!
Cheers,
Angelo
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