linux-kernel - [PATCH v12 01/10] dt-bindings: mediatek,dp: Add Display Port binding

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Message-ID: <20220627080341.5087-2-rex-bc.chen@mediatek.com>
Date:   Mon, 27 Jun 2022 16:03:32 +0800
From:   Bo-Chen Chen <rex-bc.chen@...iatek.com>
To:     <chunkuang.hu@...nel.org>, <p.zabel@...gutronix.de>,
        <daniel@...ll.ch>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mripard@...nel.org>,
        <tzimmermann@...e.de>, <matthias.bgg@...il.com>, <deller@....de>,
        <airlied@...ux.ie>
CC:     <msp@...libre.com>, <granquet@...libre.com>,
        <jitao.shi@...iatek.com>, <wenst@...omium.org>,
        <angelogioacchino.delregno@...labora.com>, <ck.hu@...iatek.com>,
        <dri-devel@...ts.freedesktop.org>,
        <linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-fbdev@...r.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Bo-Chen Chen <rex-bc.chen@...iatek.com>
Subject: [PATCH v12 01/10] dt-bindings: mediatek,dp: Add Display Port binding

From: Markus Schneider-Pargmann <msp@...libre.com>

This controller is present on several mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional difference,
so only one compatible field is added.

The controller can have two forms, as a normal display port and as an
embedded display port.

Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
[Bo-Chen: Fix reviewers' comment]
Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
---
 .../display/mediatek/mediatek,dp.yaml         | 108 ++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
new file mode 100644
index 000000000000..1a16545b6afa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Port Controller
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@...nel.org>
+  - Jitao shi <jitao.shi@...iatek.com>
+
+description: |
+  Device tree bindings for the MediaTek display port and
+  embedded display port controller present on some MediaTek SoCs.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8195-dp-tx
+      - mediatek,mt8195-edp-tx
+
+  reg:
+    maxItems: 1
+
+  nvmem-cells:
+    maxItems: 1
+    description: efuse data for display port calibration
+
+  nvmem-cell-names:
+    const: dp_calibration_data
+
+  power-domains:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input endpoint of the controller, usually dp_intf
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output endpoint of the controller
+
+    required:
+      - port@0
+      - port@1
+
+  data-lanes:
+    $ref: /schemas/media/video-interfaces.yaml#
+    description: |
+      number of lanes supported by the hardware.
+      The possible values:
+      0       - For 1 lane enabled in IP.
+      0 1     - For 2 lanes enabled in IP.
+      0 1 2 3 - For 4 lanes enabled in IP.
+    minItems: 1
+    maxItems: 4
+
+  max-linkrate-mhz:
+    enum: [ 1620, 2700, 5400, 8100 ]
+    description: maximum link rate supported by the hardware.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ports
+  - data-lanes
+  - max-linkrate-mhz
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/mt8195-power.h>
+    dp_tx@...00000 {
+        compatible = "mediatek,mt8195-dp-tx";
+        reg = <0x1c600000 0x8000>;
+        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+        data-lanes = <0 1 2 3>;
+        max-linkrate-mhz = <8100>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                edp_in: endpoint {
+                    remote-endpoint = <&dp_intf0_out>;
+                };
+            };
+            port@1 {
+                reg = <1>;
+                edp_out: endpoint {
+                    remote-endpoint = <&panel_in>;
+                };
+            };
+        };
+    };
-- 
2.18.0