linux-kernel - [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU

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Message-Id: <20220628114625.166665-1-nikita.shubin@maquefel.me>
Date:   Tue, 28 Jun 2022 14:45:54 +0300
From:   Nikita Shubin <nikita.shubin@...uefel.me>
To:     unlisted-recipients:; (no To-header on input)
Cc:     linux@...ro.com, Genevieve Chan <genevieve.chan@...rfivetech.com>,
        João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>,
        Nikita Shubin <n.shubin@...ro.com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Anup Patel <anup@...infault.org>, Jiri Olsa <jolsa@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, linux-riscv@...ts.infradead.org,
        Mark Rutland <mark.rutland@....com>,
        Namhyung Kim <namhyung@...nel.org>
Subject: [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU

From: Nikita Shubin <n.shubin@...ro.com>

From: Nikita Shubin <n.shubin@...ro.com>

This series aims to provide matching vendor SoC with corresponded JSON bindings.

The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example 
for Sifive Unmatched the corresponding string will be:

0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core

Where MIMPID can vary as all impl supported the same number of events, this might not 
be true for all future SoC however.

Also added SBI firmware events pretty names, as any firmware that supports SBI PMU 
should also support firmare events [1].

Series depends on patch by Anup Patel, exposing mvendor, marchid and mimpid 
to "/proc/cpuinfo" [2].

[1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] https://lkml.org/lkml/2022/6/20/498

Link to previous version:
https://patchwork.kernel.org/project/linux-riscv/list/?series=653649

See original cover letter by João Mário Domingos:
https://patchwork.kernel.org/project/linux-riscv/cover/20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt/

Tested with the following OpenSBI device tree bindings:

```
pmu {
	compatible = "riscv,pmu";
	riscv,event-to-mhpmcounters =
		<0x03 0x06 0x18
		0x10001 0x10002 0x18
		0x10009 0x10009 0x18
		0x10011 0x10011 0x18
		0x10019 0x10019 0x18
		0x10021 0x10021 0x18>;
	riscv,event-to-mhpmevent =
		<0x03 0x00000000 0x1801
		0x04 0x00000000 0x0302
		0x05 0x00000000 0x4000
		0x06 0x00000000 0x6001
		0x10001 0x00000000 0x0202
		0x10002 0x00000000 0x0402
		0x10009 0x00000000 0x0102
		0x10011 0x00000000 0x2002
		0x10019 0x00000000 0x1002
		0x10021 0x00000000 0x0802>;
	riscv,raw-event-to-mhpmcounters =
		<0x00000000 0x03ffff00 0x0 0x0 0x18
		0x00000000 0x0007ff01 0x0 0x1 0x18
		0x00000000 0x00003f02 0x0 0x2 0x18>;
};
```
---
v4->v5:
Atish Patra:
	- dropped cycle, time instret std arch events
	- format config is now 48-bit wide
Arnaldo Carvalho de Melo:
	- fixed cpuid leakage
	- no "if" before free
Will Deacon:
	- simply use "config:63"
---
Nikita Shubin (4):
  drivers/perf: riscv_pmu_sbi: perf format
  perf tools riscv: Add support for get_cpuid_str function
  perf arch events: riscv sbi firmware std event files
  perf vendor events riscv: add Sifive U74 JSON file

 drivers/perf/riscv_pmu_sbi.c                  |  20 +++
 tools/perf/arch/riscv/util/Build              |   1 +
 tools/perf/arch/riscv/util/header.c           | 106 ++++++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  17 +++
 .../arch/riscv/riscv-sbi-firmware.json        | 134 ++++++++++++++++++
 .../arch/riscv/sifive/u74/firmware.json       |  68 +++++++++
 .../arch/riscv/sifive/u74/instructions.json   |  92 ++++++++++++
 .../arch/riscv/sifive/u74/memory.json         |  32 +++++
 .../arch/riscv/sifive/u74/microarch.json      |  57 ++++++++
 9 files changed, 527 insertions(+)
 create mode 100644 tools/perf/arch/riscv/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json

-- 
2.30.2