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Message-Id: <20220628122255.24265-6-rogerq@kernel.org>
Date: Tue, 28 Jun 2022 15:22:53 +0300
From: Roger Quadros <rogerq@...nel.org>
To: kishon@...com, vkoul@...nel.org
Cc: vigneshr@...com, t-patil@...com, sjakhade@...ence.com,
s-vadapalli@...com, linux-phy@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Roger Quadros <rogerq@...nel.org>,
Rob Herring <robh@...nel.org>
Subject: [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
ti,j7200-wiz-10g supports an additional reference clock.
Add compatible and the additional clock.
Cc: Rob Herring <robh@...nel.org>
Signed-off-by: Roger Quadros <rogerq@...nel.org>
---
.../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3127bb648427..8305654b66c9 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -16,19 +16,23 @@ properties:
- ti,j721e-wiz-16g
- ti,j721e-wiz-10g
- ti,am64-wiz-10g
+ - ti,j7200-wiz-10g
power-domains:
maxItems: 1
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
description: clock-specifier to represent input to the WIZ
clock-names:
+ minItems: 3
items:
- const: fck
- const: core_ref_clk
- const: ext_ref_clk
+ - const: core_ref1_clk
num-lanes:
minimum: 1
@@ -106,6 +110,11 @@ properties:
- assigned-clocks
- assigned-clock-parents
+ ti,scm:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to System Control Module for syscon regmap access.
+
patternProperties:
"^pll[0|1]-refclk$":
type: object
@@ -173,6 +182,16 @@ required:
- "#reset-cells"
- ranges
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j7200-wiz-10g
+ then:
+ required:
+ - ti,scm
+
additionalProperties: false
examples:
--
2.17.1
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